hw/block/nvme: add broadcast nsid support flush command
Add support for using the broadcast nsid to issue a flush on all namespaces through a single command. Signed-off-by: Gollu Appalanaidu <anaidu.gollu@samsung.com> Reviewed-by: Klaus Jensen <k.jensen@samsung.com> Acked-by: Stefan Hajnoczi <stefanha@redhat.com> Acked-by: Keith Busch <kbusch@kernel.org> Signed-off-by: Klaus Jensen <k.jensen@samsung.com>
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594a2b742b
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c94973288c
116
hw/block/nvme.c
116
hw/block/nvme.c
@ -1466,6 +1466,41 @@ static void nvme_rw_cb(void *opaque, int ret)
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nvme_enqueue_req_completion(nvme_cq(req), req);
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}
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struct nvme_aio_flush_ctx {
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NvmeRequest *req;
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NvmeNamespace *ns;
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BlockAcctCookie acct;
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};
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static void nvme_aio_flush_cb(void *opaque, int ret)
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{
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struct nvme_aio_flush_ctx *ctx = opaque;
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NvmeRequest *req = ctx->req;
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uintptr_t *num_flushes = (uintptr_t *)&req->opaque;
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BlockBackend *blk = ctx->ns->blkconf.blk;
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BlockAcctCookie *acct = &ctx->acct;
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BlockAcctStats *stats = blk_get_stats(blk);
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trace_pci_nvme_aio_flush_cb(nvme_cid(req), blk_name(blk));
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if (!ret) {
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block_acct_done(stats, acct);
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} else {
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block_acct_failed(stats, acct);
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nvme_aio_err(req, ret);
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}
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(*num_flushes)--;
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g_free(ctx);
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if (*num_flushes) {
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return;
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}
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nvme_enqueue_req_completion(nvme_cq(req), req);
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}
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static void nvme_aio_discard_cb(void *opaque, int ret)
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{
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NvmeRequest *req = opaque;
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@ -1949,10 +1984,56 @@ static uint16_t nvme_compare(NvmeCtrl *n, NvmeRequest *req)
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static uint16_t nvme_flush(NvmeCtrl *n, NvmeRequest *req)
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{
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uint32_t nsid = le32_to_cpu(req->cmd.nsid);
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uintptr_t *num_flushes = (uintptr_t *)&req->opaque;
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uint16_t status;
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struct nvme_aio_flush_ctx *ctx;
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NvmeNamespace *ns;
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trace_pci_nvme_flush(nvme_cid(req), nsid);
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if (nsid != NVME_NSID_BROADCAST) {
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req->ns = nvme_ns(n, nsid);
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if (unlikely(!req->ns)) {
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return NVME_INVALID_FIELD | NVME_DNR;
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}
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block_acct_start(blk_get_stats(req->ns->blkconf.blk), &req->acct, 0,
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BLOCK_ACCT_FLUSH);
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req->aiocb = blk_aio_flush(req->ns->blkconf.blk, nvme_rw_cb, req);
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return NVME_NO_COMPLETE;
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}
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/* 1-initialize; see comment in nvme_dsm */
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*num_flushes = 1;
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for (int i = 1; i <= n->num_namespaces; i++) {
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ns = nvme_ns(n, i);
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if (!ns) {
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continue;
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}
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ctx = g_new(struct nvme_aio_flush_ctx, 1);
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ctx->req = req;
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ctx->ns = ns;
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(*num_flushes)++;
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block_acct_start(blk_get_stats(ns->blkconf.blk), &ctx->acct, 0,
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BLOCK_ACCT_FLUSH);
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blk_aio_flush(ns->blkconf.blk, nvme_aio_flush_cb, ctx);
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}
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/* account for the 1-initialization */
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(*num_flushes)--;
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if (*num_flushes) {
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status = NVME_NO_COMPLETE;
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} else {
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status = req->status;
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}
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return status;
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}
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static uint16_t nvme_read(NvmeCtrl *n, NvmeRequest *req)
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@ -2608,6 +2689,29 @@ static uint16_t nvme_io_cmd(NvmeCtrl *n, NvmeRequest *req)
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return NVME_INVALID_NSID | NVME_DNR;
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}
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/*
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* In the base NVM command set, Flush may apply to all namespaces
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* (indicated by NSID being set to 0xFFFFFFFF). But if that feature is used
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* along with TP 4056 (Namespace Types), it may be pretty screwed up.
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*
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* If NSID is indeed set to 0xFFFFFFFF, we simply cannot associate the
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* opcode with a specific command since we cannot determine a unique I/O
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* command set. Opcode 0x0 could have any other meaning than something
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* equivalent to flushing and say it DOES have completely different
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* semantics in some other command set - does an NSID of 0xFFFFFFFF then
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* mean "for all namespaces, apply whatever command set specific command
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* that uses the 0x0 opcode?" Or does it mean "for all namespaces, apply
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* whatever command that uses the 0x0 opcode if, and only if, it allows
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* NSID to be 0xFFFFFFFF"?
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*
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* Anyway (and luckily), for now, we do not care about this since the
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* device only supports namespace types that includes the NVM Flush command
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* (NVM and Zoned), so always do an NVM Flush.
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*/
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if (req->cmd.opcode == NVME_CMD_FLUSH) {
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return nvme_flush(n, req);
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}
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req->ns = nvme_ns(n, nsid);
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if (unlikely(!req->ns)) {
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return NVME_INVALID_FIELD | NVME_DNR;
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@ -2619,8 +2723,6 @@ static uint16_t nvme_io_cmd(NvmeCtrl *n, NvmeRequest *req)
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}
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switch (req->cmd.opcode) {
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case NVME_CMD_FLUSH:
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return nvme_flush(n, req);
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case NVME_CMD_WRITE_ZEROES:
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return nvme_write_zeroes(n, req);
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case NVME_CMD_ZONE_APPEND:
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@ -4750,7 +4852,15 @@ static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice *pci_dev)
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NVME_ONCS_FEATURES | NVME_ONCS_DSM |
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NVME_ONCS_COMPARE | NVME_ONCS_COPY);
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id->vwc = (0x2 << 1) | 0x1;
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/*
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* NOTE: If this device ever supports a command set that does NOT use 0x0
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* as a Flush-equivalent operation, support for the broadcast NSID in Flush
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* should probably be removed.
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*
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* See comment in nvme_io_cmd.
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*/
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id->vwc = NVME_VWC_NSID_BROADCAST_SUPPORT | NVME_VWC_PRESENT;
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id->ocfs = cpu_to_le16(NVME_OCFS_COPY_FORMAT_0);
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id->sgls = cpu_to_le32(NVME_CTRL_SGLS_SUPPORT_NO_ALIGN |
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NVME_CTRL_SGLS_BITBUCKET);
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@ -40,6 +40,7 @@ pci_nvme_map_prp(uint64_t trans_len, uint32_t len, uint64_t prp1, uint64_t prp2,
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pci_nvme_map_sgl(uint16_t cid, uint8_t typ, uint64_t len) "cid %"PRIu16" type 0x%"PRIx8" len %"PRIu64""
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pci_nvme_io_cmd(uint16_t cid, uint32_t nsid, uint16_t sqid, uint8_t opcode, const char *opname) "cid %"PRIu16" nsid %"PRIu32" sqid %"PRIu16" opc 0x%"PRIx8" opname '%s'"
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pci_nvme_admin_cmd(uint16_t cid, uint16_t sqid, uint8_t opcode, const char *opname) "cid %"PRIu16" sqid %"PRIu16" opc 0x%"PRIx8" opname '%s'"
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pci_nvme_flush(uint16_t cid, uint32_t nsid) "cid %"PRIu16" nsid %"PRIu32""
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pci_nvme_read(uint16_t cid, uint32_t nsid, uint32_t nlb, uint64_t count, uint64_t lba) "cid %"PRIu16" nsid %"PRIu32" nlb %"PRIu32" count %"PRIu64" lba 0x%"PRIx64""
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pci_nvme_write(uint16_t cid, const char *verb, uint32_t nsid, uint32_t nlb, uint64_t count, uint64_t lba) "cid %"PRIu16" opname '%s' nsid %"PRIu32" nlb %"PRIu32" count %"PRIu64" lba 0x%"PRIx64""
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pci_nvme_rw_cb(uint16_t cid, const char *blkname) "cid %"PRIu16" blk '%s'"
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@ -55,6 +56,7 @@ pci_nvme_compare_cb(uint16_t cid) "cid %"PRIu16""
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pci_nvme_aio_discard_cb(uint16_t cid) "cid %"PRIu16""
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pci_nvme_aio_copy_in_cb(uint16_t cid) "cid %"PRIu16""
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pci_nvme_aio_zone_reset_cb(uint16_t cid, uint64_t zslba) "cid %"PRIu16" zslba 0x%"PRIx64""
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pci_nvme_aio_flush_cb(uint16_t cid, const char *blkname) "cid %"PRIu16" blk '%s'"
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pci_nvme_create_sq(uint64_t addr, uint16_t sqid, uint16_t cqid, uint16_t qsize, uint16_t qflags) "create submission queue, addr=0x%"PRIx64", sqid=%"PRIu16", cqid=%"PRIu16", qsize=%"PRIu16", qflags=%"PRIu16""
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pci_nvme_create_cq(uint64_t addr, uint16_t cqid, uint16_t vector, uint16_t size, uint16_t qflags, int ien) "create completion queue, addr=0x%"PRIx64", cqid=%"PRIu16", vector=%"PRIu16", qsize=%"PRIu16", qflags=%"PRIu16", ien=%d"
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pci_nvme_del_sq(uint16_t qid) "deleting submission queue sqid=%"PRIu16""
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@ -1062,6 +1062,14 @@ enum NvmeIdCtrlOcfs {
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NVME_OCFS_COPY_FORMAT_0 = 1 << 0,
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};
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enum NvmeIdctrlVwc {
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NVME_VWC_PRESENT = 1 << 0,
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NVME_VWC_NSID_BROADCAST_NO_SUPPORT = 0 << 1,
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NVME_VWC_NSID_BROADCAST_RESERVED = 1 << 1,
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NVME_VWC_NSID_BROADCAST_CTRL_SPEC = 2 << 1,
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NVME_VWC_NSID_BROADCAST_SUPPORT = 3 << 1,
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};
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enum NvmeIdCtrlFrmw {
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NVME_FRMW_SLOT1_RO = 1 << 0,
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};
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