docs: Add skeletal documentation of highbank and midway
Add skeletal documentation for the highbank and midway machines. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210713142226.19155-4-peter.maydell@linaro.org
This commit is contained in:
parent
3f65df38e8
commit
c90df7ce4e
@ -643,6 +643,7 @@ L: qemu-arm@nongnu.org
|
||||
S: Odd Fixes
|
||||
F: hw/arm/highbank.c
|
||||
F: hw/net/xgmac.c
|
||||
F: docs/system/arm/highbank.rst
|
||||
|
||||
Canon DIGIC
|
||||
M: Antony Pavlov <antonynpavlov@gmail.com>
|
||||
|
19
docs/system/arm/highbank.rst
Normal file
19
docs/system/arm/highbank.rst
Normal file
@ -0,0 +1,19 @@
|
||||
Calxeda Highbank and Midway (``highbank``, ``midway``)
|
||||
======================================================
|
||||
|
||||
``highbank`` is a model of the Calxeda Highbank (ECX-1000) system,
|
||||
which has four Cortex-A9 cores.
|
||||
|
||||
``midway`` is a model of the Calxeda Midway (ECX-2000) system,
|
||||
which has four Cortex-A15 cores.
|
||||
|
||||
Emulated devices:
|
||||
|
||||
- L2x0 cache controller
|
||||
- SP804 dual timer
|
||||
- PL011 UART
|
||||
- PL061 GPIOs
|
||||
- PL031 RTC
|
||||
- PL022 synchronous serial port controller
|
||||
- AHCI
|
||||
- XGMAC ethernet controllers
|
@ -87,6 +87,7 @@ undocumented; you can get a complete list by running
|
||||
arm/digic
|
||||
arm/cubieboard
|
||||
arm/emcraft-sf2
|
||||
arm/highbank
|
||||
arm/musicpal
|
||||
arm/gumstix
|
||||
arm/nrf
|
||||
|
Loading…
Reference in New Issue
Block a user