i.MX: Add the Freescale SPI Controller
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Jean-Christophe DUBOIS
Peter Maydell
parent
53374b16a2
commit
c906a3a015
@ -4,3 +4,4 @@ common-obj-$(CONFIG_XILINX_SPI) += xilinx_spi.o
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common-obj-$(CONFIG_XILINX_SPIPS) += xilinx_spips.o
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obj-$(CONFIG_OMAP) += omap_spi.o
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obj-$(CONFIG_IMX) += imx_spi.o
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454
hw/ssi/imx_spi.c
Normal file
454
hw/ssi/imx_spi.c
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@ -0,0 +1,454 @@
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/*
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* IMX SPI Controller
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*
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* Copyright (c) 2016 Jean-Christophe Dubois <jcd@tribudubois.net>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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*/
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#include "qemu/osdep.h"
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#include "hw/ssi/imx_spi.h"
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#include "sysemu/sysemu.h"
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#ifndef DEBUG_IMX_SPI
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#define DEBUG_IMX_SPI 0
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#endif
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#define DPRINTF(fmt, args...) \
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do { \
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if (DEBUG_IMX_SPI) { \
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fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_SPI, \
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__func__, ##args); \
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} \
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} while (0)
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static char const *imx_spi_reg_name(uint32_t reg)
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{
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static char unknown[20];
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switch (reg) {
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case ECSPI_RXDATA:
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return "ECSPI_RXDATA";
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case ECSPI_TXDATA:
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return "ECSPI_TXDATA";
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case ECSPI_CONREG:
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return "ECSPI_CONREG";
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case ECSPI_CONFIGREG:
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return "ECSPI_CONFIGREG";
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case ECSPI_INTREG:
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return "ECSPI_INTREG";
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case ECSPI_DMAREG:
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return "ECSPI_DMAREG";
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case ECSPI_STATREG:
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return "ECSPI_STATREG";
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case ECSPI_PERIODREG:
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return "ECSPI_PERIODREG";
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case ECSPI_TESTREG:
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return "ECSPI_TESTREG";
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case ECSPI_MSGDATA:
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return "ECSPI_MSGDATA";
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default:
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sprintf(unknown, "%d ?", reg);
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return unknown;
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}
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}
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static const VMStateDescription vmstate_imx_spi = {
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.name = TYPE_IMX_SPI,
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_FIFO32(tx_fifo, IMXSPIState),
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VMSTATE_FIFO32(rx_fifo, IMXSPIState),
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VMSTATE_INT16(burst_length, IMXSPIState),
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VMSTATE_UINT32_ARRAY(regs, IMXSPIState, ECSPI_MAX),
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VMSTATE_END_OF_LIST()
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},
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};
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static void imx_spi_txfifo_reset(IMXSPIState *s)
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{
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fifo32_reset(&s->tx_fifo);
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s->regs[ECSPI_STATREG] |= ECSPI_STATREG_TE;
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s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_TF;
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}
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static void imx_spi_rxfifo_reset(IMXSPIState *s)
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{
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fifo32_reset(&s->rx_fifo);
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s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_RR;
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s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_RF;
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s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_RO;
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}
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static void imx_spi_update_irq(IMXSPIState *s)
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{
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int level;
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if (fifo32_is_empty(&s->rx_fifo)) {
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s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_RR;
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} else {
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s->regs[ECSPI_STATREG] |= ECSPI_STATREG_RR;
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}
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if (fifo32_is_full(&s->rx_fifo)) {
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s->regs[ECSPI_STATREG] |= ECSPI_STATREG_RF;
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} else {
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s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_RF;
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}
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if (fifo32_is_empty(&s->tx_fifo)) {
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s->regs[ECSPI_STATREG] |= ECSPI_STATREG_TE;
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} else {
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s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_TE;
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}
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if (fifo32_is_full(&s->tx_fifo)) {
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s->regs[ECSPI_STATREG] |= ECSPI_STATREG_TF;
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} else {
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s->regs[ECSPI_STATREG] &= ~ECSPI_STATREG_TF;
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}
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level = s->regs[ECSPI_STATREG] & s->regs[ECSPI_INTREG] ? 1 : 0;
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qemu_set_irq(s->irq, level);
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DPRINTF("IRQ level is %d\n", level);
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}
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static uint8_t imx_spi_selected_channel(IMXSPIState *s)
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{
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return EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_CHANNEL_SELECT);
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}
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static uint32_t imx_spi_burst_length(IMXSPIState *s)
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{
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return EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_BURST_LENGTH) + 1;
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}
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static bool imx_spi_is_enabled(IMXSPIState *s)
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{
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return s->regs[ECSPI_CONREG] & ECSPI_CONREG_EN;
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}
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static bool imx_spi_channel_is_master(IMXSPIState *s)
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{
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uint8_t mode = EXTRACT(s->regs[ECSPI_CONREG], ECSPI_CONREG_CHANNEL_MODE);
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return (mode & (1 << imx_spi_selected_channel(s))) ? true : false;
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}
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static bool imx_spi_is_multiple_master_burst(IMXSPIState *s)
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{
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uint8_t wave = EXTRACT(s->regs[ECSPI_CONFIGREG], ECSPI_CONFIGREG_SS_CTL);
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return imx_spi_channel_is_master(s) &&
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!(s->regs[ECSPI_CONREG] & ECSPI_CONREG_SMC) &&
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((wave & (1 << imx_spi_selected_channel(s))) ? true : false);
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}
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static void imx_spi_flush_txfifo(IMXSPIState *s)
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{
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uint32_t tx;
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uint32_t rx;
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DPRINTF("Begin: TX Fifo Size = %d, RX Fifo Size = %d\n",
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fifo32_num_used(&s->tx_fifo), fifo32_num_used(&s->rx_fifo));
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while (!fifo32_is_empty(&s->tx_fifo)) {
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int tx_burst = 0;
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int index = 0;
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if (s->burst_length <= 0) {
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s->burst_length = imx_spi_burst_length(s);
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DPRINTF("Burst length = %d\n", s->burst_length);
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if (imx_spi_is_multiple_master_burst(s)) {
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s->regs[ECSPI_CONREG] |= ECSPI_CONREG_XCH;
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}
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}
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tx = fifo32_pop(&s->tx_fifo);
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DPRINTF("data tx:0x%08x\n", tx);
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tx_burst = MIN(s->burst_length, 32);
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rx = 0;
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while (tx_burst) {
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uint8_t byte = tx & 0xff;
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DPRINTF("writing 0x%02x\n", (uint32_t)byte);
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/* We need to write one byte at a time */
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byte = ssi_transfer(s->bus, byte);
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DPRINTF("0x%02x read\n", (uint32_t)byte);
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tx = tx >> 8;
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rx |= (byte << (index * 8));
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/* Remove 8 bits from the actual burst */
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tx_burst -= 8;
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s->burst_length -= 8;
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index++;
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}
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DPRINTF("data rx:0x%08x\n", rx);
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if (fifo32_is_full(&s->rx_fifo)) {
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s->regs[ECSPI_STATREG] |= ECSPI_STATREG_RO;
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} else {
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fifo32_push(&s->rx_fifo, (uint8_t)rx);
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}
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if (s->burst_length <= 0) {
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s->regs[ECSPI_CONREG] &= ~ECSPI_CONREG_XCH;
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if (!imx_spi_is_multiple_master_burst(s)) {
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s->regs[ECSPI_STATREG] |= ECSPI_STATREG_TC;
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break;
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}
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}
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}
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if (fifo32_is_empty(&s->tx_fifo)) {
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s->regs[ECSPI_STATREG] |= ECSPI_STATREG_TC;
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}
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/* TODO: We should also use TDR and RDR bits */
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DPRINTF("End: TX Fifo Size = %d, RX Fifo Size = %d\n",
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fifo32_num_used(&s->tx_fifo), fifo32_num_used(&s->rx_fifo));
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}
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static void imx_spi_reset(DeviceState *dev)
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{
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IMXSPIState *s = IMX_SPI(dev);
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DPRINTF("\n");
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memset(s->regs, 0, sizeof(s->regs));
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s->regs[ECSPI_STATREG] = 0x00000003;
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imx_spi_rxfifo_reset(s);
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imx_spi_txfifo_reset(s);
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imx_spi_update_irq(s);
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s->burst_length = 0;
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}
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static uint64_t imx_spi_read(void *opaque, hwaddr offset, unsigned size)
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{
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uint32_t value = 0;
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IMXSPIState *s = opaque;
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uint32_t index = offset >> 2;
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if (index >= ECSPI_MAX) {
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qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
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HWADDR_PRIx "\n", TYPE_IMX_SPI, __func__, offset);
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return 0;
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}
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switch (index) {
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case ECSPI_RXDATA:
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if (!imx_spi_is_enabled(s)) {
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value = 0;
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} else if (fifo32_is_empty(&s->rx_fifo)) {
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/* value is undefined */
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value = 0xdeadbeef;
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} else {
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/* read from the RX FIFO */
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value = fifo32_pop(&s->rx_fifo);
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}
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break;
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case ECSPI_TXDATA:
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qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to read from TX FIFO\n",
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TYPE_IMX_SPI, __func__);
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/* Reading from TXDATA gives 0 */
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break;
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case ECSPI_MSGDATA:
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qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to read from MSG FIFO\n",
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TYPE_IMX_SPI, __func__);
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/* Reading from MSGDATA gives 0 */
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break;
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default:
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value = s->regs[index];
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break;
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}
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DPRINTF("reg[%s] => 0x%" PRIx32 "\n", imx_spi_reg_name(index), value);
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imx_spi_update_irq(s);
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return (uint64_t)value;
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}
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static void imx_spi_write(void *opaque, hwaddr offset, uint64_t value,
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unsigned size)
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{
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IMXSPIState *s = opaque;
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uint32_t index = offset >> 2;
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uint32_t change_mask;
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if (index >= ECSPI_MAX) {
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qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
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HWADDR_PRIx "\n", TYPE_IMX_SPI, __func__, offset);
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return;
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}
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DPRINTF("reg[%s] <= 0x%" PRIx32 "\n", imx_spi_reg_name(index),
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(uint32_t)value);
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change_mask = s->regs[index] ^ value;
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switch (index) {
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case ECSPI_RXDATA:
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qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Trying to write to RX FIFO\n",
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TYPE_IMX_SPI, __func__);
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break;
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case ECSPI_TXDATA:
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case ECSPI_MSGDATA:
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/* Is there any difference between TXDATA and MSGDATA ? */
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/* I'll have to look in the linux driver */
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if (!imx_spi_is_enabled(s)) {
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/* Ignore writes if device is disabled */
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break;
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} else if (fifo32_is_full(&s->tx_fifo)) {
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/* Ignore writes if queue is full */
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break;
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}
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fifo32_push(&s->tx_fifo, (uint32_t)value);
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if (imx_spi_channel_is_master(s) &&
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(s->regs[ECSPI_CONREG] & ECSPI_CONREG_SMC)) {
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/*
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* Start emitting if current channel is master and SMC bit is
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* set.
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*/
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imx_spi_flush_txfifo(s);
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}
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break;
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case ECSPI_STATREG:
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/* the RO and TC bits are write-one-to-clear */
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value &= ECSPI_STATREG_RO | ECSPI_STATREG_TC;
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s->regs[ECSPI_STATREG] &= ~value;
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break;
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case ECSPI_CONREG:
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s->regs[ECSPI_CONREG] = value;
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if (!imx_spi_is_enabled(s)) {
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/* device is disabled, so this is a reset */
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imx_spi_reset(DEVICE(s));
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return;
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}
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if (imx_spi_channel_is_master(s)) {
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int i;
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/* We are in master mode */
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for (i = 0; i < 4; i++) {
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qemu_set_irq(s->cs_lines[i],
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i == imx_spi_selected_channel(s) ? 0 : 1);
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}
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if ((value & change_mask & ECSPI_CONREG_SMC) &&
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!fifo32_is_empty(&s->tx_fifo)) {
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/* SMC bit is set and TX FIFO has some slots filled in */
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imx_spi_flush_txfifo(s);
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} else if ((value & change_mask & ECSPI_CONREG_XCH) &&
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!(value & ECSPI_CONREG_SMC)) {
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/* This is a request to start emitting */
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imx_spi_flush_txfifo(s);
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}
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}
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break;
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default:
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s->regs[index] = value;
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break;
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}
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imx_spi_update_irq(s);
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}
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static const struct MemoryRegionOps imx_spi_ops = {
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.read = imx_spi_read,
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.write = imx_spi_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid = {
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/*
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* Our device would not work correctly if the guest was doing
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* unaligned access. This might not be a limitation on the real
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* device but in practice there is no reason for a guest to access
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* this device unaligned.
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*/
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.min_access_size = 4,
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.max_access_size = 4,
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.unaligned = false,
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},
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};
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static void imx_spi_realize(DeviceState *dev, Error **errp)
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{
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IMXSPIState *s = IMX_SPI(dev);
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int i;
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s->bus = ssi_create_bus(dev, "spi");
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memory_region_init_io(&s->iomem, OBJECT(dev), &imx_spi_ops, s,
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TYPE_IMX_SPI, 0x1000);
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sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
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sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
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ssi_auto_connect_slaves(dev, s->cs_lines, s->bus);
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for (i = 0; i < 4; ++i) {
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sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->cs_lines[i]);
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}
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s->burst_length = 0;
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fifo32_create(&s->tx_fifo, ECSPI_FIFO_SIZE);
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fifo32_create(&s->rx_fifo, ECSPI_FIFO_SIZE);
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}
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static void imx_spi_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = imx_spi_realize;
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dc->vmsd = &vmstate_imx_spi;
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dc->reset = imx_spi_reset;
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dc->desc = "i.MX SPI Controller";
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}
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static const TypeInfo imx_spi_info = {
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.name = TYPE_IMX_SPI,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(IMXSPIState),
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.class_init = imx_spi_class_init,
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};
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static void imx_spi_register_types(void)
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{
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type_register_static(&imx_spi_info);
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}
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type_init(imx_spi_register_types)
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103
include/hw/ssi/imx_spi.h
Normal file
103
include/hw/ssi/imx_spi.h
Normal file
@ -0,0 +1,103 @@
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/*
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* IMX SPI Controller
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*
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* Copyright 2016 Jean-Christophe Dubois <jcd@tribudubois.net>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
|
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* See the COPYING file in the top-level directory.
|
||||
*/
|
||||
|
||||
#ifndef IMX_SPI_H
|
||||
#define IMX_SPI_H
|
||||
|
||||
#include "hw/sysbus.h"
|
||||
#include "hw/ssi/ssi.h"
|
||||
#include "qemu/bitops.h"
|
||||
#include "qemu/fifo32.h"
|
||||
|
||||
#define ECSPI_FIFO_SIZE 64
|
||||
|
||||
#define ECSPI_RXDATA 0
|
||||
#define ECSPI_TXDATA 1
|
||||
#define ECSPI_CONREG 2
|
||||
#define ECSPI_CONFIGREG 3
|
||||
#define ECSPI_INTREG 4
|
||||
#define ECSPI_DMAREG 5
|
||||
#define ECSPI_STATREG 6
|
||||
#define ECSPI_PERIODREG 7
|
||||
#define ECSPI_TESTREG 8
|
||||
#define ECSPI_MSGDATA 16
|
||||
#define ECSPI_MAX 17
|
||||
|
||||
/* ECSPI_CONREG */
|
||||
#define ECSPI_CONREG_EN (1 << 0)
|
||||
#define ECSPI_CONREG_HT (1 << 1)
|
||||
#define ECSPI_CONREG_XCH (1 << 2)
|
||||
#define ECSPI_CONREG_SMC (1 << 3)
|
||||
#define ECSPI_CONREG_CHANNEL_MODE_SHIFT 4
|
||||
#define ECSPI_CONREG_CHANNEL_MODE_LENGTH 4
|
||||
#define ECSPI_CONREG_DRCTL_SHIFT 16
|
||||
#define ECSPI_CONREG_DRCTL_LENGTH 2
|
||||
#define ECSPI_CONREG_CHANNEL_SELECT_SHIFT 18
|
||||
#define ECSPI_CONREG_CHANNEL_SELECT_LENGTH 2
|
||||
#define ECSPI_CONREG_BURST_LENGTH_SHIFT 20
|
||||
#define ECSPI_CONREG_BURST_LENGTH_LENGTH 12
|
||||
|
||||
/* ECSPI_CONFIGREG */
|
||||
#define ECSPI_CONFIGREG_SS_CTL_SHIFT 8
|
||||
#define ECSPI_CONFIGREG_SS_CTL_LENGTH 4
|
||||
|
||||
/* ECSPI_INTREG */
|
||||
#define ECSPI_INTREG_TEEN (1 << 0)
|
||||
#define ECSPI_INTREG_TDREN (1 << 1)
|
||||
#define ECSPI_INTREG_TFEN (1 << 2)
|
||||
#define ECSPI_INTREG_RREN (1 << 3)
|
||||
#define ECSPI_INTREG_RDREN (1 << 4)
|
||||
#define ECSPI_INTREG_RFEN (1 << 5)
|
||||
#define ECSPI_INTREG_ROEN (1 << 6)
|
||||
#define ECSPI_INTREG_TCEN (1 << 7)
|
||||
|
||||
/* ECSPI_DMAREG */
|
||||
#define ECSPI_DMAREG_RXTDEN (1 << 31)
|
||||
#define ECSPI_DMAREG_RXDEN (1 << 23)
|
||||
#define ECSPI_DMAREG_TEDEN (1 << 7)
|
||||
#define ECSPI_DMAREG_RX_THRESHOLD_SHIFT 16
|
||||
#define ECSPI_DMAREG_RX_THRESHOLD_LENGTH 6
|
||||
|
||||
/* ECSPI_STATREG */
|
||||
#define ECSPI_STATREG_TE (1 << 0)
|
||||
#define ECSPI_STATREG_TDR (1 << 1)
|
||||
#define ECSPI_STATREG_TF (1 << 2)
|
||||
#define ECSPI_STATREG_RR (1 << 3)
|
||||
#define ECSPI_STATREG_RDR (1 << 4)
|
||||
#define ECSPI_STATREG_RF (1 << 5)
|
||||
#define ECSPI_STATREG_RO (1 << 6)
|
||||
#define ECSPI_STATREG_TC (1 << 7)
|
||||
|
||||
#define EXTRACT(value, name) extract32(value, name##_SHIFT, name##_LENGTH)
|
||||
|
||||
#define TYPE_IMX_SPI "imx.spi"
|
||||
#define IMX_SPI(obj) OBJECT_CHECK(IMXSPIState, (obj), TYPE_IMX_SPI)
|
||||
|
||||
typedef struct IMXSPIState {
|
||||
/* <private> */
|
||||
SysBusDevice parent_obj;
|
||||
|
||||
/* <public> */
|
||||
MemoryRegion iomem;
|
||||
|
||||
qemu_irq irq;
|
||||
|
||||
qemu_irq cs_lines[4];
|
||||
|
||||
SSIBus *bus;
|
||||
|
||||
uint32_t regs[ECSPI_MAX];
|
||||
|
||||
Fifo32 rx_fifo;
|
||||
Fifo32 tx_fifo;
|
||||
|
||||
int16_t burst_length;
|
||||
} IMXSPIState;
|
||||
|
||||
#endif /* IMX_SPI_H */
|
||||
Loading…
Reference in New Issue
Block a user