Malta flash support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3887 c046a42c-6fe2-441c-8c8c-71466251a162
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@ -470,6 +470,7 @@ VL_OBJS+= jazz_led.o
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VL_OBJS+= ide.o gt64xxx.o pckbd.o ps2.o fdc.o mc146818rtc.o usb-uhci.o acpi.o ds1225y.o
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VL_OBJS+= piix_pci.o parallel.o cirrus_vga.o $(SOUND_HW)
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VL_OBJS+= mipsnet.o
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VL_OBJS+= pflash_cfi01.o
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CPPFLAGS += -DHAS_AUDIO
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endif
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ifeq ($(TARGET_BASE_ARCH), cris)
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@ -28,6 +28,8 @@
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#include "net.h"
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#include "boards.h"
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#include "smbus.h"
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#include "block.h"
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#include "flash.h"
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#include "mips.h"
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#include "pci.h"
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#include "qemu-char.h"
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@ -35,6 +37,8 @@
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#include "audio/audio.h"
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#include "boards.h"
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//#define DEBUG_BOARD_INIT
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#ifdef TARGET_WORDS_BIGENDIAN
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#define BIOS_FILENAME "mips_bios.bin"
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#else
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@ -766,13 +770,13 @@ void mips_malta_init (int ram_size, int vga_ram_size,
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{
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char buf[1024];
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unsigned long bios_offset;
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target_long bios_size;
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int64_t kernel_entry;
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PCIBus *pci_bus;
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CPUState *env;
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RTCState *rtc_state;
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fdctrl_t *floppy_controller;
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MaltaFPGAState *malta_fpga;
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int ret;
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qemu_irq *i8259;
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int piix4_devfn;
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uint8_t *eeprom_buf;
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@ -781,6 +785,8 @@ void mips_malta_init (int ram_size, int vga_ram_size,
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int index;
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BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
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BlockDriverState *fd[MAX_FD];
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int fl_idx = 0;
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int fl_sectors = 0;
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/* init CPUs */
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if (cpu_model == NULL) {
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@ -801,7 +807,7 @@ void mips_malta_init (int ram_size, int vga_ram_size,
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/* allocate RAM */
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cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
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/* Map the bios at two physical locations, as on the real board */
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/* Map the bios at two physical locations, as on the real board. */
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bios_offset = ram_size + vga_ram_size;
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cpu_register_physical_memory(0x1e000000LL,
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BIOS_SIZE, bios_offset | IO_MEM_ROM);
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@ -811,35 +817,9 @@ void mips_malta_init (int ram_size, int vga_ram_size,
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/* FPGA */
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malta_fpga = malta_fpga_init(0x1f000000LL, env);
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/* Load a BIOS image unless a kernel image has been specified. */
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if (!kernel_filename) {
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if (bios_name == NULL)
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bios_name = BIOS_FILENAME;
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snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
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ret = load_image(buf, phys_ram_base + bios_offset);
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if (ret < 0 || ret > BIOS_SIZE) {
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fprintf(stderr,
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"qemu: Could not load MIPS bios '%s', and no -kernel argument was specified\n",
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buf);
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exit(1);
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}
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/* In little endian mode the 32bit words in the bios are swapped,
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a neat trick which allows bi-endian firmware. */
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#ifndef TARGET_WORDS_BIGENDIAN
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{
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uint32_t *addr;
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for (addr = (uint32_t *)(phys_ram_base + bios_offset);
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addr < (uint32_t *)(phys_ram_base + bios_offset + ret);
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addr++) {
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*addr = bswap32(*addr);
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}
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}
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#endif
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}
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/* If a kernel image has been specified, write a small bootloader
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to the flash location. */
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/* Load firmware in flash / BIOS unless we boot directly into a kernel. */
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if (kernel_filename) {
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/* Write a small bootloader to the flash location. */
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loaderparams.ram_size = ram_size;
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loaderparams.kernel_filename = kernel_filename;
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loaderparams.kernel_cmdline = kernel_cmdline;
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@ -847,6 +827,47 @@ void mips_malta_init (int ram_size, int vga_ram_size,
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kernel_entry = load_kernel(env);
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env->CP0_Status &= ~((1 << CP0St_BEV) | (1 << CP0St_ERL));
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write_bootloader(env, bios_offset, kernel_entry);
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} else {
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index = drive_get_index(IF_PFLASH, 0, fl_idx);
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if (index != -1) {
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/* Load firmware from flash. */
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bios_size = 0x400000;
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fl_sectors = bios_size >> 16;
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#ifdef DEBUG_BOARD_INIT
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printf("Register parallel flash %d size " TARGET_FMT_lx " at "
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"offset %08lx addr %08llx '%s' %x\n",
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fl_idx, bios_size, bios_offset, 0x1e000000LL,
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bdrv_get_device_name(drives_table[index].bdrv), fl_sectors);
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#endif
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pflash_cfi01_register(0x1e000000LL, bios_offset,
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drives_table[index].bdrv, 65536, fl_sectors,
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4, 0x0000, 0x0000, 0x0000, 0x0000);
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fl_idx++;
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} else {
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/* Load a BIOS image. */
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if (bios_name == NULL)
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bios_name = BIOS_FILENAME;
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snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
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bios_size = load_image(buf, phys_ram_base + bios_offset);
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if ((bios_size < 0 || bios_size > BIOS_SIZE) && !kernel_filename) {
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fprintf(stderr,
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"qemu: Could not load MIPS bios '%s', and no -kernel argument was specified\n",
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buf);
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exit(1);
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}
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}
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/* In little endian mode the 32bit words in the bios are swapped,
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a neat trick which allows bi-endian firmware. */
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#ifndef TARGET_WORDS_BIGENDIAN
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{
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uint32_t *addr;
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for (addr = (uint32_t *)(phys_ram_base + bios_offset);
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addr < (uint32_t *)(phys_ram_base + bios_offset + bios_size);
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addr++) {
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*addr = bswap32(*addr);
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}
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}
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#endif
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}
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/* Board ID = 0x420 (Malta Board with CoreLV)
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@ -111,7 +111,7 @@ static uint32_t pflash_read (pflash_t *pfl, target_ulong offset, int width)
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else if (pfl->width == 4)
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boff = boff >> 2;
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DPRINTF("%s: reading offset %08x under cmd %02x\n",
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DPRINTF("%s: reading offset " TARGET_FMT_lx " under cmd %02x\n",
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__func__, boff, pfl->cmd);
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switch (pfl->cmd) {
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@ -121,7 +121,8 @@ static uint32_t pflash_read (pflash_t *pfl, target_ulong offset, int width)
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switch (width) {
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case 1:
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ret = p[offset];
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DPRINTF("%s: data offset %08x %02x\n", __func__, offset, ret);
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DPRINTF("%s: data offset " TARGET_FMT_lx " %02x\n",
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__func__, offset, ret);
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break;
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case 2:
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#if defined(TARGET_WORDS_BIGENDIAN)
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@ -131,7 +132,8 @@ static uint32_t pflash_read (pflash_t *pfl, target_ulong offset, int width)
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ret = p[offset];
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ret |= p[offset + 1] << 8;
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#endif
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DPRINTF("%s: data offset %08x %04x\n", __func__, offset, ret);
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DPRINTF("%s: data offset " TARGET_FMT_lx " %04x\n",
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__func__, offset, ret);
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break;
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case 4:
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#if defined(TARGET_WORDS_BIGENDIAN)
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@ -146,7 +148,8 @@ static uint32_t pflash_read (pflash_t *pfl, target_ulong offset, int width)
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ret |= p[offset + 2] << 16;
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ret |= p[offset + 3] << 24;
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#endif
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DPRINTF("%s: data offset %08x %08x\n", __func__, offset, ret);
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DPRINTF("%s: data offset " TARGET_FMT_lx " %08x\n",
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__func__, offset, ret);
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break;
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default:
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DPRINTF("BUG in %s\n", __func__);
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@ -208,7 +211,7 @@ static void pflash_write (pflash_t *pfl, target_ulong offset, uint32_t value,
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else
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offset -= pfl->base;
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DPRINTF("%s: offset %08x %08x %d wcycle 0x%x\n",
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DPRINTF("%s: offset " TARGET_FMT_lx " %08x %d wcycle 0x%x\n",
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__func__, offset, value, width, pfl->wcycle);
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/* Set the device in I/O access mode */
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@ -230,8 +233,9 @@ static void pflash_write (pflash_t *pfl, target_ulong offset, uint32_t value,
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p = pfl->storage;
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offset &= ~(pfl->sector_len - 1);
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DPRINTF("%s: block erase at 0x%x bytes 0x%x\n", __func__,
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offset, pfl->sector_len);
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DPRINTF("%s: block erase at " TARGET_FMT_lx " bytes "
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TARGET_FMT_lx "\n",
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__func__, offset, pfl->sector_len);
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memset(p + offset, 0xff, pfl->sector_len);
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pflash_update(pfl, offset, pfl->sector_len);
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@ -278,7 +282,7 @@ static void pflash_write (pflash_t *pfl, target_ulong offset, uint32_t value,
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break;
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case 0xe8:
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DPRINTF("%s: block write of 0x%x bytes\n", __func__, cmd);
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DPRINTF("%s: block write of %x bytes\n", __func__, cmd);
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pfl->counter = cmd;
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pfl->wcycle++;
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break;
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@ -311,7 +315,8 @@ static void pflash_write (pflash_t *pfl, target_ulong offset, uint32_t value,
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switch (pfl->cmd) {
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case 0xe8: /* Block write */
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p = pfl->storage;
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DPRINTF("%s: block write offset 0x%x value 0x%x counter 0x%x\n",
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DPRINTF("%s: block write offset " TARGET_FMT_lx
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" value %x counter " TARGET_FMT_lx "\n",
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__func__, offset, value, pfl->counter);
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switch (width) {
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case 1:
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@ -382,7 +387,7 @@ static void pflash_write (pflash_t *pfl, target_ulong offset, uint32_t value,
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error_flash:
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printf("%s: Unimplemented flash cmd sequence "
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"(offset 0x%x, wcycle 0x%x cmd 0x%x value 0x%x\n",
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"(offset " TARGET_FMT_lx ", wcycle 0x%x cmd 0x%x value 0x%x\n",
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__func__, offset, pfl->wcycle, pfl->cmd, value);
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reset_flash:
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@ -484,7 +489,7 @@ static int ctz32 (uint32_t n)
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}
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pflash_t *pflash_cfi01_register(target_phys_addr_t base, ram_addr_t off,
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BlockDriverState *bs, target_ulong sector_len,
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BlockDriverState *bs, uint32_t sector_len,
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int nb_blocs, int width,
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uint16_t id0, uint16_t id1,
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uint16_t id2, uint16_t id3)
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@ -495,9 +500,11 @@ pflash_t *pflash_cfi01_register(target_phys_addr_t base, ram_addr_t off,
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total_len = sector_len * nb_blocs;
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/* XXX: to be fixed */
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#if 0
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if (total_len != (8 * 1024 * 1024) && total_len != (16 * 1024 * 1024) &&
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total_len != (32 * 1024 * 1024) && total_len != (64 * 1024 * 1024))
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return NULL;
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#endif
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pfl = qemu_mallocz(sizeof(pflash_t));
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