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pflash_cfi01/pflash_cfi02: convert to memory API

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cfi02 is annoying in that is ignores some address bits; we probably
want explicit support in the memory API for that.

Reviewed-by: Richard Henderson  <rth@twiddle.net>
Signed-off-by: Avi Kivity <avi@redhat.com>
This commit is contained in:
Avi Kivity 2011-08-04 15:55:30 +03:00
parent a1807ef295
commit c8a50e596c
18 changed files with 246 additions and 223 deletions
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16
hw/collie.c
View File

@ -26,7 +26,7 @@ static void collie_init(ram_addr_t ram_size,
{ {
StrongARMState *s; StrongARMState *s;
DriveInfo *dinfo; DriveInfo *dinfo;
ram_addr_t phys_flash; MemoryRegion *phys_flash = g_new(MemoryRegion, 2);
if (!cpu_model) { if (!cpu_model) {
cpu_model = "sa1110"; cpu_model = "sa1110";
@ -34,17 +34,19 @@ static void collie_init(ram_addr_t ram_size,
s = sa1110_init(collie_binfo.ram_size, cpu_model); s = sa1110_init(collie_binfo.ram_size, cpu_model);
phys_flash = qemu_ram_alloc(NULL, "collie.fl1", 0x02000000); memory_region_init_rom_device(&phys_flash[0], &pflash_cfi01_ops_le,
NULL, "collie.fl1", 0x02000000);
dinfo = drive_get(IF_PFLASH, 0, 0); dinfo = drive_get(IF_PFLASH, 0, 0);
pflash_cfi01_register(SA_CS0, phys_flash, pflash_cfi01_register(SA_CS0, &phys_flash[0],
dinfo ? dinfo->bdrv : NULL, (64 * 1024), dinfo ? dinfo->bdrv : NULL, (64 * 1024),
512, 4, 0x00, 0x00, 0x00, 0x00, 0); 512, 4, 0x00, 0x00, 0x00, 0x00);
phys_flash = qemu_ram_alloc(NULL, "collie.fl2", 0x02000000); memory_region_init_rom_device(&phys_flash[1], &pflash_cfi01_ops_le,
NULL, "collie.fl2", 0x02000000);
dinfo = drive_get(IF_PFLASH, 0, 1); dinfo = drive_get(IF_PFLASH, 0, 1);
pflash_cfi01_register(SA_CS1, phys_flash, pflash_cfi01_register(SA_CS1, &phys_flash[1],
dinfo ? dinfo->bdrv : NULL, (64 * 1024), dinfo ? dinfo->bdrv : NULL, (64 * 1024),
512, 4, 0x00, 0x00, 0x00, 0x00, 0); 512, 4, 0x00, 0x00, 0x00, 0x00);
sysbus_create_simple("scoop", 0x40800000, NULL); sysbus_create_simple("scoop", 0x40800000, NULL);

16
hw/flash.h
View File

@ -1,21 +1,27 @@
#include "memory.h"
/* NOR flash devices */ /* NOR flash devices */
typedef struct pflash_t pflash_t; typedef struct pflash_t pflash_t;
/* pflash_cfi01.c */ /* pflash_cfi01.c */
pflash_t *pflash_cfi01_register(target_phys_addr_t base, ram_addr_t off, extern const MemoryRegionOps pflash_cfi01_ops_be;
extern const MemoryRegionOps pflash_cfi01_ops_le;
extern const MemoryRegionOps pflash_cfi02_ops_be;
extern const MemoryRegionOps pflash_cfi02_ops_le;
pflash_t *pflash_cfi01_register(target_phys_addr_t base, MemoryRegion *mem,
BlockDriverState *bs, BlockDriverState *bs,
uint32_t sector_len, int nb_blocs, int width, uint32_t sector_len, int nb_blocs, int width,
uint16_t id0, uint16_t id1, uint16_t id0, uint16_t id1,
uint16_t id2, uint16_t id3, int be); uint16_t id2, uint16_t id3);
/* pflash_cfi02.c */ /* pflash_cfi02.c */
pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off, pflash_t *pflash_cfi02_register(target_phys_addr_t base, MemoryRegion *mem,
BlockDriverState *bs, uint32_t sector_len, BlockDriverState *bs, uint32_t sector_len,
int nb_blocs, int nb_mappings, int width, int nb_blocs, int nb_mappings, int width,
uint16_t id0, uint16_t id1, uint16_t id0, uint16_t id1,
uint16_t id2, uint16_t id3, uint16_t id2, uint16_t id3,
uint16_t unlock_addr0, uint16_t unlock_addr1, uint16_t unlock_addr0, uint16_t unlock_addr1);
int be);
/* nand.c */ /* nand.c */
DeviceState *nand_init(BlockDriverState *bdrv, int manf_id, int chip_id); DeviceState *nand_init(BlockDriverState *bdrv, int manf_id, int chip_id);

28
hw/gumstix.c
View File

@ -48,7 +48,8 @@ static void connex_init(ram_addr_t ram_size,
{ {
PXA2xxState *cpu; PXA2xxState *cpu;
DriveInfo *dinfo; DriveInfo *dinfo;
int be; const MemoryRegionOps *flash_ops;
MemoryRegion *flash = g_new(MemoryRegion, 1);
uint32_t connex_rom = 0x01000000; uint32_t connex_rom = 0x01000000;
uint32_t connex_ram = 0x04000000; uint32_t connex_ram = 0x04000000;
@ -63,14 +64,15 @@ static void connex_init(ram_addr_t ram_size,
} }
#ifdef TARGET_WORDS_BIGENDIAN #ifdef TARGET_WORDS_BIGENDIAN
be = 1; flash_ops = &pflash_cfi01_ops_be;
#else #else
be = 0; flash_ops = &pflash_cfi01_ops_le;
#endif #endif
if (!pflash_cfi01_register(0x00000000, qemu_ram_alloc(NULL, "connext.rom", memory_region_init_rom_device(flash, flash_ops,
connex_rom), NULL, "connext.rom", connex_rom);
if (!pflash_cfi01_register(0x00000000, flash,
dinfo->bdrv, sector_len, connex_rom / sector_len, dinfo->bdrv, sector_len, connex_rom / sector_len,
2, 0, 0, 0, 0, be)) { 2, 0, 0, 0, 0)) {
fprintf(stderr, "qemu: Error registering flash memory.\n"); fprintf(stderr, "qemu: Error registering flash memory.\n");
exit(1); exit(1);
} }
@ -87,7 +89,8 @@ static void verdex_init(ram_addr_t ram_size,
{ {
PXA2xxState *cpu; PXA2xxState *cpu;
DriveInfo *dinfo; DriveInfo *dinfo;
int be; MemoryRegion *flash = g_new(MemoryRegion, 1);
const MemoryRegionOps *flash_ops;
uint32_t verdex_rom = 0x02000000; uint32_t verdex_rom = 0x02000000;
uint32_t verdex_ram = 0x10000000; uint32_t verdex_ram = 0x10000000;
@ -102,14 +105,15 @@ static void verdex_init(ram_addr_t ram_size,
} }
#ifdef TARGET_WORDS_BIGENDIAN #ifdef TARGET_WORDS_BIGENDIAN
be = 1; flash_ops = &pflash_cfi01_ops_be;
#else #else
be = 0; flash_ops = &pflash_cfi01_ops_le;
#endif #endif
if (!pflash_cfi01_register(0x00000000, qemu_ram_alloc(NULL, "verdex.rom", memory_region_init_rom_device(flash, flash_ops,
verdex_rom), NULL, "verdex.rom", verdex_rom);
if (!pflash_cfi01_register(0x00000000, flash,
dinfo->bdrv, sector_len, verdex_rom / sector_len, dinfo->bdrv, sector_len, verdex_rom / sector_len,
2, 0, 0, 0, 0, be)) { 2, 0, 0, 0, 0)) {
fprintf(stderr, "qemu: Error registering flash memory.\n"); fprintf(stderr, "qemu: Error registering flash memory.\n");
exit(1); exit(1);
} }

14
hw/lm32_boards.c
View File

@ -77,7 +77,7 @@ static void lm32_evr_init(ram_addr_t ram_size_not_used,
CPUState *env; CPUState *env;
DriveInfo *dinfo; DriveInfo *dinfo;
ram_addr_t phys_ram; ram_addr_t phys_ram;
ram_addr_t phys_flash; MemoryRegion *phys_flash = g_new(MemoryRegion, 1);
qemu_irq *cpu_irq, irq[32]; qemu_irq *cpu_irq, irq[32];
ResetInfo *reset_info; ResetInfo *reset_info;
int i; int i;
@ -108,13 +108,14 @@ static void lm32_evr_init(ram_addr_t ram_size_not_used,
phys_ram = qemu_ram_alloc(NULL, "lm32_evr.sdram", ram_size); phys_ram = qemu_ram_alloc(NULL, "lm32_evr.sdram", ram_size);
cpu_register_physical_memory(ram_base, ram_size, phys_ram | IO_MEM_RAM); cpu_register_physical_memory(ram_base, ram_size, phys_ram | IO_MEM_RAM);
phys_flash = qemu_ram_alloc(NULL, "lm32_evr.flash", flash_size); memory_region_init_rom_device(phys_flash, &pflash_cfi02_ops_be,
NULL, "lm32_evr.flash", flash_size);
dinfo = drive_get(IF_PFLASH, 0, 0); dinfo = drive_get(IF_PFLASH, 0, 0);
/* Spansion S29NS128P */ /* Spansion S29NS128P */
pflash_cfi02_register(flash_base, phys_flash, pflash_cfi02_register(flash_base, phys_flash,
dinfo ? dinfo->bdrv : NULL, flash_sector_size, dinfo ? dinfo->bdrv : NULL, flash_sector_size,
flash_size / flash_sector_size, 1, 2, flash_size / flash_sector_size, 1, 2,
0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1); 0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa);
/* create irq lines */ /* create irq lines */
cpu_irq = qemu_allocate_irqs(cpu_irq_handler, env, 1); cpu_irq = qemu_allocate_irqs(cpu_irq_handler, env, 1);
@ -165,7 +166,7 @@ static void lm32_uclinux_init(ram_addr_t ram_size_not_used,
CPUState *env; CPUState *env;
DriveInfo *dinfo; DriveInfo *dinfo;
ram_addr_t phys_ram; ram_addr_t phys_ram;
ram_addr_t phys_flash; MemoryRegion *phys_flash = g_new(MemoryRegion, 1);
qemu_irq *cpu_irq, irq[32]; qemu_irq *cpu_irq, irq[32];
HWSetup *hw; HWSetup *hw;
ResetInfo *reset_info; ResetInfo *reset_info;
@ -203,13 +204,14 @@ static void lm32_uclinux_init(ram_addr_t ram_size_not_used,
phys_ram = qemu_ram_alloc(NULL, "lm32_uclinux.sdram", ram_size); phys_ram = qemu_ram_alloc(NULL, "lm32_uclinux.sdram", ram_size);
cpu_register_physical_memory(ram_base, ram_size, phys_ram | IO_MEM_RAM); cpu_register_physical_memory(ram_base, ram_size, phys_ram | IO_MEM_RAM);
phys_flash = qemu_ram_alloc(NULL, "lm32_uclinux.flash", flash_size); memory_region_init_rom_device(phys_flash, &pflash_cfi01_ops_be,
NULL, "lm32_uclinux.flash", flash_size);
dinfo = drive_get(IF_PFLASH, 0, 0); dinfo = drive_get(IF_PFLASH, 0, 0);
/* Spansion S29NS128P */ /* Spansion S29NS128P */
pflash_cfi02_register(flash_base, phys_flash, pflash_cfi02_register(flash_base, phys_flash,
dinfo ? dinfo->bdrv : NULL, flash_sector_size, dinfo ? dinfo->bdrv : NULL, flash_sector_size,
flash_size / flash_sector_size, 1, 2, flash_size / flash_sector_size, 1, 2,
0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1); 0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa);
/* create irq lines */ /* create irq lines */
cpu_irq = qemu_allocate_irqs(cpu_irq_handler, env, 1); cpu_irq = qemu_allocate_irqs(cpu_irq_handler, env, 1);

20
hw/mainstone.c
View File

@ -101,7 +101,8 @@ static void mainstone_common_init(ram_addr_t ram_size,
DeviceState *mst_irq; DeviceState *mst_irq;
DriveInfo *dinfo; DriveInfo *dinfo;
int i; int i;
int be; MemoryRegion *flashes = g_new(MemoryRegion, 2);
const MemoryRegionOps *flash_ops;
if (!cpu_model) if (!cpu_model)
cpu_model = "pxa270-c5"; cpu_model = "pxa270-c5";
@ -113,9 +114,9 @@ static void mainstone_common_init(ram_addr_t ram_size,
MAINSTONE_ROM) | IO_MEM_ROM); MAINSTONE_ROM) | IO_MEM_ROM);
#ifdef TARGET_WORDS_BIGENDIAN #ifdef TARGET_WORDS_BIGENDIAN
be = 1; flash_ops = &pflash_cfi01_ops_be;
#else #else
be = 0; flash_ops = &pflash_cfi01_ops_le;
#endif #endif
/* There are two 32MiB flash devices on the board */ /* There are two 32MiB flash devices on the board */
for (i = 0; i < 2; i ++) { for (i = 0; i < 2; i ++) {
@ -126,13 +127,14 @@ static void mainstone_common_init(ram_addr_t ram_size,
exit(1); exit(1);
} }
memory_region_init_rom_device(&flashes[i], flash_ops,
NULL, (i ? "mainstone.flash1"
: "mainstone.flash0"),
MAINSTONE_FLASH);
if (!pflash_cfi01_register(mainstone_flash_base[i], if (!pflash_cfi01_register(mainstone_flash_base[i],
qemu_ram_alloc(NULL, i ? "mainstone.flash1" : &flashes[i], dinfo->bdrv, sector_len,
"mainstone.flash0", MAINSTONE_FLASH / sector_len, 4, 0, 0, 0,
MAINSTONE_FLASH), 0)) {
dinfo->bdrv, sector_len,
MAINSTONE_FLASH / sector_len, 4, 0, 0, 0, 0,
be)) {
fprintf(stderr, "qemu: Error registering flash memory.\n"); fprintf(stderr, "qemu: Error registering flash memory.\n");
exit(1); exit(1);
} }

7
hw/milkymist.c
View File

@ -82,7 +82,7 @@ milkymist_init(ram_addr_t ram_size_not_used,
int kernel_size; int kernel_size;
DriveInfo *dinfo; DriveInfo *dinfo;
ram_addr_t phys_sdram; ram_addr_t phys_sdram;
ram_addr_t phys_flash; MemoryRegion *phys_flash = g_new(MemoryRegion, 1);
qemu_irq irq[32], *cpu_irq; qemu_irq irq[32], *cpu_irq;
int i; int i;
char *bios_filename; char *bios_filename;
@ -113,13 +113,14 @@ milkymist_init(ram_addr_t ram_size_not_used,
cpu_register_physical_memory(sdram_base, sdram_size, cpu_register_physical_memory(sdram_base, sdram_size,
phys_sdram | IO_MEM_RAM); phys_sdram | IO_MEM_RAM);
phys_flash = qemu_ram_alloc(NULL, "milkymist.flash", flash_size); memory_region_init_rom_device(phys_flash, &pflash_cfi01_ops_be,
NULL, "milkymist.flash", flash_size);
dinfo = drive_get(IF_PFLASH, 0, 0); dinfo = drive_get(IF_PFLASH, 0, 0);
/* Numonyx JS28F256J3F105 */ /* Numonyx JS28F256J3F105 */
pflash_cfi01_register(flash_base, phys_flash, pflash_cfi01_register(flash_base, phys_flash,
dinfo ? dinfo->bdrv : NULL, flash_sector_size, dinfo ? dinfo->bdrv : NULL, flash_sector_size,
flash_size / flash_sector_size, 2, flash_size / flash_sector_size, 2,
0x00, 0x89, 0x00, 0x1d, 1); 0x00, 0x89, 0x00, 0x1d);
/* create irq lines */ /* create irq lines */
cpu_irq = qemu_allocate_irqs(cpu_irq_handler, env, 1); cpu_irq = qemu_allocate_irqs(cpu_irq_handler, env, 1);

45
hw/mips_malta.c
View File

@ -46,6 +46,7 @@
#include "elf.h" #include "elf.h"
#include "mc146818rtc.h" #include "mc146818rtc.h"
#include "blockdev.h" #include "blockdev.h"
#include "exec-memory.h"
//#define DEBUG_BOARD_INIT //#define DEBUG_BOARD_INIT
@ -762,7 +763,10 @@ void mips_malta_init (ram_addr_t ram_size,
{ {
char *filename; char *filename;
ram_addr_t ram_offset; ram_addr_t ram_offset;
ram_addr_t bios_offset; MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *bios = g_new(MemoryRegion, 1);
MemoryRegion *bios_1e0 = g_new(MemoryRegion, 1);
MemoryRegion *bios_1fc = g_new(MemoryRegion, 1);
target_long bios_size; target_long bios_size;
int64_t kernel_entry; int64_t kernel_entry;
PCIBus *pci_bus; PCIBus *pci_bus;
@ -777,7 +781,7 @@ void mips_malta_init (ram_addr_t ram_size,
DriveInfo *fd[MAX_FD]; DriveInfo *fd[MAX_FD];
int fl_idx = 0; int fl_idx = 0;
int fl_sectors = 0; int fl_sectors = 0;
int be; const MemoryRegionOps *bios_ops;
/* Make sure the first 3 serial ports are associated with a device. */ /* Make sure the first 3 serial ports are associated with a device. */
for(i = 0; i < 3; i++) { for(i = 0; i < 3; i++) {
@ -810,23 +814,24 @@ void mips_malta_init (ram_addr_t ram_size,
((unsigned int)ram_size / (1 << 20))); ((unsigned int)ram_size / (1 << 20)));
exit(1); exit(1);
} }
ram_offset = qemu_ram_alloc(NULL, "mips_malta.ram", ram_size); #ifdef TARGET_WORDS_BIGENDIAN
bios_offset = qemu_ram_alloc(NULL, "mips_malta.bios", BIOS_SIZE); bios_ops = &pflash_cfi01_ops_be;
#else
bios_ops = &pflash_cfi01_ops_le;
#endif
ram_offset = qemu_ram_alloc(NULL, "mips_malta.ram", ram_size);
memory_region_init_rom_device(bios, bios_ops, NULL,
"mips_malta.bios", BIOS_SIZE);
cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM); cpu_register_physical_memory(0, ram_size, ram_offset | IO_MEM_RAM);
/* Map the bios at two physical locations, as on the real board. */ /* Map the bios at two physical locations, as on the real board. */
cpu_register_physical_memory(0x1e000000LL, memory_region_init_alias(bios_1e0, "bios-1e0", bios, 0, BIOS_SIZE);
BIOS_SIZE, bios_offset | IO_MEM_ROM); memory_region_add_subregion(address_space_mem, 0x1e000000LL, bios_1e0);
cpu_register_physical_memory(0x1fc00000LL, memory_region_init_alias(bios_1fc, "bios-1fc", bios, 0, BIOS_SIZE);
BIOS_SIZE, bios_offset | IO_MEM_ROM); memory_region_add_subregion(address_space_mem, 0x1fc00000LL, bios_1fc);
#ifdef TARGET_WORDS_BIGENDIAN
be = 1;
#else
be = 0;
#endif
/* FPGA */ /* FPGA */
malta_fpga_init(0x1f000000LL, env->irq[2], serial_hds[2]); malta_fpga_init(0x1f000000LL, env->irq[2], serial_hds[2]);
@ -838,7 +843,7 @@ void mips_malta_init (ram_addr_t ram_size,
loaderparams.kernel_cmdline = kernel_cmdline; loaderparams.kernel_cmdline = kernel_cmdline;
loaderparams.initrd_filename = initrd_filename; loaderparams.initrd_filename = initrd_filename;
kernel_entry = load_kernel(); kernel_entry = load_kernel();
write_bootloader(env, qemu_get_ram_ptr(bios_offset), kernel_entry); write_bootloader(env, memory_region_get_ram_ptr(bios), kernel_entry);
} else { } else {
dinfo = drive_get(IF_PFLASH, 0, fl_idx); dinfo = drive_get(IF_PFLASH, 0, fl_idx);
if (dinfo) { if (dinfo) {
@ -847,13 +852,13 @@ void mips_malta_init (ram_addr_t ram_size,
fl_sectors = bios_size >> 16; fl_sectors = bios_size >> 16;
#ifdef DEBUG_BOARD_INIT #ifdef DEBUG_BOARD_INIT
printf("Register parallel flash %d size " TARGET_FMT_lx " at " printf("Register parallel flash %d size " TARGET_FMT_lx " at "
"offset %08lx addr %08llx '%s' %x\n", "addr %08llx '%s' %x\n",
fl_idx, bios_size, bios_offset, 0x1e000000LL, fl_idx, bios_size, 0x1e000000LL,
bdrv_get_device_name(dinfo->bdrv), fl_sectors); bdrv_get_device_name(dinfo->bdrv), fl_sectors);
#endif #endif
pflash_cfi01_register(0x1e000000LL, bios_offset, pflash_cfi01_register(0x1e000000LL, bios,
dinfo->bdrv, 65536, fl_sectors, dinfo->bdrv, 65536, fl_sectors,
4, 0x0000, 0x0000, 0x0000, 0x0000, be); 4, 0x0000, 0x0000, 0x0000, 0x0000);
fl_idx++; fl_idx++;
} else { } else {
/* Load a BIOS image. */ /* Load a BIOS image. */
@ -878,7 +883,7 @@ void mips_malta_init (ram_addr_t ram_size,
a neat trick which allows bi-endian firmware. */ a neat trick which allows bi-endian firmware. */
#ifndef TARGET_WORDS_BIGENDIAN #ifndef TARGET_WORDS_BIGENDIAN
{ {
uint32_t *addr = qemu_get_ram_ptr(bios_offset);; uint32_t *addr = memory_region_get_ram_ptr(bios);
uint32_t *end = addr + bios_size; uint32_t *end = addr + bios_size;
while (addr < end) { while (addr < end) {
bswap32s(addr); bswap32s(addr);
@ -890,7 +895,7 @@ void mips_malta_init (ram_addr_t ram_size,
/* Board ID = 0x420 (Malta Board with CoreLV) /* Board ID = 0x420 (Malta Board with CoreLV)
XXX: theoretically 0x1e000010 should map to flash and 0x1fc00010 should XXX: theoretically 0x1e000010 should map to flash and 0x1fc00010 should
map to the board ID. */ map to the board ID. */
stl_p(qemu_get_ram_ptr(bios_offset) + 0x10, 0x00000420); stl_p(memory_region_get_ram_ptr(bios) + 0x10, 0x00000420);
/* Init internal devices */ /* Init internal devices */
cpu_mips_irq_init_cpu(env); cpu_mips_irq_init_cpu(env);

20
hw/mips_r4k.c
View File

@ -23,6 +23,7 @@
#include "elf.h" #include "elf.h"
#include "mc146818rtc.h" #include "mc146818rtc.h"
#include "blockdev.h" #include "blockdev.h"
#include "exec-memory.h"
#define MAX_IDE_BUS 2 #define MAX_IDE_BUS 2
@ -163,7 +164,8 @@ void mips_r4k_init (ram_addr_t ram_size,
{ {
char *filename; char *filename;
ram_addr_t ram_offset; ram_addr_t ram_offset;
ram_addr_t bios_offset; MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *bios = g_new(MemoryRegion, 1);
int bios_size; int bios_size;
CPUState *env; CPUState *env;
ResetData *reset_info; ResetData *reset_info;
@ -227,18 +229,20 @@ void mips_r4k_init (ram_addr_t ram_size,
be = 0; be = 0;
#endif #endif
if ((bios_size > 0) && (bios_size <= BIOS_SIZE)) { if ((bios_size > 0) && (bios_size <= BIOS_SIZE)) {
bios_offset = qemu_ram_alloc(NULL, "mips_r4k.bios", BIOS_SIZE); memory_region_init_ram(bios, NULL, "mips_r4k.bios", BIOS_SIZE);
cpu_register_physical_memory(0x1fc00000, BIOS_SIZE, memory_region_set_readonly(bios, true);
bios_offset | IO_MEM_ROM); memory_region_add_subregion(address_space_mem, 0x1fc00000, bios);
load_image_targphys(filename, 0x1fc00000, BIOS_SIZE); load_image_targphys(filename, 0x1fc00000, BIOS_SIZE);
} else if ((dinfo = drive_get(IF_PFLASH, 0, 0)) != NULL) { } else if ((dinfo = drive_get(IF_PFLASH, 0, 0)) != NULL) {
uint32_t mips_rom = 0x00400000; uint32_t mips_rom = 0x00400000;
bios_offset = qemu_ram_alloc(NULL, "mips_r4k.bios", mips_rom); memory_region_init_rom_device(bios,
if (!pflash_cfi01_register(0x1fc00000, bios_offset, (be ? &pflash_cfi01_ops_be
: &pflash_cfi01_ops_le),
NULL, "mips_r4k.bios", mips_rom);
if (!pflash_cfi01_register(0x1fc00000, bios,
dinfo->bdrv, sector_len, dinfo->bdrv, sector_len,
mips_rom / sector_len, mips_rom / sector_len,
4, 0, 0, 0, 0, be)) { 4, 0, 0, 0, 0)) {
fprintf(stderr, "qemu: Error registering flash memory.\n"); fprintf(stderr, "qemu: Error registering flash memory.\n");
} }
} }

15
hw/musicpal.c
View File

@ -1502,6 +1502,7 @@ static void musicpal_init(ram_addr_t ram_size,
unsigned long flash_size; unsigned long flash_size;
DriveInfo *dinfo; DriveInfo *dinfo;
ram_addr_t sram_off; ram_addr_t sram_off;
MemoryRegion *flash = g_new(MemoryRegion, 1);
if (!cpu_model) { if (!cpu_model) {
cpu_model = "arm926"; cpu_model = "arm926";
@ -1565,21 +1566,23 @@ static void musicpal_init(ram_addr_t ram_size,
* image is smaller than 32 MB. * image is smaller than 32 MB.
*/ */
#ifdef TARGET_WORDS_BIGENDIAN #ifdef TARGET_WORDS_BIGENDIAN
pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, qemu_ram_alloc(NULL, memory_region_init_rom_device(flash, &pflash_cfi02_ops_be,
"musicpal.flash", flash_size), NULL, "musicpal.flash", flash_size);
pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, flash,
dinfo->bdrv, 0x10000, dinfo->bdrv, 0x10000,
(flash_size + 0xffff) >> 16, (flash_size + 0xffff) >> 16,
MP_FLASH_SIZE_MAX / flash_size, MP_FLASH_SIZE_MAX / flash_size,
2, 0x00BF, 0x236D, 0x0000, 0x0000, 2, 0x00BF, 0x236D, 0x0000, 0x0000,
0x5555, 0x2AAA, 1); 0x5555, 0x2AAA);
#else #else
pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, qemu_ram_alloc(NULL, memory_region_init_rom_device(flash, &pflash_cfi02_ops_le,
"musicpal.flash", flash_size), NULL, "musicpal.flash", flash_size);
pflash_cfi02_register(0-MP_FLASH_SIZE_MAX, flash,
dinfo->bdrv, 0x10000, dinfo->bdrv, 0x10000,
(flash_size + 0xffff) >> 16, (flash_size + 0xffff) >> 16,
MP_FLASH_SIZE_MAX / flash_size, MP_FLASH_SIZE_MAX / flash_size,
2, 0x00BF, 0x236D, 0x0000, 0x0000, 2, 0x00BF, 0x236D, 0x0000, 0x0000,
0x5555, 0x2AAA, 0); 0x5555, 0x2AAA);
#endif #endif
} }

21
hw/omap_sx1.c
View File

@ -129,7 +129,8 @@ static void sx1_init(ram_addr_t ram_size,
DriveInfo *dinfo; DriveInfo *dinfo;
int fl_idx; int fl_idx;
uint32_t flash_size = flash0_size; uint32_t flash_size = flash0_size;
int be; const MemoryRegionOps *flash_ops;
MemoryRegion *flash = g_new(MemoryRegion, 2);
if (version == 2) { if (version == 2) {
flash_size = flash2_size; flash_size = flash2_size;
@ -155,17 +156,18 @@ static void sx1_init(ram_addr_t ram_size,
fl_idx = 0; fl_idx = 0;
#ifdef TARGET_WORDS_BIGENDIAN #ifdef TARGET_WORDS_BIGENDIAN
be = 1; flash_ops = &pflash_cfi01_ops_be;
#else #else
be = 0; flash_ops = &pflash_cfi01_ops_le;
#endif #endif
if ((dinfo = drive_get(IF_PFLASH, 0, fl_idx)) != NULL) { if ((dinfo = drive_get(IF_PFLASH, 0, fl_idx)) != NULL) {
if (!pflash_cfi01_register(OMAP_CS0_BASE, qemu_ram_alloc(NULL, memory_region_init_rom_device(&flash[0], flash_ops,
"omap_sx1.flash0-1", flash_size), NULL, "omap_sx1.flash0-1", flash_size);
if (!pflash_cfi01_register(OMAP_CS0_BASE, &flash[0],
dinfo->bdrv, sector_size, dinfo->bdrv, sector_size,
flash_size / sector_size, flash_size / sector_size,
4, 0, 0, 0, 0, be)) { 4, 0, 0, 0, 0)) {
fprintf(stderr, "qemu: Error registering flash memory %d.\n", fprintf(stderr, "qemu: Error registering flash memory %d.\n",
fl_idx); fl_idx);
} }
@ -182,11 +184,12 @@ static void sx1_init(ram_addr_t ram_size,
cpu_register_physical_memory(OMAP_CS1_BASE + flash1_size, cpu_register_physical_memory(OMAP_CS1_BASE + flash1_size,
OMAP_CS1_SIZE - flash1_size, io); OMAP_CS1_SIZE - flash1_size, io);
if (!pflash_cfi01_register(OMAP_CS1_BASE, qemu_ram_alloc(NULL, memory_region_init_rom_device(&flash[1], flash_ops,
"omap_sx1.flash1-1", flash1_size), NULL, "omap_sx1.flash1-1", flash1_size);
if (!pflash_cfi01_register(OMAP_CS1_BASE, &flash[1],
dinfo->bdrv, sector_size, dinfo->bdrv, sector_size,
flash1_size / sector_size, flash1_size / sector_size,
4, 0, 0, 0, 0, be)) { 4, 0, 0, 0, 0)) {
fprintf(stderr, "qemu: Error registering flash memory %d.\n", fprintf(stderr, "qemu: Error registering flash memory %d.\n",
fl_idx); fl_idx);
} }

7
hw/petalogix_ml605_mmu.c
View File

@ -149,7 +149,7 @@ petalogix_ml605_init(ram_addr_t ram_size,
target_phys_addr_t ddr_base = MEMORY_BASEADDR; target_phys_addr_t ddr_base = MEMORY_BASEADDR;
ram_addr_t phys_lmb_bram; ram_addr_t phys_lmb_bram;
ram_addr_t phys_ram; ram_addr_t phys_ram;
ram_addr_t phys_flash; MemoryRegion *phys_flash = g_new(MemoryRegion, 1);
qemu_irq irq[32], *cpu_irq; qemu_irq irq[32], *cpu_irq;
/* init CPUs */ /* init CPUs */
@ -169,14 +169,15 @@ petalogix_ml605_init(ram_addr_t ram_size,
phys_ram = qemu_ram_alloc(NULL, "petalogix_ml605.ram", ram_size); phys_ram = qemu_ram_alloc(NULL, "petalogix_ml605.ram", ram_size);
cpu_register_physical_memory(ddr_base, ram_size, phys_ram | IO_MEM_RAM); cpu_register_physical_memory(ddr_base, ram_size, phys_ram | IO_MEM_RAM);
phys_flash = qemu_ram_alloc(NULL, "petalogix_ml605.flash", FLASH_SIZE); memory_region_init_rom_device(phys_flash, &pflash_cfi01_ops_le,
NULL, "petalogix_ml605.flash", FLASH_SIZE);
dinfo = drive_get(IF_PFLASH, 0, 0); dinfo = drive_get(IF_PFLASH, 0, 0);
/* 5th parameter 2 means bank-width /* 5th parameter 2 means bank-width
* 10th paremeter 0 means little-endian */ * 10th paremeter 0 means little-endian */
pflash_cfi01_register(FLASH_BASEADDR, phys_flash, pflash_cfi01_register(FLASH_BASEADDR, phys_flash,
dinfo ? dinfo->bdrv : NULL, (64 * 1024), dinfo ? dinfo->bdrv : NULL, (64 * 1024),
FLASH_SIZE >> 16, FLASH_SIZE >> 16,
2, 0x89, 0x18, 0x0000, 0x0, 0); 2, 0x89, 0x18, 0x0000, 0x0);
cpu_irq = microblaze_pic_init_cpu(env); cpu_irq = microblaze_pic_init_cpu(env);

8
hw/petalogix_s3adsp1800_mmu.c
View File

@ -127,7 +127,7 @@ petalogix_s3adsp1800_init(ram_addr_t ram_size,
target_phys_addr_t ddr_base = 0x90000000; target_phys_addr_t ddr_base = 0x90000000;
ram_addr_t phys_lmb_bram; ram_addr_t phys_lmb_bram;
ram_addr_t phys_ram; ram_addr_t phys_ram;
ram_addr_t phys_flash; MemoryRegion *phys_flash = g_new(MemoryRegion, 1);
qemu_irq irq[32], *cpu_irq; qemu_irq irq[32], *cpu_irq;
/* init CPUs */ /* init CPUs */
@ -148,12 +148,14 @@ petalogix_s3adsp1800_init(ram_addr_t ram_size,
phys_ram = qemu_ram_alloc(NULL, "petalogix_s3adsp1800.ram", ram_size); phys_ram = qemu_ram_alloc(NULL, "petalogix_s3adsp1800.ram", ram_size);
cpu_register_physical_memory(ddr_base, ram_size, phys_ram | IO_MEM_RAM); cpu_register_physical_memory(ddr_base, ram_size, phys_ram | IO_MEM_RAM);
phys_flash = qemu_ram_alloc(NULL, "petalogix_s3adsp1800.flash", FLASH_SIZE); memory_region_init_rom_device(phys_flash, &pflash_cfi01_ops_be,
NULL, "petalogix_s3adsp1800.flash",
FLASH_SIZE);
dinfo = drive_get(IF_PFLASH, 0, 0); dinfo = drive_get(IF_PFLASH, 0, 0);
pflash_cfi01_register(0xa0000000, phys_flash, pflash_cfi01_register(0xa0000000, phys_flash,
dinfo ? dinfo->bdrv : NULL, (64 * 1024), dinfo ? dinfo->bdrv : NULL, (64 * 1024),
FLASH_SIZE >> 16, FLASH_SIZE >> 16,
1, 0x89, 0x18, 0x0000, 0x0, 1); 1, 0x89, 0x18, 0x0000, 0x0);
cpu_irq = microblaze_pic_init_cpu(env); cpu_irq = microblaze_pic_init_cpu(env);
dev = xilinx_intc_create(0x81800000, cpu_irq[0], 2); dev = xilinx_intc_create(0x81800000, cpu_irq[0], 2);

67
hw/pflash_cfi01.c
View File

@ -40,6 +40,7 @@
#include "flash.h" #include "flash.h"
#include "block.h" #include "block.h"
#include "qemu-timer.h" #include "qemu-timer.h"
#include "exec-memory.h"
#define PFLASH_BUG(fmt, ...) \ #define PFLASH_BUG(fmt, ...) \
do { \ do { \
@ -74,8 +75,7 @@ struct pflash_t {
target_phys_addr_t counter; target_phys_addr_t counter;
unsigned int writeblock_size; unsigned int writeblock_size;
QEMUTimer *timer; QEMUTimer *timer;
ram_addr_t off; MemoryRegion *mem;
int fl_mem;
void *storage; void *storage;
}; };
@ -89,8 +89,7 @@ static void pflash_timer (void *opaque)
if (pfl->bypass) { if (pfl->bypass) {
pfl->wcycle = 2; pfl->wcycle = 2;
} else { } else {
cpu_register_physical_memory(pfl->base, pfl->total_len, memory_region_rom_device_set_readable(pfl->mem, true);
pfl->off | IO_MEM_ROMD | pfl->fl_mem);
pfl->wcycle = 0; pfl->wcycle = 0;
} }
pfl->cmd = 0; pfl->cmd = 0;
@ -263,7 +262,7 @@ static void pflash_write(pflash_t *pfl, target_phys_addr_t offset,
if (!pfl->wcycle) { if (!pfl->wcycle) {
/* Set the device in I/O access mode */ /* Set the device in I/O access mode */
cpu_register_physical_memory(pfl->base, pfl->total_len, pfl->fl_mem); memory_region_rom_device_set_readable(pfl->mem, false);
} }
switch (pfl->wcycle) { switch (pfl->wcycle) {
@ -422,8 +421,7 @@ static void pflash_write(pflash_t *pfl, target_phys_addr_t offset,
__func__, offset, pfl->wcycle, pfl->cmd, value); __func__, offset, pfl->wcycle, pfl->cmd, value);
reset_flash: reset_flash:
cpu_register_physical_memory(pfl->base, pfl->total_len, memory_region_rom_device_set_readable(pfl->mem, true);
pfl->off | IO_MEM_ROMD | pfl->fl_mem);
pfl->bypass = 0; pfl->bypass = 0;
pfl->wcycle = 0; pfl->wcycle = 0;
@ -514,28 +512,20 @@ static void pflash_writel_le(void *opaque, target_phys_addr_t addr,
pflash_write(pfl, addr, value, 4, 0); pflash_write(pfl, addr, value, 4, 0);
} }
static CPUWriteMemoryFunc * const pflash_write_ops_be[] = { const MemoryRegionOps pflash_cfi01_ops_be = {
&pflash_writeb_be, .old_mmio = {
&pflash_writew_be, .read = { pflash_readb_be, pflash_readw_be, pflash_readl_be, },
&pflash_writel_be, .write = { pflash_writeb_be, pflash_writew_be, pflash_writel_be, },
},
.endianness = DEVICE_NATIVE_ENDIAN,
}; };
static CPUReadMemoryFunc * const pflash_read_ops_be[] = { const MemoryRegionOps pflash_cfi01_ops_le = {
&pflash_readb_be, .old_mmio = {
&pflash_readw_be, .read = { pflash_readb_le, pflash_readw_le, pflash_readl_le, },
&pflash_readl_be, .write = { pflash_writeb_le, pflash_writew_le, pflash_writel_le, },
}; },
.endianness = DEVICE_NATIVE_ENDIAN,
static CPUWriteMemoryFunc * const pflash_write_ops_le[] = {
&pflash_writeb_le,
&pflash_writew_le,
&pflash_writel_le,
};
static CPUReadMemoryFunc * const pflash_read_ops_le[] = {
&pflash_readb_le,
&pflash_readw_le,
&pflash_readl_le,
}; };
/* Count trailing zeroes of a 32 bits quantity */ /* Count trailing zeroes of a 32 bits quantity */
@ -574,12 +564,11 @@ static int ctz32 (uint32_t n)
return ret; return ret;
} }
pflash_t *pflash_cfi01_register(target_phys_addr_t base, ram_addr_t off, pflash_t *pflash_cfi01_register(target_phys_addr_t base, MemoryRegion *mem,
BlockDriverState *bs, uint32_t sector_len, BlockDriverState *bs, uint32_t sector_len,
int nb_blocs, int width, int nb_blocs, int width,
uint16_t id0, uint16_t id1, uint16_t id0, uint16_t id1,
uint16_t id2, uint16_t id3, uint16_t id2, uint16_t id3)
int be)
{ {
pflash_t *pfl; pflash_t *pfl;
target_phys_addr_t total_len; target_phys_addr_t total_len;
@ -597,26 +586,16 @@ pflash_t *pflash_cfi01_register(target_phys_addr_t base, ram_addr_t off,
pfl = g_malloc0(sizeof(pflash_t)); pfl = g_malloc0(sizeof(pflash_t));
/* FIXME: Allocate ram ourselves. */ /* FIXME: Allocate ram ourselves. */
pfl->storage = qemu_get_ram_ptr(off); pfl->storage = memory_region_get_ram_ptr(mem);
if (be) { pfl->mem = mem;
pfl->fl_mem = cpu_register_io_memory(pflash_read_ops_be, memory_region_add_subregion(get_system_memory(), base, mem);
pflash_write_ops_be, pfl,
DEVICE_NATIVE_ENDIAN);
} else {
pfl->fl_mem = cpu_register_io_memory(pflash_read_ops_le,
pflash_write_ops_le, pfl,
DEVICE_NATIVE_ENDIAN);
}
pfl->off = off;
cpu_register_physical_memory(base, total_len,
off | pfl->fl_mem | IO_MEM_ROMD);
pfl->bs = bs; pfl->bs = bs;
if (pfl->bs) { if (pfl->bs) {
/* read the initial flash content */ /* read the initial flash content */
ret = bdrv_read(pfl->bs, 0, pfl->storage, total_len >> 9); ret = bdrv_read(pfl->bs, 0, pfl->storage, total_len >> 9);
if (ret < 0) { if (ret < 0) {
cpu_unregister_io_memory(pfl->fl_mem); memory_region_del_subregion(get_system_memory(), mem);
g_free(pfl); g_free(pfl);
return NULL; return NULL;
} }

93
hw/pflash_cfi02.c
View File

@ -39,6 +39,7 @@
#include "flash.h" #include "flash.h"
#include "qemu-timer.h" #include "qemu-timer.h"
#include "block.h" #include "block.h"
#include "exec-memory.h"
//#define PFLASH_DEBUG //#define PFLASH_DEBUG
#ifdef PFLASH_DEBUG #ifdef PFLASH_DEBUG
@ -69,25 +70,39 @@ struct pflash_t {
uint8_t cfi_len; uint8_t cfi_len;
uint8_t cfi_table[0x52]; uint8_t cfi_table[0x52];
QEMUTimer *timer; QEMUTimer *timer;
ram_addr_t off; /* The device replicates the flash memory across its memory space. Emulate
int fl_mem; * that by having a container (.mem) filled with an array of aliases
* (.mem_mappings) pointing to the flash memory (.orig_mem).
*/
MemoryRegion mem;
MemoryRegion *mem_mappings; /* array; one per mapping */
MemoryRegion *orig_mem;
int rom_mode; int rom_mode;
int read_counter; /* used for lazy switch-back to rom mode */ int read_counter; /* used for lazy switch-back to rom mode */
void *storage; void *storage;
}; };
/*
* Set up replicated mappings of the same region.
*/
static void pflash_setup_mappings(pflash_t *pfl, MemoryRegion *mem)
{
unsigned i;
target_phys_addr_t size = memory_region_size(mem);
pfl->orig_mem = mem;
memory_region_init(&pfl->mem, "pflash", pfl->mappings * size);
pfl->mem_mappings = g_new(MemoryRegion, pfl->mappings);
for (i = 0; i < pfl->mappings; ++i) {
memory_region_init_alias(&pfl->mem_mappings[i], "pflash-alias", mem,
0, size);
memory_region_add_subregion(&pfl->mem, i * size, &pfl->mem_mappings[i]);
}
}
static void pflash_register_memory(pflash_t *pfl, int rom_mode) static void pflash_register_memory(pflash_t *pfl, int rom_mode)
{ {
unsigned long phys_offset = pfl->fl_mem; memory_region_rom_device_set_readable(pfl->orig_mem, rom_mode);
int i;
if (rom_mode)
phys_offset |= pfl->off | IO_MEM_ROMD;
pfl->rom_mode = rom_mode;
for (i = 0; i < pfl->mappings; i++)
cpu_register_physical_memory(pfl->base + i * pfl->chip_len,
pfl->chip_len, phys_offset);
} }
static void pflash_timer (void *opaque) static void pflash_timer (void *opaque)
@ -538,28 +553,20 @@ static void pflash_writel_le(void *opaque, target_phys_addr_t addr,
pflash_write(pfl, addr, value, 4, 0); pflash_write(pfl, addr, value, 4, 0);
} }
static CPUWriteMemoryFunc * const pflash_write_ops_be[] = { const MemoryRegionOps pflash_cfi02_ops_be = {
&pflash_writeb_be, .old_mmio = {
&pflash_writew_be, .read = { pflash_readb_be, pflash_readw_be, pflash_readl_be, },
&pflash_writel_be, .write = { pflash_writeb_be, pflash_writew_be, pflash_writel_be, },
},
.endianness = DEVICE_NATIVE_ENDIAN,
}; };
static CPUReadMemoryFunc * const pflash_read_ops_be[] = { const MemoryRegionOps pflash_cfi02_ops_le = {
&pflash_readb_be, .old_mmio = {
&pflash_readw_be, .read = { pflash_readb_le, pflash_readw_le, pflash_readl_le, },
&pflash_readl_be, .write = { pflash_writeb_le, pflash_writew_le, pflash_writel_le, },
}; },
.endianness = DEVICE_NATIVE_ENDIAN,
static CPUWriteMemoryFunc * const pflash_write_ops_le[] = {
&pflash_writeb_le,
&pflash_writew_le,
&pflash_writel_le,
};
static CPUReadMemoryFunc * const pflash_read_ops_le[] = {
&pflash_readb_le,
&pflash_readw_le,
&pflash_readl_le,
}; };
/* Count trailing zeroes of a 32 bits quantity */ /* Count trailing zeroes of a 32 bits quantity */
@ -598,13 +605,12 @@ static int ctz32 (uint32_t n)
return ret; return ret;
} }
pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off, pflash_t *pflash_cfi02_register(target_phys_addr_t base, MemoryRegion *mem,
BlockDriverState *bs, uint32_t sector_len, BlockDriverState *bs, uint32_t sector_len,
int nb_blocs, int nb_mappings, int width, int nb_blocs, int nb_mappings, int width,
uint16_t id0, uint16_t id1, uint16_t id0, uint16_t id1,
uint16_t id2, uint16_t id3, uint16_t id2, uint16_t id3,
uint16_t unlock_addr0, uint16_t unlock_addr1, uint16_t unlock_addr0, uint16_t unlock_addr1)
int be)
{ {
pflash_t *pfl; pflash_t *pfl;
int32_t chip_len; int32_t chip_len;
@ -619,31 +625,22 @@ pflash_t *pflash_cfi02_register(target_phys_addr_t base, ram_addr_t off,
#endif #endif
pfl = g_malloc0(sizeof(pflash_t)); pfl = g_malloc0(sizeof(pflash_t));
/* FIXME: Allocate ram ourselves. */ /* FIXME: Allocate ram ourselves. */
pfl->storage = qemu_get_ram_ptr(off); pfl->storage = memory_region_get_ram_ptr(mem);
if (be) {
pfl->fl_mem = cpu_register_io_memory(pflash_read_ops_be,
pflash_write_ops_be,
pfl, DEVICE_NATIVE_ENDIAN);
} else {
pfl->fl_mem = cpu_register_io_memory(pflash_read_ops_le,
pflash_write_ops_le,
pfl, DEVICE_NATIVE_ENDIAN);
}
pfl->off = off;
pfl->base = base; pfl->base = base;
pfl->chip_len = chip_len; pfl->chip_len = chip_len;
pfl->mappings = nb_mappings; pfl->mappings = nb_mappings;
pflash_register_memory(pfl, 1);
pfl->bs = bs; pfl->bs = bs;
if (pfl->bs) { if (pfl->bs) {
/* read the initial flash content */ /* read the initial flash content */
ret = bdrv_read(pfl->bs, 0, pfl->storage, chip_len >> 9); ret = bdrv_read(pfl->bs, 0, pfl->storage, chip_len >> 9);
if (ret < 0) { if (ret < 0) {
cpu_unregister_io_memory(pfl->fl_mem);
g_free(pfl); g_free(pfl);
return NULL; return NULL;
} }
} }
pflash_setup_mappings(pfl, mem);
pfl->rom_mode = 1;
memory_region_add_subregion(get_system_memory(), pfl->base, &pfl->mem);
#if 0 /* XXX: there should be a bit to set up read-only, #if 0 /* XXX: there should be a bit to set up read-only,
* the same way the hardware does (with WP pin). * the same way the hardware does (with WP pin).
*/ */

63
hw/ppc405_boards.c
View File

@ -32,6 +32,7 @@
#include "qemu-log.h" #include "qemu-log.h"
#include "loader.h" #include "loader.h"
#include "blockdev.h" #include "blockdev.h"
#include "exec-memory.h"
#define BIOS_FILENAME "ppc405_rom.bin" #define BIOS_FILENAME "ppc405_rom.bin"
#define BIOS_SIZE (2048 * 1024) #define BIOS_SIZE (2048 * 1024)
@ -181,7 +182,9 @@ static void ref405ep_init (ram_addr_t ram_size,
ppc4xx_bd_info_t bd; ppc4xx_bd_info_t bd;
CPUPPCState *env; CPUPPCState *env;
qemu_irq *pic; qemu_irq *pic;
ram_addr_t sram_offset, bios_offset, bdloc; ram_addr_t sram_offset, bdloc;
MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *bios = g_new(MemoryRegion, 1);
MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories)); MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories));
target_phys_addr_t ram_bases[2], ram_sizes[2]; target_phys_addr_t ram_bases[2], ram_sizes[2];
target_ulong sram_size; target_ulong sram_size;
@ -224,18 +227,18 @@ static void ref405ep_init (ram_addr_t ram_size,
dinfo = drive_get(IF_PFLASH, 0, fl_idx); dinfo = drive_get(IF_PFLASH, 0, fl_idx);
if (dinfo) { if (dinfo) {
bios_size = bdrv_getlength(dinfo->bdrv); bios_size = bdrv_getlength(dinfo->bdrv);
bios_offset = qemu_ram_alloc(NULL, "ef405ep.bios", bios_size); memory_region_init_rom_device(bios, &pflash_cfi02_ops_be,
NULL, "ef405ep.bios", bios_size);
fl_sectors = (bios_size + 65535) >> 16; fl_sectors = (bios_size + 65535) >> 16;
#ifdef DEBUG_BOARD_INIT #ifdef DEBUG_BOARD_INIT
printf("Register parallel flash %d size %lx" printf("Register parallel flash %d size %lx"
" at offset %08lx addr %lx '%s' %d\n", " at addr %lx '%s' %d\n",
fl_idx, bios_size, bios_offset, -bios_size, fl_idx, bios_size, -bios_size,
bdrv_get_device_name(dinfo->bdrv), fl_sectors); bdrv_get_device_name(dinfo->bdrv), fl_sectors);
#endif #endif
pflash_cfi02_register((uint32_t)(-bios_size), bios_offset, pflash_cfi02_register((uint32_t)(-bios_size), bios,
dinfo->bdrv, 65536, fl_sectors, 1, dinfo->bdrv, 65536, fl_sectors, 1,
2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA, 2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA);
1);
fl_idx++; fl_idx++;
} else } else
#endif #endif
@ -243,12 +246,12 @@ static void ref405ep_init (ram_addr_t ram_size,
#ifdef DEBUG_BOARD_INIT #ifdef DEBUG_BOARD_INIT
printf("Load BIOS from file\n"); printf("Load BIOS from file\n");
#endif #endif
bios_offset = qemu_ram_alloc(NULL, "ef405ep.bios", BIOS_SIZE); memory_region_init_ram(bios, NULL, "ef405ep.bios", BIOS_SIZE);
if (bios_name == NULL) if (bios_name == NULL)
bios_name = BIOS_FILENAME; bios_name = BIOS_FILENAME;
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
if (filename) { if (filename) {
bios_size = load_image(filename, qemu_get_ram_ptr(bios_offset)); bios_size = load_image(filename, memory_region_get_ram_ptr(bios));
g_free(filename); g_free(filename);
} else { } else {
bios_size = -1; bios_size = -1;
@ -259,8 +262,9 @@ static void ref405ep_init (ram_addr_t ram_size,
exit(1); exit(1);
} }
bios_size = (bios_size + 0xfff) & ~0xfff; bios_size = (bios_size + 0xfff) & ~0xfff;
cpu_register_physical_memory((uint32_t)(-bios_size), memory_region_set_readonly(bios, true);
bios_size, bios_offset | IO_MEM_ROM); memory_region_add_subregion(address_space_mem, (uint32_t)(-bios_size),
bios);
} }
/* Register FPGA */ /* Register FPGA */
#ifdef DEBUG_BOARD_INIT #ifdef DEBUG_BOARD_INIT
@ -507,7 +511,9 @@ static void taihu_405ep_init(ram_addr_t ram_size,
{ {
char *filename; char *filename;
qemu_irq *pic; qemu_irq *pic;
ram_addr_t bios_offset; MemoryRegion *address_space_mem = get_system_memory();
MemoryRegion *bios = g_new(MemoryRegion, 1);
MemoryRegion *flash = g_new(MemoryRegion, 1);
MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories)); MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories));
target_phys_addr_t ram_bases[2], ram_sizes[2]; target_phys_addr_t ram_bases[2], ram_sizes[2];
long bios_size; long bios_size;
@ -544,17 +550,17 @@ static void taihu_405ep_init(ram_addr_t ram_size,
/* XXX: should check that size is 2MB */ /* XXX: should check that size is 2MB */
// bios_size = 2 * 1024 * 1024; // bios_size = 2 * 1024 * 1024;
fl_sectors = (bios_size + 65535) >> 16; fl_sectors = (bios_size + 65535) >> 16;
bios_offset = qemu_ram_alloc(NULL, "taihu_405ep.bios", bios_size); memory_region_init_rom_device(bios, &pflash_cfi02_ops_be,
NULL, "taihu_405ep.bios", bios_size);
#ifdef DEBUG_BOARD_INIT #ifdef DEBUG_BOARD_INIT
printf("Register parallel flash %d size %lx" printf("Register parallel flash %d size %lx"
" at offset %08lx addr %lx '%s' %d\n", " at addr %lx '%s' %d\n",
fl_idx, bios_size, bios_offset, -bios_size, fl_idx, bios_size, -bios_size,
bdrv_get_device_name(dinfo->bdrv), fl_sectors); bdrv_get_device_name(dinfo->bdrv), fl_sectors);
#endif #endif
pflash_cfi02_register((uint32_t)(-bios_size), bios_offset, pflash_cfi02_register((uint32_t)(-bios_size), bios,
dinfo->bdrv, 65536, fl_sectors, 1, dinfo->bdrv, 65536, fl_sectors, 1,
4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA, 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA);
1);
fl_idx++; fl_idx++;
} else } else
#endif #endif
@ -564,10 +570,10 @@ static void taihu_405ep_init(ram_addr_t ram_size,
#endif #endif
if (bios_name == NULL) if (bios_name == NULL)
bios_name = BIOS_FILENAME; bios_name = BIOS_FILENAME;
bios_offset = qemu_ram_alloc(NULL, "taihu_405ep.bios", BIOS_SIZE); memory_region_init_ram(bios, NULL, "taihu_405ep.bios", BIOS_SIZE);
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
if (filename) { if (filename) {
bios_size = load_image(filename, qemu_get_ram_ptr(bios_offset)); bios_size = load_image(filename, memory_region_get_ram_ptr(bios));
g_free(filename); g_free(filename);
} else { } else {
bios_size = -1; bios_size = -1;
@ -578,8 +584,9 @@ static void taihu_405ep_init(ram_addr_t ram_size,
exit(1); exit(1);
} }
bios_size = (bios_size + 0xfff) & ~0xfff; bios_size = (bios_size + 0xfff) & ~0xfff;
cpu_register_physical_memory((uint32_t)(-bios_size), memory_region_set_readonly(bios, true);
bios_size, bios_offset | IO_MEM_ROM); memory_region_add_subregion(address_space_mem,
(uint32_t)(-bios_size), bios);
} }
/* Register Linux flash */ /* Register Linux flash */
dinfo = drive_get(IF_PFLASH, 0, fl_idx); dinfo = drive_get(IF_PFLASH, 0, fl_idx);
@ -590,15 +597,15 @@ static void taihu_405ep_init(ram_addr_t ram_size,
fl_sectors = (bios_size + 65535) >> 16; fl_sectors = (bios_size + 65535) >> 16;
#ifdef DEBUG_BOARD_INIT #ifdef DEBUG_BOARD_INIT
printf("Register parallel flash %d size %lx" printf("Register parallel flash %d size %lx"
" at offset %08lx addr " TARGET_FMT_lx " '%s'\n", " at addr " TARGET_FMT_lx " '%s'\n",
fl_idx, bios_size, bios_offset, (target_ulong)0xfc000000, fl_idx, bios_size, (target_ulong)0xfc000000,
bdrv_get_device_name(dinfo->bdrv)); bdrv_get_device_name(dinfo->bdrv));
#endif #endif
bios_offset = qemu_ram_alloc(NULL, "taihu_405ep.flash", bios_size); memory_region_init_rom_device(flash, &pflash_cfi02_ops_be,
pflash_cfi02_register(0xfc000000, bios_offset, NULL, "taihu_405ep.flash", bios_size);
pflash_cfi02_register(0xfc000000, flash,
dinfo->bdrv, 65536, fl_sectors, 1, dinfo->bdrv, 65536, fl_sectors, 1,
4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA, 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA);
1);
fl_idx++; fl_idx++;
} }
/* Register CLPD & LCD display */ /* Register CLPD & LCD display */

7
hw/r2d.c
View File

@ -235,6 +235,7 @@ static void r2d_init(ram_addr_t ram_size,
qemu_irq *irq; qemu_irq *irq;
DriveInfo *dinfo; DriveInfo *dinfo;
int i; int i;
MemoryRegion *flash = g_new(MemoryRegion, 1);
if (!cpu_model) if (!cpu_model)
cpu_model = "SH7751R"; cpu_model = "SH7751R";
@ -267,11 +268,13 @@ static void r2d_init(ram_addr_t ram_size,
/* onboard flash memory */ /* onboard flash memory */
dinfo = drive_get(IF_PFLASH, 0, 0); dinfo = drive_get(IF_PFLASH, 0, 0);
pflash_cfi02_register(0x0, qemu_ram_alloc(NULL, "r2d.flash", FLASH_SIZE), memory_region_init_rom_device(flash, &pflash_cfi02_ops_le,
NULL, "r2d.flash", FLASH_SIZE);
pflash_cfi02_register(0x0, flash,
dinfo ? dinfo->bdrv : NULL, (16 * 1024), dinfo ? dinfo->bdrv : NULL, (16 * 1024),
FLASH_SIZE >> 16, FLASH_SIZE >> 16,
1, 4, 0x0000, 0x0000, 0x0000, 0x0000, 1, 4, 0x0000, 0x0000, 0x0000, 0x0000,
0x555, 0x2aa, 0); 0x555, 0x2aa);
/* NIC: rtl8139 on-board, and 2 slots. */ /* NIC: rtl8139 on-board, and 2 slots. */
for (i = 0; i < nb_nics; i++) for (i = 0; i < nb_nics; i++)

7
hw/virtex_ml507.c
View File

@ -196,7 +196,7 @@ static void virtex_init(ram_addr_t ram_size,
target_phys_addr_t ram_base = 0; target_phys_addr_t ram_base = 0;
DriveInfo *dinfo; DriveInfo *dinfo;
ram_addr_t phys_ram; ram_addr_t phys_ram;
ram_addr_t phys_flash; MemoryRegion *phys_flash = g_new(MemoryRegion, 1);
qemu_irq irq[32], *cpu_irq; qemu_irq irq[32], *cpu_irq;
clk_setup_t clk_setup[7]; clk_setup_t clk_setup[7];
int kernel_size; int kernel_size;
@ -215,12 +215,13 @@ static void virtex_init(ram_addr_t ram_size,
phys_ram = qemu_ram_alloc(NULL, "ram", ram_size); phys_ram = qemu_ram_alloc(NULL, "ram", ram_size);
cpu_register_physical_memory(ram_base, ram_size, phys_ram | IO_MEM_RAM); cpu_register_physical_memory(ram_base, ram_size, phys_ram | IO_MEM_RAM);
phys_flash = qemu_ram_alloc(NULL, "virtex.flash", FLASH_SIZE); memory_region_init_rom_device(phys_flash, &pflash_cfi01_ops_be,
NULL, "virtex.flash", FLASH_SIZE);
dinfo = drive_get(IF_PFLASH, 0, 0); dinfo = drive_get(IF_PFLASH, 0, 0);
pflash_cfi01_register(0xfc000000, phys_flash, pflash_cfi01_register(0xfc000000, phys_flash,
dinfo ? dinfo->bdrv : NULL, (64 * 1024), dinfo ? dinfo->bdrv : NULL, (64 * 1024),
FLASH_SIZE >> 16, FLASH_SIZE >> 16,
1, 0x89, 0x18, 0x0000, 0x0, 1); 1, 0x89, 0x18, 0x0000, 0x0);
cpu_irq = (qemu_irq *) &env->irq_inputs[PPC40x_INPUT_INT]; cpu_irq = (qemu_irq *) &env->irq_inputs[PPC40x_INPUT_INT];
dev = xilinx_intc_create(0x81800000, cpu_irq[0], 0); dev = xilinx_intc_create(0x81800000, cpu_irq[0], 0);

15
hw/z2.c
View File

@ -280,10 +280,11 @@ static void z2_init(ram_addr_t ram_size,
uint32_t sector_len = 0x10000; uint32_t sector_len = 0x10000;
PXA2xxState *cpu; PXA2xxState *cpu;
DriveInfo *dinfo; DriveInfo *dinfo;
int be; const MemoryRegionOps *flash_ops;
void *z2_lcd; void *z2_lcd;
i2c_bus *bus; i2c_bus *bus;
DeviceState *wm; DeviceState *wm;
MemoryRegion *flash = g_new(MemoryRegion, 1);
if (!cpu_model) { if (!cpu_model) {
cpu_model = "pxa270-c5"; cpu_model = "pxa270-c5";
@ -293,9 +294,9 @@ static void z2_init(ram_addr_t ram_size,
cpu = pxa270_init(z2_binfo.ram_size, cpu_model); cpu = pxa270_init(z2_binfo.ram_size, cpu_model);
#ifdef TARGET_WORDS_BIGENDIAN #ifdef TARGET_WORDS_BIGENDIAN
be = 1; flash_ops = &pflash_cfi01_ops_be;
#else #else
be = 0; flash_ops = &pflash_cfi01_ops_le;
#endif #endif
dinfo = drive_get(IF_PFLASH, 0, 0); dinfo = drive_get(IF_PFLASH, 0, 0);
if (!dinfo) { if (!dinfo) {
@ -304,11 +305,11 @@ static void z2_init(ram_addr_t ram_size,
exit(1); exit(1);
} }
if (!pflash_cfi01_register(Z2_FLASH_BASE, memory_region_init_rom_device(flash, flash_ops,
qemu_ram_alloc(NULL, "z2.flash0", Z2_FLASH_SIZE), NULL, "z2.flash0", Z2_FLASH_SIZE);
if (!pflash_cfi01_register(Z2_FLASH_BASE, flash,
dinfo->bdrv, sector_len, dinfo->bdrv, sector_len,
Z2_FLASH_SIZE / sector_len, 4, 0, 0, 0, 0, Z2_FLASH_SIZE / sector_len, 4, 0, 0, 0, 0)) {
be)) {
fprintf(stderr, "qemu: Error registering flash memory.\n"); fprintf(stderr, "qemu: Error registering flash memory.\n");
exit(1); exit(1);
} }