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fdc: use IsaDma interface instead of global DMA_* functions

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Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Message-id: 1453843944-26833-16-git-send-email-hpoussin@reactos.org
Signed-off-by: John Snow <jsnow@redhat.com>
This commit is contained in:
Hervé Poussineau 2016-02-03 11:28:58 -05:00 committed by John Snow
parent c3ae40e12c
commit c8a35f1cf0
1 changed files with 46 additions and 17 deletions
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63
hw/block/fdc.c
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@ -644,6 +644,7 @@ struct FDCtrl {
QEMUTimer *result_timer; QEMUTimer *result_timer;
int dma_chann; int dma_chann;
uint8_t phase; uint8_t phase;
IsaDma *dma;
/* Controller's identification */ /* Controller's identification */
uint8_t version; uint8_t version;
/* HW */ /* HW */
@ -1429,7 +1430,8 @@ static void fdctrl_stop_transfer(FDCtrl *fdctrl, uint8_t status0,
fdctrl->fifo[6] = FD_SECTOR_SC; fdctrl->fifo[6] = FD_SECTOR_SC;
fdctrl->data_dir = FD_DIR_READ; fdctrl->data_dir = FD_DIR_READ;
if (!(fdctrl->msr & FD_MSR_NONDMA)) { if (!(fdctrl->msr & FD_MSR_NONDMA)) {
DMA_release_DREQ(fdctrl->dma_chann); IsaDmaClass *k = ISADMA_GET_CLASS(fdctrl->dma);
k->release_DREQ(fdctrl->dma, fdctrl->dma_chann);
} }
fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO; fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
fdctrl->msr &= ~FD_MSR_NONDMA; fdctrl->msr &= ~FD_MSR_NONDMA;
@ -1515,27 +1517,43 @@ static void fdctrl_start_transfer(FDCtrl *fdctrl, int direction)
} }
fdctrl->eot = fdctrl->fifo[6]; fdctrl->eot = fdctrl->fifo[6];
if (fdctrl->dor & FD_DOR_DMAEN) { if (fdctrl->dor & FD_DOR_DMAEN) {
int dma_mode; IsaDmaTransferMode dma_mode;
IsaDmaClass *k = ISADMA_GET_CLASS(fdctrl->dma);
bool dma_mode_ok;
/* DMA transfer are enabled. Check if DMA channel is well programmed */ /* DMA transfer are enabled. Check if DMA channel is well programmed */
dma_mode = DMA_get_channel_mode(fdctrl->dma_chann); dma_mode = k->get_transfer_mode(fdctrl->dma, fdctrl->dma_chann);
dma_mode = (dma_mode >> 2) & 3;
FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d - %d)\n", FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d - %d)\n",
dma_mode, direction, dma_mode, direction,
(128 << fdctrl->fifo[5]) * (128 << fdctrl->fifo[5]) *
(cur_drv->last_sect - ks + 1), fdctrl->data_len); (cur_drv->last_sect - ks + 1), fdctrl->data_len);
if (((direction == FD_DIR_SCANE || direction == FD_DIR_SCANL || switch (direction) {
direction == FD_DIR_SCANH) && dma_mode == 0) || case FD_DIR_SCANE:
(direction == FD_DIR_WRITE && dma_mode == 2) || case FD_DIR_SCANL:
(direction == FD_DIR_READ && dma_mode == 1) || case FD_DIR_SCANH:
(direction == FD_DIR_VERIFY)) { dma_mode_ok = (dma_mode == ISADMA_TRANSFER_VERIFY);
break;
case FD_DIR_WRITE:
dma_mode_ok = (dma_mode == ISADMA_TRANSFER_WRITE);
break;
case FD_DIR_READ:
dma_mode_ok = (dma_mode == ISADMA_TRANSFER_READ);
break;
case FD_DIR_VERIFY:
dma_mode_ok = true;
break;
default:
dma_mode_ok = false;
break;
}
if (dma_mode_ok) {
/* No access is allowed until DMA transfer has completed */ /* No access is allowed until DMA transfer has completed */
fdctrl->msr &= ~FD_MSR_RQM; fdctrl->msr &= ~FD_MSR_RQM;
if (direction != FD_DIR_VERIFY) { if (direction != FD_DIR_VERIFY) {
/* Now, we just have to wait for the DMA controller to /* Now, we just have to wait for the DMA controller to
* recall us... * recall us...
*/ */
DMA_hold_DREQ(fdctrl->dma_chann); k->hold_DREQ(fdctrl->dma, fdctrl->dma_chann);
DMA_schedule(); k->schedule(fdctrl->dma);
} else { } else {
/* Start transfer */ /* Start transfer */
fdctrl_transfer_handler(fdctrl, fdctrl->dma_chann, 0, fdctrl_transfer_handler(fdctrl, fdctrl->dma_chann, 0,
@ -1574,12 +1592,14 @@ static int fdctrl_transfer_handler (void *opaque, int nchan,
FDrive *cur_drv; FDrive *cur_drv;
int len, start_pos, rel_pos; int len, start_pos, rel_pos;
uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00; uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00;
IsaDmaClass *k;
fdctrl = opaque; fdctrl = opaque;
if (fdctrl->msr & FD_MSR_RQM) { if (fdctrl->msr & FD_MSR_RQM) {
FLOPPY_DPRINTF("Not in DMA transfer mode !\n"); FLOPPY_DPRINTF("Not in DMA transfer mode !\n");
return 0; return 0;
} }
k = ISADMA_GET_CLASS(fdctrl->dma);
cur_drv = get_cur_drv(fdctrl); cur_drv = get_cur_drv(fdctrl);
if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL || if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL ||
fdctrl->data_dir == FD_DIR_SCANH) fdctrl->data_dir == FD_DIR_SCANH)
@ -1618,8 +1638,8 @@ static int fdctrl_transfer_handler (void *opaque, int nchan,
switch (fdctrl->data_dir) { switch (fdctrl->data_dir) {
case FD_DIR_READ: case FD_DIR_READ:
/* READ commands */ /* READ commands */
DMA_write_memory (nchan, fdctrl->fifo + rel_pos, k->write_memory(fdctrl->dma, nchan, fdctrl->fifo + rel_pos,
fdctrl->data_pos, len); fdctrl->data_pos, len);
break; break;
case FD_DIR_WRITE: case FD_DIR_WRITE:
/* WRITE commands */ /* WRITE commands */
@ -1633,8 +1653,8 @@ static int fdctrl_transfer_handler (void *opaque, int nchan,
goto transfer_error; goto transfer_error;
} }
DMA_read_memory (nchan, fdctrl->fifo + rel_pos, k->read_memory(fdctrl->dma, nchan, fdctrl->fifo + rel_pos,
fdctrl->data_pos, len); fdctrl->data_pos, len);
if (blk_write(cur_drv->blk, fd_sector(cur_drv), if (blk_write(cur_drv->blk, fd_sector(cur_drv),
fdctrl->fifo, 1) < 0) { fdctrl->fifo, 1) < 0) {
FLOPPY_DPRINTF("error writing sector %d\n", FLOPPY_DPRINTF("error writing sector %d\n",
@ -1651,7 +1671,8 @@ static int fdctrl_transfer_handler (void *opaque, int nchan,
{ {
uint8_t tmpbuf[FD_SECTOR_LEN]; uint8_t tmpbuf[FD_SECTOR_LEN];
int ret; int ret;
DMA_read_memory (nchan, tmpbuf, fdctrl->data_pos, len); k->read_memory(fdctrl->dma, nchan, tmpbuf, fdctrl->data_pos,
len);
ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len); ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len);
if (ret == 0) { if (ret == 0) {
status2 = FD_SR2_SEH; status2 = FD_SR2_SEH;
@ -2441,7 +2462,11 @@ static void fdctrl_realize_common(FDCtrl *fdctrl, Error **errp)
fdctrl->num_floppies = MAX_FD; fdctrl->num_floppies = MAX_FD;
if (fdctrl->dma_chann != -1) { if (fdctrl->dma_chann != -1) {
DMA_register_channel(fdctrl->dma_chann, &fdctrl_transfer_handler, fdctrl); IsaDmaClass *k;
assert(fdctrl->dma);
k = ISADMA_GET_CLASS(fdctrl->dma);
k->register_channel(fdctrl->dma, fdctrl->dma_chann,
&fdctrl_transfer_handler, fdctrl);
} }
fdctrl_connect_drives(fdctrl, errp); fdctrl_connect_drives(fdctrl, errp);
} }
@ -2464,6 +2489,10 @@ static void isabus_fdc_realize(DeviceState *dev, Error **errp)
isa_init_irq(isadev, &fdctrl->irq, isa->irq); isa_init_irq(isadev, &fdctrl->irq, isa->irq);
fdctrl->dma_chann = isa->dma; fdctrl->dma_chann = isa->dma;
if (fdctrl->dma_chann != -1) {
fdctrl->dma = isa_get_dma(isa_bus_from_device(isadev), isa->dma);
assert(fdctrl->dma);
}
qdev_set_legacy_instance_id(dev, isa->iobase, 2); qdev_set_legacy_instance_id(dev, isa->iobase, 2);
fdctrl_realize_common(fdctrl, &err); fdctrl_realize_common(fdctrl, &err);