target/openrisc: Merge disas_openrisc_insn
Acked-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -1373,14 +1373,6 @@ static bool trans_lf_sfle_s(DisasContext *dc, arg_ab *a, uint32_t insn)
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return true;
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}
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static void disas_openrisc_insn(DisasContext *dc, OpenRISCCPU *cpu)
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{
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uint32_t insn = cpu_ldl_code(&cpu->env, dc->base.pc_next);
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if (!decode(dc, insn)) {
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gen_illegal_exception(dc);
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}
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}
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static void openrisc_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs)
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{
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DisasContext *dc = container_of(dcb, DisasContext, base);
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@ -1435,8 +1427,11 @@ static void openrisc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
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{
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DisasContext *dc = container_of(dcbase, DisasContext, base);
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OpenRISCCPU *cpu = OPENRISC_CPU(cs);
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uint32_t insn = cpu_ldl_code(&cpu->env, dc->base.pc_next);
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disas_openrisc_insn(dc, cpu);
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if (!decode(dc, insn)) {
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gen_illegal_exception(dc);
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}
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dc->base.pc_next += 4;
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/* delay slot */
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