tcg/aarch64: Add support for fence
Cc: Claudio Fontana <claudio.fontana@gmail.com> Signed-off-by: Pranith Kumar <bobby.prani@gmail.com> Message-Id: <20160714202026.9727-4-bobby.prani@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net>
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@ -372,6 +372,11 @@ typedef enum {
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I3510_EOR = 0x4a000000,
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I3510_EON = 0x4a200000,
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I3510_ANDS = 0x6a000000,
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/* System instructions. */
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DMB_ISH = 0xd50338bf,
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DMB_LD = 0x00000100,
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DMB_ST = 0x00000200,
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} AArch64Insn;
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static inline uint32_t tcg_in32(TCGContext *s)
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@ -981,6 +986,18 @@ static inline void tcg_out_addsub2(TCGContext *s, int ext, TCGReg rl,
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tcg_out_mov(s, ext, orig_rl, rl);
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}
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static inline void tcg_out_mb(TCGContext *s, TCGArg a0)
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{
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static const uint32_t sync[] = {
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[0 ... TCG_MO_ALL] = DMB_ISH | DMB_LD | DMB_ST,
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[TCG_MO_ST_ST] = DMB_ISH | DMB_ST,
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[TCG_MO_LD_LD] = DMB_ISH | DMB_LD,
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[TCG_MO_LD_ST] = DMB_ISH | DMB_LD,
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[TCG_MO_LD_ST | TCG_MO_LD_LD] = DMB_ISH | DMB_LD,
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};
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tcg_out32(s, sync[a0 & TCG_MO_ALL]);
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}
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#ifdef CONFIG_SOFTMMU
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/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
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* TCGMemOpIdx oi, uintptr_t ra)
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@ -1649,6 +1666,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
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tcg_out_insn(s, 3508, SMULH, TCG_TYPE_I64, a0, a1, a2);
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break;
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case INDEX_op_mb:
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tcg_out_mb(s, a0);
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break;
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case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
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case INDEX_op_mov_i64:
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case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
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@ -1773,6 +1794,7 @@ static const TCGTargetOpDef aarch64_op_defs[] = {
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{ INDEX_op_muluh_i64, { "r", "r", "r" } },
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{ INDEX_op_mulsh_i64, { "r", "r", "r" } },
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{ INDEX_op_mb, { } },
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{ -1 },
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};
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