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target/mips: Convert MSA 3R instruction format to decodetree (part 3/4)

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Convert BINSL (Vector Bit Insert Left) and BINSR (Vector Bit
Insert Right) opcodes to decodetree.

Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211028210843.2120802-23-f4bug@amsat.org>
This commit is contained in:
Philippe Mathieu-Daudé 2021-10-19 14:22:32 +02:00
parent f18708a53a
commit c79db8c239
2 changed files with 9 additions and 34 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
target/mips/tcg/msa.decode
View File

@ -89,6 +89,9 @@ BNZ 010001 111 .. ..... ................ @bz
SRARI 011110 010 ....... ..... ..... 001010 @bit SRARI 011110 010 ....... ..... ..... 001010 @bit
SRLRI 011110 011 ....... ..... ..... 001010 @bit SRLRI 011110 011 ....... ..... ..... 001010 @bit
BINSL 011110 110.. ..... ..... ..... 001101 @3r
BINSR 011110 111.. ..... ..... ..... 001101 @3r
DOTP_S 011110 000.. ..... ..... ..... 010011 @3r DOTP_S 011110 000.. ..... ..... ..... 010011 @3r
DOTP_U 011110 001.. ..... ..... ..... 010011 @3r DOTP_U 011110 001.. ..... ..... ..... 010011 @3r
DPADD_S 011110 010.. ..... ..... ..... 010011 @3r DPADD_S 011110 010.. ..... ..... ..... 010011 @3r

40
target/mips/tcg/msa_translate.c
View File

@ -91,12 +91,10 @@ enum {
OPC_ASUB_U_df = (0x5 << 23) | OPC_MSA_3R_11, OPC_ASUB_U_df = (0x5 << 23) | OPC_MSA_3R_11,
OPC_DIV_U_df = (0x5 << 23) | OPC_MSA_3R_12, OPC_DIV_U_df = (0x5 << 23) | OPC_MSA_3R_12,
OPC_ILVR_df = (0x5 << 23) | OPC_MSA_3R_14, OPC_ILVR_df = (0x5 << 23) | OPC_MSA_3R_14,
OPC_BINSL_df = (0x6 << 23) | OPC_MSA_3R_0D,
OPC_MAX_A_df = (0x6 << 23) | OPC_MSA_3R_0E, OPC_MAX_A_df = (0x6 << 23) | OPC_MSA_3R_0E,
OPC_AVER_S_df = (0x6 << 23) | OPC_MSA_3R_10, OPC_AVER_S_df = (0x6 << 23) | OPC_MSA_3R_10,
OPC_MOD_S_df = (0x6 << 23) | OPC_MSA_3R_12, OPC_MOD_S_df = (0x6 << 23) | OPC_MSA_3R_12,
OPC_ILVEV_df = (0x6 << 23) | OPC_MSA_3R_14, OPC_ILVEV_df = (0x6 << 23) | OPC_MSA_3R_14,
OPC_BINSR_df = (0x7 << 23) | OPC_MSA_3R_0D,
OPC_MIN_A_df = (0x7 << 23) | OPC_MSA_3R_0E, OPC_MIN_A_df = (0x7 << 23) | OPC_MSA_3R_0E,
OPC_AVER_U_df = (0x7 << 23) | OPC_MSA_3R_10, OPC_AVER_U_df = (0x7 << 23) | OPC_MSA_3R_10,
OPC_MOD_U_df = (0x7 << 23) | OPC_MSA_3R_12, OPC_MOD_U_df = (0x7 << 23) | OPC_MSA_3R_12,
@ -245,6 +243,9 @@ typedef void gen_helper_piiii(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i32);
#define TRANS_DF_ii(NAME, trans_func, gen_func) \ #define TRANS_DF_ii(NAME, trans_func, gen_func) \
TRANS_DF_x(ii, NAME, trans_func, gen_func) TRANS_DF_x(ii, NAME, trans_func, gen_func)
#define TRANS_DF_iii(NAME, trans_func, gen_func) \
TRANS_DF_x(iii, NAME, trans_func, gen_func)
#define TRANS_DF_iii_b(NAME, trans_func, gen_func) \ #define TRANS_DF_iii_b(NAME, trans_func, gen_func) \
static gen_helper_piii * const NAME##_tab[4] = { \ static gen_helper_piii * const NAME##_tab[4] = { \
NULL, gen_func##_h, gen_func##_w, gen_func##_d \ NULL, gen_func##_h, gen_func##_w, gen_func##_d \
@ -505,6 +506,9 @@ TRANS(BMNZ_V, trans_msa_3r, gen_helper_msa_bmnz_v);
TRANS(BMZ_V, trans_msa_3r, gen_helper_msa_bmz_v); TRANS(BMZ_V, trans_msa_3r, gen_helper_msa_bmz_v);
TRANS(BSEL_V, trans_msa_3r, gen_helper_msa_bsel_v); TRANS(BSEL_V, trans_msa_3r, gen_helper_msa_bsel_v);
TRANS_DF_iii(BINSL, trans_msa_3r, gen_helper_msa_binsl);
TRANS_DF_iii(BINSR, trans_msa_3r, gen_helper_msa_binsr);
TRANS_DF_iii_b(DOTP_S, trans_msa_3r, gen_helper_msa_dotp_s); TRANS_DF_iii_b(DOTP_S, trans_msa_3r, gen_helper_msa_dotp_s);
TRANS_DF_iii_b(DOTP_U, trans_msa_3r, gen_helper_msa_dotp_u); TRANS_DF_iii_b(DOTP_U, trans_msa_3r, gen_helper_msa_dotp_u);
TRANS_DF_iii_b(DPADD_S, trans_msa_3r, gen_helper_msa_dpadd_s); TRANS_DF_iii_b(DPADD_S, trans_msa_3r, gen_helper_msa_dpadd_s);
@ -535,38 +539,6 @@ static void gen_msa_3r(DisasContext *ctx)
TCGv_i32 twt = tcg_const_i32(wt); TCGv_i32 twt = tcg_const_i32(wt);
switch (MASK_MSA_3R(ctx->opcode)) { switch (MASK_MSA_3R(ctx->opcode)) {
case OPC_BINSL_df:
switch (df) {
case DF_BYTE:
gen_helper_msa_binsl_b(cpu_env, twd, tws, twt);
break;
case DF_HALF:
gen_helper_msa_binsl_h(cpu_env, twd, tws, twt);
break;
case DF_WORD:
gen_helper_msa_binsl_w(cpu_env, twd, tws, twt);
break;
case DF_DOUBLE:
gen_helper_msa_binsl_d(cpu_env, twd, tws, twt);
break;
}
break;
case OPC_BINSR_df:
switch (df) {
case DF_BYTE:
gen_helper_msa_binsr_b(cpu_env, twd, tws, twt);
break;
case DF_HALF:
gen_helper_msa_binsr_h(cpu_env, twd, tws, twt);
break;
case DF_WORD:
gen_helper_msa_binsr_w(cpu_env, twd, tws, twt);
break;
case DF_DOUBLE:
gen_helper_msa_binsr_d(cpu_env, twd, tws, twt);
break;
}
break;
case OPC_BCLR_df: case OPC_BCLR_df:
switch (df) { switch (df) {
case DF_BYTE: case DF_BYTE: