sh4: Add IRL (4-bit encoded interrupt input) support (Takashi YOSHII).
This patch adds IRL(4bit encoded 15 level interrupt input) support to SH using qemu_irq as a multi level (!=on/off) signal. Signed-off-by: Takashi YOSHII <takasi-y@ops.dti.ne.jp> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5925 c046a42c-6fe2-441c-8c8c-71466251a162
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a4a771c055
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3
hw/sh.h
3
hw/sh.h
@ -42,6 +42,9 @@ void sh_serial_init (target_phys_addr_t base, int feat,
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qemu_irq tei_source,
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qemu_irq tei_source,
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qemu_irq bri_source);
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qemu_irq bri_source);
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/* sh7750.c */
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qemu_irq sh7750_irl(struct SH7750State *s);
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/* tc58128.c */
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/* tc58128.c */
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int tc58128_init(struct SH7750State *s, const char *zone1, const char *zone2);
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int tc58128_init(struct SH7750State *s, const char *zone1, const char *zone2);
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40
hw/sh7750.c
40
hw/sh7750.c
@ -412,7 +412,9 @@ enum {
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UNUSED = 0,
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UNUSED = 0,
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/* interrupt sources */
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/* interrupt sources */
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IRL0, IRL1, IRL2, IRL3, /* only IRLM mode supported */
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IRL_0, IRL_1, IRL_2, IRL_3, IRL_4, IRL_5, IRL_6, IRL_7,
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IRL_8, IRL_9, IRL_A, IRL_B, IRL_C, IRL_D, IRL_E,
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IRL0, IRL1, IRL2, IRL3,
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HUDI, GPIOI,
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HUDI, GPIOI,
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DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, DMAC_DMTE3,
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DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, DMAC_DMTE3,
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DMAC_DMTE4, DMAC_DMTE5, DMAC_DMTE6, DMAC_DMTE7,
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DMAC_DMTE4, DMAC_DMTE5, DMAC_DMTE6, DMAC_DMTE7,
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@ -428,6 +430,8 @@ enum {
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/* interrupt groups */
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/* interrupt groups */
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DMAC, PCIC1, TMU2, RTC, SCI1, SCIF, REF,
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DMAC, PCIC1, TMU2, RTC, SCI1, SCIF, REF,
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/* irl bundle */
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IRL,
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NR_SOURCES,
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NR_SOURCES,
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};
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};
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@ -529,6 +533,29 @@ static struct intc_group groups_pci[] = {
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PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3),
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PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3),
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};
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};
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static struct intc_vect vectors_irl[] = {
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INTC_VECT(IRL_0, 0x200),
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INTC_VECT(IRL_1, 0x220),
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INTC_VECT(IRL_2, 0x240),
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INTC_VECT(IRL_3, 0x260),
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INTC_VECT(IRL_4, 0x280),
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INTC_VECT(IRL_5, 0x2a0),
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INTC_VECT(IRL_6, 0x2c0),
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INTC_VECT(IRL_7, 0x2e0),
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INTC_VECT(IRL_8, 0x300),
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INTC_VECT(IRL_9, 0x320),
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INTC_VECT(IRL_A, 0x340),
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INTC_VECT(IRL_B, 0x360),
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INTC_VECT(IRL_C, 0x380),
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INTC_VECT(IRL_D, 0x3a0),
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INTC_VECT(IRL_E, 0x3c0),
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};
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static struct intc_group groups_irl[] = {
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INTC_GROUP(IRL, IRL_0, IRL_1, IRL_2, IRL_3, IRL_4, IRL_5, IRL_6,
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IRL_7, IRL_8, IRL_9, IRL_A, IRL_B, IRL_C, IRL_D, IRL_E),
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};
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/**********************************************************************
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/**********************************************************************
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Memory mapped cache and TLB
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Memory mapped cache and TLB
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**********************************************************************/
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**********************************************************************/
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@ -718,5 +745,16 @@ SH7750State *sh7750_init(CPUSH4State * cpu)
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NULL, 0);
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NULL, 0);
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}
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}
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sh_intc_register_sources(&s->intc,
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_INTC_ARRAY(vectors_irl),
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_INTC_ARRAY(groups_irl));
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return s;
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return s;
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}
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}
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qemu_irq sh7750_irl(SH7750State *s)
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{
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sh_intc_toggle_source(sh_intc_source(&s->intc, IRL), 1, 0); /* enable */
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return qemu_allocate_irqs(sh_intc_set_irl, sh_intc_source(&s->intc, IRL),
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1)[0];
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}
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15
hw/sh_intc.c
15
hw/sh_intc.c
@ -465,3 +465,18 @@ int sh_intc_init(struct intc_desc *desc,
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return 0;
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return 0;
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}
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}
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/* Assert level <n> IRL interrupt.
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0:deassert. 1:lowest priority,... 15:highest priority. */
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void sh_intc_set_irl(void *opaque, int n, int level)
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{
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struct intc_source *s = opaque;
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int i, irl = level ^ 15;
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for (i = 0; (s = sh_intc_source(s->parent, s->next_enum_id)); i++) {
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if (i == irl)
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sh_intc_toggle_source(s, s->enable_count?0:1, s->asserted?0:1);
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else
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if (s->asserted)
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sh_intc_toggle_source(s, 0, -1);
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}
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}
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@ -75,4 +75,6 @@ int sh_intc_init(struct intc_desc *desc,
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struct intc_prio_reg *prio_regs,
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struct intc_prio_reg *prio_regs,
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int nr_prio_regs);
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int nr_prio_regs);
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void sh_intc_set_irl(void *opaque, int n, int level);
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#endif /* __SH_INTC_H__ */
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#endif /* __SH_INTC_H__ */
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