target/ppc: Style fixes for cpu.[ch]
Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org>
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David Gibson
parent
b93745bba4
commit
c647e3fe3d
145
target/ppc/cpu.h
145
target/ppc/cpu.h
@ -23,23 +23,28 @@
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#include "qemu-common.h"
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#include "qemu/int128.h"
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//#define PPC_EMULATE_32BITS_HYPV
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/* #define PPC_EMULATE_32BITS_HYPV */
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#if defined (TARGET_PPC64)
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#if defined(TARGET_PPC64)
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/* PowerPC 64 definitions */
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#define TARGET_LONG_BITS 64
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#define TARGET_PAGE_BITS 12
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#define TCG_GUEST_DEFAULT_MO 0
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/* Note that the official physical address space bits is 62-M where M
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is implementation dependent. I've not looked up M for the set of
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cpus we emulate at the system level. */
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/*
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* Note that the official physical address space bits is 62-M where M
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* is implementation dependent. I've not looked up M for the set of
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* cpus we emulate at the system level.
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*/
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#define TARGET_PHYS_ADDR_SPACE_BITS 62
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/* Note that the PPC environment architecture talks about 80 bit virtual
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addresses, with segmentation. Obviously that's not all visible to a
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single process, which is all we're concerned with here. */
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/*
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* Note that the PPC environment architecture talks about 80 bit
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* virtual addresses, with segmentation. Obviously that's not all
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* visible to a single process, which is all we're concerned with
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* here.
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*/
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#ifdef TARGET_ABI32
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# define TARGET_VIRT_ADDR_SPACE_BITS 32
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#else
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@ -49,7 +54,7 @@
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#define TARGET_PAGE_BITS_64K 16
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#define TARGET_PAGE_BITS_16M 24
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#else /* defined (TARGET_PPC64) */
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#else /* defined(TARGET_PPC64) */
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/* PowerPC 32 definitions */
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#define TARGET_LONG_BITS 32
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#define TARGET_PAGE_BITS 12
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@ -57,14 +62,14 @@
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#define TARGET_PHYS_ADDR_SPACE_BITS 36
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#define TARGET_VIRT_ADDR_SPACE_BITS 32
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#endif /* defined (TARGET_PPC64) */
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#endif /* defined(TARGET_PPC64) */
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#define CPUArchState struct CPUPPCState
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#include "exec/cpu-defs.h"
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#include "cpu-qom.h"
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#if defined (TARGET_PPC64)
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#if defined(TARGET_PPC64)
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#define PPC_ELF_MACHINE EM_PPC64
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#else
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#define PPC_ELF_MACHINE EM_PPC
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@ -237,9 +242,11 @@ struct ppc_spr_t {
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const char *name;
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target_ulong default_value;
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#ifdef CONFIG_KVM
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/* We (ab)use the fact that all the SPRs will have ids for the
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/*
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* We (ab)use the fact that all the SPRs will have ids for the
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* ONE_REG interface will have KVM_REG_PPC to use 0 as meaning,
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* don't sync this */
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* don't sync this
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*/
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uint64_t one_reg_id;
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#endif
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};
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@ -962,9 +969,10 @@ struct ppc_radix_page_info {
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/*****************************************************************************/
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/* The whole PowerPC CPU context */
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/* PowerPC needs eight modes for different hypervisor/supervisor/guest +
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* real/paged mode combinations. The other two modes are for external PID
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* load/store.
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/*
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* PowerPC needs eight modes for different hypervisor/supervisor/guest
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* + real/paged mode combinations. The other two modes are for
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* external PID load/store.
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*/
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#define NB_MMU_MODES 10
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#define MMU_MODE8_SUFFIX _epl
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@ -976,8 +984,9 @@ struct ppc_radix_page_info {
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#define PPC_CPU_INDIRECT_OPCODES_LEN 0x20
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struct CPUPPCState {
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/* First are the most commonly used resources
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* during translated code execution
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/*
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* First are the most commonly used resources during translated
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* code execution
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*/
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/* general purpose registers */
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target_ulong gpr[32];
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@ -1023,8 +1032,8 @@ struct CPUPPCState {
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/* High part of 128-bit helper return. */
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uint64_t retxh;
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int access_type; /* when a memory exception occurs, the access
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type is stored here */
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/* when a memory exception occurs, the access type is stored here */
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int access_type;
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CPU_COMMON
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@ -1072,8 +1081,10 @@ struct CPUPPCState {
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/* SPE registers */
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uint64_t spe_acc;
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uint32_t spe_fscr;
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/* SPE and Altivec can share a status since they will never be used
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* simultaneously */
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/*
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* SPE and Altivec can share a status since they will never be
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* used simultaneously
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*/
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float_status vec_status;
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/* Internal devices resources */
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@ -1103,7 +1114,8 @@ struct CPUPPCState {
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int error_code;
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uint32_t pending_interrupts;
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#if !defined(CONFIG_USER_ONLY)
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/* This is the IRQ controller, which is implementation dependent
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/*
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* This is the IRQ controller, which is implementation dependent
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* and only relevant when emulating a complete machine.
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*/
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uint32_t irq_input_state;
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@ -1117,7 +1129,8 @@ struct CPUPPCState {
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hwaddr mpic_iack;
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/* true when the external proxy facility mode is enabled */
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bool mpic_proxy;
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/* set when the processor has an HV mode, thus HV priv
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/*
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* set when the processor has an HV mode, thus HV priv
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* instructions and SPRs are diallowed if MSR:HV is 0
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*/
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bool has_hv_mode;
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@ -1149,8 +1162,10 @@ struct CPUPPCState {
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/* booke timers */
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/* Specifies bit locations of the Time Base used to signal a fixed timer
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* exception on a transition from 0 to 1. (watchdog or fixed-interval timer)
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/*
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* Specifies bit locations of the Time Base used to signal a fixed
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* timer exception on a transition from 0 to 1. (watchdog or
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* fixed-interval timer)
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*
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* 0 selects the least significant bit.
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* 63 selects the most significant bit.
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@ -1290,53 +1305,54 @@ extern const struct VMStateDescription vmstate_ppc_cpu;
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/*****************************************************************************/
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void ppc_translate_init(void);
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/* you can call this signal handler from your SIGBUS and SIGSEGV
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signal handlers to inform the virtual CPU of exceptions. non zero
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is returned if the signal was handled by the virtual CPU. */
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int cpu_ppc_signal_handler (int host_signum, void *pinfo,
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void *puc);
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/*
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* you can call this signal handler from your SIGBUS and SIGSEGV
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* signal handlers to inform the virtual CPU of exceptions. non zero
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* is returned if the signal was handled by the virtual CPU.
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*/
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int cpu_ppc_signal_handler(int host_signum, void *pinfo, void *puc);
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#if defined(CONFIG_USER_ONLY)
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int ppc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw,
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int mmu_idx);
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#endif
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#if !defined(CONFIG_USER_ONLY)
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void ppc_store_sdr1 (CPUPPCState *env, target_ulong value);
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void ppc_store_sdr1(CPUPPCState *env, target_ulong value);
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void ppc_store_ptcr(CPUPPCState *env, target_ulong value);
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#endif /* !defined(CONFIG_USER_ONLY) */
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void ppc_store_msr (CPUPPCState *env, target_ulong value);
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void ppc_store_msr(CPUPPCState *env, target_ulong value);
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void ppc_cpu_list(void);
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/* Time-base and decrementer management */
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#ifndef NO_CPU_IO_DEFS
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uint64_t cpu_ppc_load_tbl (CPUPPCState *env);
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uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
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void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
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void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
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uint64_t cpu_ppc_load_atbl (CPUPPCState *env);
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uint32_t cpu_ppc_load_atbu (CPUPPCState *env);
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void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);
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void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);
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uint64_t cpu_ppc_load_tbl(CPUPPCState *env);
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uint32_t cpu_ppc_load_tbu(CPUPPCState *env);
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void cpu_ppc_store_tbu(CPUPPCState *env, uint32_t value);
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void cpu_ppc_store_tbl(CPUPPCState *env, uint32_t value);
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uint64_t cpu_ppc_load_atbl(CPUPPCState *env);
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uint32_t cpu_ppc_load_atbu(CPUPPCState *env);
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void cpu_ppc_store_atbl(CPUPPCState *env, uint32_t value);
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void cpu_ppc_store_atbu(CPUPPCState *env, uint32_t value);
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bool ppc_decr_clear_on_delivery(CPUPPCState *env);
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target_ulong cpu_ppc_load_decr(CPUPPCState *env);
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void cpu_ppc_store_decr(CPUPPCState *env, target_ulong value);
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target_ulong cpu_ppc_load_hdecr(CPUPPCState *env);
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void cpu_ppc_store_hdecr(CPUPPCState *env, target_ulong value);
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uint64_t cpu_ppc_load_purr (CPUPPCState *env);
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uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
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uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
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uint64_t cpu_ppc_load_purr(CPUPPCState *env);
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uint32_t cpu_ppc601_load_rtcl(CPUPPCState *env);
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uint32_t cpu_ppc601_load_rtcu(CPUPPCState *env);
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#if !defined(CONFIG_USER_ONLY)
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void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
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void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
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target_ulong load_40x_pit (CPUPPCState *env);
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void store_40x_pit (CPUPPCState *env, target_ulong val);
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void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
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void store_40x_sler (CPUPPCState *env, uint32_t val);
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void store_booke_tcr (CPUPPCState *env, target_ulong val);
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void store_booke_tsr (CPUPPCState *env, target_ulong val);
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void ppc_tlb_invalidate_all (CPUPPCState *env);
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void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
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void cpu_ppc601_store_rtcl(CPUPPCState *env, uint32_t value);
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void cpu_ppc601_store_rtcu(CPUPPCState *env, uint32_t value);
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target_ulong load_40x_pit(CPUPPCState *env);
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void store_40x_pit(CPUPPCState *env, target_ulong val);
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void store_40x_dbcr0(CPUPPCState *env, uint32_t val);
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void store_40x_sler(CPUPPCState *env, uint32_t val);
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void store_booke_tcr(CPUPPCState *env, target_ulong val);
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void store_booke_tsr(CPUPPCState *env, target_ulong val);
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void ppc_tlb_invalidate_all(CPUPPCState *env);
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void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr);
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void cpu_ppc_set_vhyp(PowerPCCPU *cpu, PPCVirtualHypervisor *vhyp);
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#endif
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#endif
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@ -1349,7 +1365,8 @@ static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
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gprv = env->gpr[gprn];
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if (env->flags & POWERPC_FLAG_SPE) {
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/* If the CPU implements the SPE extension, we have to get the
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/*
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* If the CPU implements the SPE extension, we have to get the
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* high bits of the GPR from the gprh storage area
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*/
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gprv &= 0xFFFFFFFFULL;
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@ -1360,8 +1377,8 @@ static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
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}
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/* Device control registers */
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int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp);
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int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
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int ppc_dcr_read(ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp);
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int ppc_dcr_write(ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
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#define POWERPC_CPU_TYPE_SUFFIX "-" TYPE_POWERPC_CPU
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#define POWERPC_CPU_TYPE_NAME(model) model POWERPC_CPU_TYPE_SUFFIX
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@ -1372,7 +1389,7 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
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/* MMU modes definitions */
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#define MMU_USER_IDX 0
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static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
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static inline int cpu_mmu_index(CPUPPCState *env, bool ifetch)
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{
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return ifetch ? env->immu_idx : env->dmmu_idx;
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}
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@ -2226,7 +2243,8 @@ enum {
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};
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/*****************************************************************************/
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/* Memory access type :
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/*
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* Memory access type :
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* may be needed for precise access rights control and precise exceptions.
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*/
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enum {
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@ -2242,7 +2260,8 @@ enum {
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ACCESS_CACHE = 0x60, /* Cache manipulation */
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};
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/* Hardware interruption sources:
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/*
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* Hardware interrupt sources:
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* all those exception can be raised simulteaneously
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*/
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/* Input pins definitions */
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@ -2325,9 +2344,11 @@ enum {
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enum {
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/* POWER7 input pins */
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POWER7_INPUT_INT = 0,
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/* POWER7 probably has other inputs, but we don't care about them
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/*
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* POWER7 probably has other inputs, but we don't care about them
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* for any existing machine. We can wire these up when we need
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* them */
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* them
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*/
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POWER7_INPUT_NB,
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};
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