hw/i386/pc_piix: Move i440fx' realize near its qdev_new()
I440FX realization is currently mixed with PIIX3 creation. Furthermore, it is common practice to only set properties between a device's qdev_new() and qdev_realize(). Clean up to resolve both issues. Since I440FX spawns a PCI bus let's also move the pci_bus initialization there. Note that when running `qemu-system-x86_64 -M pc -S` before and after this patch, `info mtree` in the QEMU console doesn't show any differences except that the ordering is different. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230630073720.21297-18-shentey@gmail.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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@ -114,7 +114,7 @@ static void pc_init1(MachineState *machine,
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X86MachineState *x86ms = X86_MACHINE(machine);
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MemoryRegion *system_memory = get_system_memory();
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MemoryRegion *system_io = get_system_io();
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PCIBus *pci_bus;
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PCIBus *pci_bus = NULL;
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ISABus *isa_bus;
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int piix3_devfn = -1;
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qemu_irq smi_irq;
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@ -126,7 +126,6 @@ static void pc_init1(MachineState *machine,
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MemoryRegion *rom_memory = system_memory;
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ram_addr_t lowmem;
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uint64_t hole64_size = 0;
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Object *phb = NULL;
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/*
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* Calculate ram split, for memory below and above 4G. It's a bit
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@ -198,11 +197,36 @@ static void pc_init1(MachineState *machine,
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}
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if (pcmc->pci_enabled) {
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Object *phb;
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pci_memory = g_new(MemoryRegion, 1);
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memory_region_init(pci_memory, NULL, "pci", UINT64_MAX);
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rom_memory = pci_memory;
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phb = OBJECT(qdev_new(host_type));
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object_property_add_child(OBJECT(machine), "i440fx", phb);
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object_property_set_link(phb, PCI_HOST_PROP_RAM_MEM,
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OBJECT(ram_memory), &error_fatal);
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object_property_set_link(phb, PCI_HOST_PROP_PCI_MEM,
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OBJECT(pci_memory), &error_fatal);
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object_property_set_link(phb, PCI_HOST_PROP_SYSTEM_MEM,
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OBJECT(system_memory), &error_fatal);
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object_property_set_link(phb, PCI_HOST_PROP_IO_MEM,
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OBJECT(system_io), &error_fatal);
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object_property_set_uint(phb, PCI_HOST_BELOW_4G_MEM_SIZE,
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x86ms->below_4g_mem_size, &error_fatal);
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object_property_set_uint(phb, PCI_HOST_ABOVE_4G_MEM_SIZE,
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x86ms->above_4g_mem_size, &error_fatal);
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object_property_set_str(phb, I440FX_HOST_PROP_PCI_TYPE, pci_type,
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&error_fatal);
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sysbus_realize_and_unref(SYS_BUS_DEVICE(phb), &error_fatal);
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pci_bus = PCI_BUS(qdev_get_child_bus(DEVICE(phb), "pci.0"));
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pci_bus_map_irqs(pci_bus,
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xen_enabled() ? xen_pci_slot_get_pirq
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: pc_pci_slot_get_pirq);
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pcms->bus = pci_bus;
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hole64_size = object_property_get_uint(phb,
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PCI_HOST_PROP_PCI_HOLE64_SIZE,
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&error_abort);
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@ -239,28 +263,6 @@ static void pc_init1(MachineState *machine,
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PIIX3State *piix3;
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PCIDevice *pci_dev;
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object_property_set_link(phb, PCI_HOST_PROP_RAM_MEM,
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OBJECT(ram_memory), &error_fatal);
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object_property_set_link(phb, PCI_HOST_PROP_PCI_MEM,
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OBJECT(pci_memory), &error_fatal);
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object_property_set_link(phb, PCI_HOST_PROP_SYSTEM_MEM,
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OBJECT(system_memory), &error_fatal);
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object_property_set_link(phb, PCI_HOST_PROP_IO_MEM,
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OBJECT(system_io), &error_fatal);
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object_property_set_uint(phb, PCI_HOST_BELOW_4G_MEM_SIZE,
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x86ms->below_4g_mem_size, &error_fatal);
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object_property_set_uint(phb, PCI_HOST_ABOVE_4G_MEM_SIZE,
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x86ms->above_4g_mem_size, &error_fatal);
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object_property_set_str(phb, I440FX_HOST_PROP_PCI_TYPE,
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pci_type, &error_fatal);
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sysbus_realize_and_unref(SYS_BUS_DEVICE(phb), &error_fatal);
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pci_bus = PCI_BUS(qdev_get_child_bus(DEVICE(phb), "pci.0"));
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pci_bus_map_irqs(pci_bus,
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xen_enabled() ? xen_pci_slot_get_pirq
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: pc_pci_slot_get_pirq);
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pcms->bus = pci_bus;
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pci_dev = pci_create_simple_multifunction(pci_bus, -1, true,
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TYPE_PIIX3_DEVICE);
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@ -285,7 +287,6 @@ static void pc_init1(MachineState *machine,
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rtc_state = ISA_DEVICE(object_resolve_path_component(OBJECT(pci_dev),
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"rtc"));
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} else {
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pci_bus = NULL;
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isa_bus = isa_bus_new(NULL, system_memory, system_io,
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&error_abort);
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