target/ppc: Fix FPSCR.FI changing in float_overflow_excp()
This patch fixes another not-so-clear situation in Power ISA regarding the inexact bits in FPSCR. The ISA states that: """ When Overflow Exception is disabled (OE=0) and an Overflow Exception occurs, the following actions are taken: ... 2. Inexact Exception is set XX <- 1 ... FI is set to 1 ... """ However, when tested on a Power 9 hardware, some instructions that trigger an OX don't set the FI bit: xvcvdpsp(0x4050533fcdb7b95ff8d561c40bf90996) = FI: CLEARED -> CLEARED xvnmsubmsp(0xf3c0c1fc8f3230, 0xbeaab9c5) = FI: CLEARED -> CLEARED (just a few examples. Other instructions are also affected) The root cause for this seems to be that only instructions that list the bit FI in the "Special Registers Altered" should modify it. QEMU is, today, not working like the hardware: xvcvdpsp(0x4050533fcdb7b95ff8d561c40bf90996) = FI: CLEARED -> SET xvnmsubmsp(0xf3c0c1fc8f3230, 0xbeaab9c5) = FI: CLEARED -> SET (all tests assume FI is cleared beforehand) Fix this by making float_overflow_excp() return float_flag_inexact if it should update the inexact flags. Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Rashmica Gupta <rashmica.g@gmail.com> Message-Id: <20220517161522.36132-3-victor.colombo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
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@ -329,24 +329,25 @@ static inline void float_zero_divide_excp(CPUPPCState *env, uintptr_t raddr)
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}
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}
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static inline void float_overflow_excp(CPUPPCState *env)
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static inline int float_overflow_excp(CPUPPCState *env)
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{
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CPUState *cs = env_cpu(env);
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env->fpscr |= FP_OX;
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/* Update the floating-point exception summary */
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env->fpscr |= FP_FX;
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if (env->fpscr & FP_OE) {
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bool overflow_enabled = !!(env->fpscr & FP_OE);
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if (overflow_enabled) {
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/* XXX: should adjust the result */
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/* Update the floating-point enabled exception summary */
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env->fpscr |= FP_FEX;
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/* We must update the target FPR before raising the exception */
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cs->exception_index = POWERPC_EXCP_PROGRAM;
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env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
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} else {
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env->fpscr |= FP_XX;
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env->fpscr |= FP_FI;
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}
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return overflow_enabled ? 0 : float_flag_inexact;
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}
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static inline void float_underflow_excp(CPUPPCState *env)
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@ -468,7 +469,7 @@ static void do_float_check_status(CPUPPCState *env, bool change_fi,
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int status = get_float_exception_flags(&env->fp_status);
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if (status & float_flag_overflow) {
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float_overflow_excp(env);
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status |= float_overflow_excp(env);
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} else if (status & float_flag_underflow) {
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float_underflow_excp(env);
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}
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