PowerPC 4xx software driven TLB fixes + debug traces.
Add code provision for more MMU models support. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2683 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
j_mayer
parent
0a032cbec6
commit
c55e9aefa7
@ -581,12 +581,12 @@ struct ppc6xx_tlb_t {
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typedef struct ppcemb_tlb_t ppcemb_tlb_t;
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struct ppcemb_tlb_t {
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target_ulong RPN;
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target_phys_addr_t RPN;
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target_ulong EPN;
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target_ulong PID;
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int size;
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int prot;
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int attr; /* Storage attributes */
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target_ulong size;
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uint32_t prot;
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uint32_t attr; /* Storage attributes */
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};
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union ppc_tlb_t {
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@ -765,10 +765,6 @@ struct CPUPPCState {
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int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */
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int nb_pids; /* Number of available PID registers */
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ppc_tlb_t *tlb; /* TLB is optional. Allocate them only if needed */
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/* Callbacks for specific checks on some implementations */
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int (*tlb_check_more)(CPUPPCState *env, ppc_tlb_t *tlb, int *prot,
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target_ulong vaddr, int rw, int acc_type,
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int is_user);
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/* 403 dedicated access protection registers */
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target_ulong pb[4];
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@ -657,7 +657,8 @@ int mmu4xx_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
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target_ulong mask;
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int i, ret, zsel, zpr;
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ret = -6;
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ret = -1;
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raddr = -1;
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for (i = 0; i < env->nb_tlb; i++) {
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tlb = &env->tlb[i].tlbe;
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/* Check valid flag */
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@ -691,8 +692,8 @@ int mmu4xx_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
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switch (zpr) {
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case 0x0:
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if (msr_pr) {
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ret = -3;
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ctx->prot = 0;
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ret = -3;
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break;
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}
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/* No break here */
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@ -702,25 +703,26 @@ int mmu4xx_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
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if (!(tlb->prot & PAGE_EXEC)) {
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ret = -3;
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} else {
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if (tlb->prot & PAGE_WRITE)
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if (tlb->prot & PAGE_WRITE) {
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ctx->prot = PAGE_READ | PAGE_WRITE;
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else
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} else {
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ctx->prot = PAGE_READ;
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}
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ret = 0;
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}
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break;
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case 0x3:
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/* All accesses granted */
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ret = 0;
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ctx->prot = PAGE_READ | PAGE_WRITE;
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ret = 0;
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break;
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}
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} else {
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switch (zpr) {
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case 0x0:
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if (msr_pr) {
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ret = -2;
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ctx->prot = 0;
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ret = -2;
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break;
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}
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/* No break here */
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@ -728,20 +730,21 @@ int mmu4xx_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
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case 0x2:
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/* Check from TLB entry */
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/* Check write protection bit */
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if (rw && !(tlb->prot & PAGE_WRITE)) {
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ret = -2;
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if (tlb->prot & PAGE_WRITE) {
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ctx->prot = PAGE_READ | PAGE_WRITE;
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ret = 0;
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} else {
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ret = 2;
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if (tlb->prot & PAGE_WRITE)
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ctx->prot = PAGE_READ | PAGE_WRITE;
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ctx->prot = PAGE_READ;
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if (rw)
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ret = -2;
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else
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ctx->prot = PAGE_READ;
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ret = 0;
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}
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break;
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case 0x3:
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/* All accesses granted */
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ret = 2;
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ctx->prot = PAGE_READ | PAGE_WRITE;
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ret = 0;
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break;
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}
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}
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@ -749,11 +752,17 @@ int mmu4xx_get_physical_address (CPUState *env, mmu_ctx_t *ctx,
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ctx->raddr = raddr;
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if (loglevel) {
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fprintf(logfile, "%s: access granted " ADDRX " => " REGX
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" %d\n", __func__, address, ctx->raddr, ctx->prot);
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" %d %d\n", __func__, address, ctx->raddr, ctx->prot,
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ret);
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}
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return i;
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return 0;
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}
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}
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if (loglevel) {
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fprintf(logfile, "%s: access refused " ADDRX " => " REGX
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" %d %d\n", __func__, address, raddr, ctx->prot,
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ret);
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}
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return ret;
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}
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@ -808,32 +817,49 @@ int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong eaddr,
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/* No address translation */
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ret = check_physical(env, ctx, eaddr, rw);
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} else {
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ret = -1;
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switch (PPC_MMU(env)) {
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case PPC_FLAGS_MMU_32B:
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case PPC_FLAGS_MMU_SOFT_6xx:
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/* Try to find a BAT */
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ret = -1;
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if (check_BATs)
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ret = get_bat(env, ctx, eaddr, rw, access_type);
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/* No break here */
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#if defined(TARGET_PPC64)
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case PPC_FLAGS_MMU_64B:
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case PPC_FLAGS_MMU_64BRIDGE:
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#endif
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if (ret < 0) {
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/* We didn't match any BAT entry */
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/* We didn't match any BAT entry or don't have BATs */
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ret = get_segment(env, ctx, eaddr, rw, access_type);
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}
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break;
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case PPC_FLAGS_MMU_SOFT_4xx:
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case PPC_FLAGS_MMU_403:
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ret = mmu4xx_get_physical_address(env, ctx, eaddr,
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rw, access_type);
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break;
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default:
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case PPC_FLAGS_MMU_601:
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/* XXX: TODO */
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cpu_abort(env, "MMU model not implemented\n");
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cpu_abort(env, "601 MMU model not implemented\n");
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return -1;
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case PPC_FLAGS_MMU_BOOKE:
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/* XXX: TODO */
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cpu_abort(env, "BookeE MMU model not implemented\n");
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return -1;
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case PPC_FLAGS_MMU_BOOKE_FSL:
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/* XXX: TODO */
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cpu_abort(env, "BookE FSL MMU model not implemented\n");
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return -1;
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default:
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cpu_abort(env, "Unknown or invalid MMU model\n");
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return -1;
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}
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}
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#if 0
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if (loglevel > 0) {
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fprintf(logfile, "%s address " ADDRX " => " ADDRX "\n",
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__func__, eaddr, ctx->raddr);
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fprintf(logfile, "%s address " ADDRX " => %d " ADDRX "\n",
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__func__, eaddr, ret, ctx->raddr);
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}
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#endif
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@ -885,19 +911,48 @@ int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
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switch (ret) {
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case -1:
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/* No matches in page tables or TLB */
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if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_6xx)) {
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switch (PPC_MMU(env)) {
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case PPC_FLAGS_MMU_SOFT_6xx:
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exception = EXCP_I_TLBMISS;
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env->spr[SPR_IMISS] = address;
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env->spr[SPR_ICMP] = 0x80000000 | ctx.ptem;
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error_code = 1 << 18;
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goto tlb_miss;
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} else if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_4xx)) {
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case PPC_FLAGS_MMU_SOFT_4xx:
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case PPC_FLAGS_MMU_403:
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exception = EXCP_40x_ITLBMISS;
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error_code = 0;
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env->spr[SPR_40x_DEAR] = address;
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env->spr[SPR_40x_ESR] = 0x00000000;
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} else {
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break;
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case PPC_FLAGS_MMU_32B:
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error_code = 0x40000000;
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break;
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#if defined(TARGET_PPC64)
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case PPC_FLAGS_MMU_64B:
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/* XXX: TODO */
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cpu_abort(env, "MMU model not implemented\n");
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return -1;
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case PPC_FLAGS_MMU_64BRIDGE:
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/* XXX: TODO */
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cpu_abort(env, "MMU model not implemented\n");
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return -1;
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#endif
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case PPC_FLAGS_MMU_601:
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/* XXX: TODO */
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cpu_abort(env, "MMU model not implemented\n");
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return -1;
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case PPC_FLAGS_MMU_BOOKE:
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/* XXX: TODO */
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cpu_abort(env, "MMU model not implemented\n");
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return -1;
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case PPC_FLAGS_MMU_BOOKE_FSL:
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/* XXX: TODO */
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cpu_abort(env, "MMU model not implemented\n");
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return -1;
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default:
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cpu_abort(env, "Unknown or invalid MMU model\n");
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return -1;
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}
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break;
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case -2:
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@ -924,7 +979,8 @@ int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
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switch (ret) {
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case -1:
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/* No matches in page tables or TLB */
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if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_6xx)) {
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switch (PPC_MMU(env)) {
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case PPC_FLAGS_MMU_SOFT_6xx:
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if (rw == 1) {
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exception = EXCP_DS_TLBMISS;
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error_code = 1 << 16;
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@ -940,7 +996,8 @@ int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
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env->spr[SPR_HASH2] = ctx.pg_addr[1];
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/* Do not alter DAR nor DSISR */
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goto out;
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} else if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_4xx)) {
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case PPC_FLAGS_MMU_SOFT_4xx:
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case PPC_FLAGS_MMU_403:
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exception = EXCP_40x_DTLBMISS;
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error_code = 0;
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env->spr[SPR_40x_DEAR] = address;
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@ -948,8 +1005,35 @@ int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
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env->spr[SPR_40x_ESR] = 0x00800000;
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else
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env->spr[SPR_40x_ESR] = 0x00000000;
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} else {
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break;
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case PPC_FLAGS_MMU_32B:
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error_code = 0x40000000;
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break;
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#if defined(TARGET_PPC64)
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case PPC_FLAGS_MMU_64B:
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/* XXX: TODO */
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cpu_abort(env, "MMU model not implemented\n");
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return -1;
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case PPC_FLAGS_MMU_64BRIDGE:
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/* XXX: TODO */
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cpu_abort(env, "MMU model not implemented\n");
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return -1;
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#endif
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case PPC_FLAGS_MMU_601:
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/* XXX: TODO */
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cpu_abort(env, "MMU model not implemented\n");
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return -1;
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case PPC_FLAGS_MMU_BOOKE:
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/* XXX: TODO */
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cpu_abort(env, "MMU model not implemented\n");
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return -1;
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case PPC_FLAGS_MMU_BOOKE_FSL:
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/* XXX: TODO */
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cpu_abort(env, "MMU model not implemented\n");
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return -1;
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default:
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cpu_abort(env, "Unknown or invalid MMU model\n");
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return -1;
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}
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break;
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case -2:
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@ -2537,39 +2537,72 @@ void do_4xx_tlbsx_ (void)
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env->crf[0] = tmp;
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}
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void do_4xx_tlbwe_lo (void)
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void do_4xx_tlbwe_hi (void)
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{
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ppcemb_tlb_t *tlb;
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target_ulong page, end;
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#if defined (DEBUG_SOFTWARE_TLB)
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if (loglevel) {
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fprintf(logfile, "%s T0 " REGX " T1 " REGX "\n", __func__, T0, T1);
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}
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#endif
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T0 &= 0x3F;
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tlb = &env->tlb[T0].tlbe;
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/* Invalidate previous TLB (if it's valid) */
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if (tlb->prot & PAGE_VALID) {
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end = tlb->EPN + tlb->size;
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#if defined (DEBUG_SOFTWARE_TLB)
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if (loglevel) {
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fprintf(logfile, "%s: invalidate old TLB %d start " ADDRX
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" end " ADDRX "\n", __func__, (int)T0, tlb->EPN, end);
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}
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#endif
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for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
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tlb_flush_page(env, page);
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}
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tlb->size = booke_tlb_to_page_size((T1 >> 7) & 0x7);
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tlb->EPN = (T1 & 0xFFFFFC00) & ~(tlb->size - 1);
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if (T1 & 0x400)
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if (T1 & 0x40)
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tlb->prot |= PAGE_VALID;
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else
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tlb->prot &= ~PAGE_VALID;
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tlb->PID = env->spr[SPR_BOOKE_PID]; /* PID */
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tlb->PID = env->spr[SPR_40x_PID]; /* PID */
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tlb->attr = T1 & 0xFF;
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#if defined (DEBUG_SOFTWARE_TLB)
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if (loglevel) {
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fprintf(logfile, "%s: set up TLB %d RPN " ADDRX " EPN " ADDRX
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" size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
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(int)T0, tlb->RPN, tlb->EPN, tlb->size,
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tlb->prot & PAGE_READ ? 'r' : '-',
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tlb->prot & PAGE_WRITE ? 'w' : '-',
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tlb->prot & PAGE_EXEC ? 'x' : '-',
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tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
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}
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#endif
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/* Invalidate new TLB (if valid) */
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if (tlb->prot & PAGE_VALID) {
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end = tlb->EPN + tlb->size;
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#if defined (DEBUG_SOFTWARE_TLB)
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if (loglevel) {
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fprintf(logfile, "%s: invalidate TLB %d start " ADDRX
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" end " ADDRX "\n", __func__, (int)T0, tlb->EPN, end);
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}
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#endif
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for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
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tlb_flush_page(env, page);
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}
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}
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void do_4xx_tlbwe_hi (void)
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void do_4xx_tlbwe_lo (void)
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{
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ppcemb_tlb_t *tlb;
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#if defined (DEBUG_SOFTWARE_TLB)
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if (loglevel) {
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fprintf(logfile, "%s T0 " REGX " T1 " REGX "\n", __func__, T0, T1);
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}
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#endif
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T0 &= 0x3F;
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tlb = &env->tlb[T0].tlbe;
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tlb->RPN = T1 & 0xFFFFFC00;
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@ -2578,5 +2611,16 @@ void do_4xx_tlbwe_hi (void)
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tlb->prot |= PAGE_EXEC;
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if (T1 & 0x100)
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tlb->prot |= PAGE_WRITE;
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#if defined (DEBUG_SOFTWARE_TLB)
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if (loglevel) {
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fprintf(logfile, "%s: set up TLB %d RPN " ADDRX " EPN " ADDRX
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" size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
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(int)T0, tlb->RPN, tlb->EPN, tlb->size,
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tlb->prot & PAGE_READ ? 'r' : '-',
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tlb->prot & PAGE_WRITE ? 'w' : '-',
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tlb->prot & PAGE_EXEC ? 'x' : '-',
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tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID);
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}
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#endif
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}
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#endif /* !CONFIG_USER_ONLY */
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