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Merge branch 'target-arm.for-upstream' of git://git.linaro.org/people/pmaydell/qemu-arm

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* 'target-arm.for-upstream' of git://git.linaro.org/people/pmaydell/qemu-arm:
  target-arm: Make SETEND respect bswap_code (BE8) setting
  target-arm: Move A9 config_base_address reset value to ARMCPU
  target-arm: Change cpu_arm_init() return type to ARMCPU
This commit is contained in:
Blue Swirl 2012-04-28 08:57:56 +00:00
commit c4c50b9edd
6 changed files with 19 additions and 23 deletions
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15
hw/highbank.c
View File

@ -35,12 +35,6 @@
#define NIRQ_GIC 160
/* Board init. */
static void highbank_cpu_reset(void *opaque)
{
CPUARMState *env = opaque;
env->cp15.c15_config_base_address = GIC_BASE_ADDR;
}
static void hb_write_secondary(CPUARMState *env, const struct arm_boot_info *info)
{
@ -213,14 +207,17 @@ static void highbank_init(ram_addr_t ram_size,
}
for (n = 0; n < smp_cpus; n++) {
env = cpu_init(cpu_model);
if (!env) {
ARMCPU *cpu;
cpu = cpu_arm_init(cpu_model);
if (cpu == NULL) {
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
env = &cpu->env;
/* This will become a QOM property eventually */
cpu->reset_cbar = GIC_BASE_ADDR;
irqp = arm_pic_init_cpu(env);
cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
qemu_register_reset(highbank_cpu_reset, env);
}
sysmem = get_system_memory();

2
target-arm/cpu-qom.h
View File

@ -21,7 +21,6 @@
#define QEMU_ARM_CPU_QOM_H
#include "qemu/cpu.h"
#include "cpu.h"
#define TYPE_ARM_CPU "arm-cpu"
@ -94,6 +93,7 @@ typedef struct ARMCPU {
* in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.
*/
uint32_t ccsidr[16];
uint32_t reset_cbar;
} ARMCPU;
static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)

6
target-arm/cpu.c
View File

@ -18,7 +18,7 @@
* <http://www.gnu.org/licenses/gpl-2.0.html>
*/
#include "cpu-qom.h"
#include "cpu.h"
#include "qemu-common.h"
#if !defined(CONFIG_USER_ONLY)
#include "hw/loader.h"
@ -30,7 +30,6 @@ static void arm_cpu_reset(CPUState *s)
ARMCPU *cpu = ARM_CPU(s);
ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
CPUARMState *env = &cpu->env;
uint32_t tmp = 0;
if (qemu_loglevel_mask(CPU_LOG_RESET)) {
qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
@ -39,9 +38,8 @@ static void arm_cpu_reset(CPUState *s)
acc->parent_reset(s);
tmp = env->cp15.c15_config_base_address;
memset(env, 0, offsetof(CPUARMState, breakpoints));
env->cp15.c15_config_base_address = tmp;
env->cp15.c15_config_base_address = cpu->reset_cbar;
env->cp15.c0_cpuid = cpu->midr;
env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;

7
target-arm/cpu.h
View File

@ -238,7 +238,9 @@ typedef struct CPUARMState {
const struct arm_boot_info *boot_info;
} CPUARMState;
CPUARMState *cpu_arm_init(const char *cpu_model);
#include "cpu-qom.h"
ARMCPU *cpu_arm_init(const char *cpu_model);
void arm_translate_init(void);
int cpu_arm_exec(CPUARMState *s);
void do_interrupt(CPUARMState *);
@ -456,7 +458,7 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32
#define cpu_init cpu_arm_init
#define cpu_init(model) (&cpu_arm_init(model)->env)
#define cpu_exec cpu_arm_exec
#define cpu_gen_code cpu_arm_gen_code
#define cpu_signal_handler cpu_arm_signal_handler
@ -483,7 +485,6 @@ static inline void cpu_clone_regs(CPUARMState *env, target_ulong newsp)
#endif
#include "cpu-all.h"
#include "cpu-qom.h"
/* Bit usage in the TB flags field: */
#define ARM_TBFLAG_THUMB_SHIFT 0

4
target-arm/helper.c
View File

@ -61,7 +61,7 @@ static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
return 0;
}
CPUARMState *cpu_arm_init(const char *cpu_model)
ARMCPU *cpu_arm_init(const char *cpu_model)
{
ARMCPU *cpu;
CPUARMState *env;
@ -92,7 +92,7 @@ CPUARMState *cpu_arm_init(const char *cpu_model)
19, "arm-vfp.xml", 0);
}
qemu_init_vcpu(env);
return env;
return cpu;
}
typedef struct ARMCPUListState {

8
target-arm/translate.c
View File

@ -6767,8 +6767,8 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s)
if ((insn & 0x0ffffdff) == 0x01010000) {
ARCH(6);
/* setend */
if (insn & (1 << 9)) {
/* BE8 mode not implemented. */
if (((insn >> 9) & 1) != s->bswap_code) {
/* Dynamic endianness switching not implemented. */
goto illegal_op;
}
return;
@ -9710,8 +9710,8 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
case 2:
/* setend */
ARCH(6);
if (insn & (1 << 3)) {
/* BE8 mode not implemented. */
if (((insn >> 3) & 1) != s->bswap_code) {
/* Dynamic endianness switching not implemented. */
goto illegal_op;
}
break;