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Implement fast tlb insert insns.

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Fix data tlb exception for pa 1.1.
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Merge remote-tracking branch 'remotes/rth/tags/pull-hppa-20190429' into staging

Implement fast tlb insert insns.
Fix data tlb exception for pa 1.1.

# gpg: Signature made Mon 29 Apr 2019 22:54:08 BST
# gpg:                using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg:                issuer "richard.henderson@linaro.org"
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A  05C0 64DF 38E8 AF7E 215F

* remotes/rth/tags/pull-hppa-20190429:
  target/hppa: Always return EXCP_DMAR for protection id trap
  target/hppa: Implement Fast TLB Insert instructions

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2019-04-30 10:20:22 +01:00
commit c4bfdd5947
3 changed files with 58 additions and 2 deletions
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3
target/hppa/insns.decode
View File

@ -133,6 +133,9 @@ ixtlbx 000001 b:5 r:5 sp:2 0100000 addr:1 0 00000 data=1
ixtlbx 000001 b:5 r:5 ... 000000 addr:1 0 00000 \
sp=%assemble_sr3x data=0
# pcxl and pcxl2 Fast TLB Insert instructions
ixtlbxf 000001 00000 r:5 00 0 data:1 01000 addr:1 0 00000
pxtlbx 000001 b:5 x:5 sp:2 0100100 local:1 m:1 ----- data=1
pxtlbx 000001 b:5 x:5 ... 000100 local:1 m:1 ----- \
sp=%assemble_sr3x data=0

3
target/hppa/mem_helper.c
View File

@ -154,8 +154,7 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx,
if (unlikely(!(prot & type))) {
/* The access isn't allowed -- Inst/Data Memory Protection Fault. */
ret = (type & PAGE_EXEC ? EXCP_IMP :
prot & PAGE_READ ? EXCP_DMP : EXCP_DMAR);
ret = (type & PAGE_EXEC) ? EXCP_IMP : EXCP_DMAR;
goto egress;
}

54
target/hppa/translate.c
View File

@ -2518,6 +2518,60 @@ static bool trans_pxtlbx(DisasContext *ctx, arg_pxtlbx *a)
#endif
}
/*
* Implement the pcxl and pcxl2 Fast TLB Insert instructions.
* See
* https://parisc.wiki.kernel.org/images-parisc/a/a9/Pcxl2_ers.pdf
* page 13-9 (195/206)
*/
static bool trans_ixtlbxf(DisasContext *ctx, arg_ixtlbxf *a)
{
CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);
#ifndef CONFIG_USER_ONLY
TCGv_tl addr, atl, stl;
TCGv_reg reg;
nullify_over(ctx);
/*
* FIXME:
* if (not (pcxl or pcxl2))
* return gen_illegal(ctx);
*
* Note for future: these are 32-bit systems; no hppa64.
*/
atl = tcg_temp_new_tl();
stl = tcg_temp_new_tl();
addr = tcg_temp_new_tl();
tcg_gen_ld32u_i64(stl, cpu_env,
a->data ? offsetof(CPUHPPAState, cr[CR_ISR])
: offsetof(CPUHPPAState, cr[CR_IIASQ]));
tcg_gen_ld32u_i64(atl, cpu_env,
a->data ? offsetof(CPUHPPAState, cr[CR_IOR])
: offsetof(CPUHPPAState, cr[CR_IIAOQ]));
tcg_gen_shli_i64(stl, stl, 32);
tcg_gen_or_tl(addr, atl, stl);
tcg_temp_free_tl(atl);
tcg_temp_free_tl(stl);
reg = load_gpr(ctx, a->r);
if (a->addr) {
gen_helper_itlba(cpu_env, addr, reg);
} else {
gen_helper_itlbp(cpu_env, addr, reg);
}
tcg_temp_free_tl(addr);
/* Exit TB for TLB change if mmu is enabled. */
if (ctx->tb_flags & PSW_C) {
ctx->base.is_jmp = DISAS_IAQ_N_STALE;
}
return nullify_end(ctx);
#endif
}
static bool trans_lpa(DisasContext *ctx, arg_ldst *a)
{
CHECK_MOST_PRIVILEGED(EXCP_PRIV_OPR);