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target/arm: Reject dup_i w/ shifted byte early

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Remove the unparsed extraction in trans_DUP_i,
which is intended to reject an 8-bit shift of
an 8-bit constant for 8-bit element.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220527181907.189259-72-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2022-05-27 11:18:24 -07:00 committed by Peter Maydell
parent fa4bd72cc1
commit c437c59ba1
2 changed files with 10 additions and 5 deletions
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5
target/arm/sve.decode
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@ -787,7 +787,10 @@ WHILE_ptr 00100101 esz:2 1 rm:5 001 100 rn:5 rw:1 rd:4
FDUP 00100101 esz:2 111 00 1110 imm:8 rd:5
# SVE broadcast integer immediate (unpredicated)
DUP_i 00100101 esz:2 111 00 011 . ........ rd:5 imm=%sh8_i8s
{
INVALID 00100101 00 111 00 011 1 -------- -----
DUP_i 00100101 esz:2 111 00 011 . ........ rd:5 imm=%sh8_i8s
}
# SVE integer add/subtract immediate (unpredicated)
ADD_zzi 00100101 .. 100 000 11 . ........ ..... @rdn_sh_i8u

10
target/arm/translate-sve.c
View File

@ -403,6 +403,12 @@ const uint64_t pred_esz_masks[4] = {
0x1111111111111111ull, 0x0101010101010101ull
};
static bool trans_INVALID(DisasContext *s, arg_INVALID *a)
{
unallocated_encoding(s);
return true;
}
/*
*** SVE Logical - Unpredicated Group
*/
@ -3246,13 +3252,9 @@ static bool trans_FDUP(DisasContext *s, arg_FDUP *a)
static bool trans_DUP_i(DisasContext *s, arg_DUP_i *a)
{
if (a->esz == 0 && extract32(s->insn, 13, 1)) {
return false;
}
if (sve_access_check(s)) {
unsigned vsz = vec_full_reg_size(s);
int dofs = vec_full_reg_offset(s, a->rd);
tcg_gen_gvec_dup_imm(a->esz, dofs, vsz, vsz, a->imm);
}
return true;