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acpi_piix4: Do not use old_portio-style callbacks

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Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
[AF: Used HWADDR_PRIx for hwaddr PIIX4_DPRINTF()]
Signed-off-by: Andreas Färber <afaerber@suse.de>
This commit is contained in:
Hervé Poussineau 2013-01-04 22:29:41 +01:00 committed by Andreas Färber
parent 7a652efa1b
commit c3a29809e4
1 changed files with 40 additions and 50 deletions
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90
hw/acpi_piix4.c
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@ -531,68 +531,58 @@ static const MemoryRegionOps piix4_gpe_ops = {
.endianness = DEVICE_LITTLE_ENDIAN, .endianness = DEVICE_LITTLE_ENDIAN,
}; };
static uint32_t pci_up_read(void *opaque, uint32_t addr) static uint64_t pci_read(void *opaque, hwaddr addr, unsigned int size)
{ {
PIIX4PMState *s = opaque; PIIX4PMState *s = opaque;
uint32_t val; uint32_t val = 0;
/* Manufacture an "up" value to cause a device check on any hotplug switch (addr) {
* slot with a device. Extra device checks are harmless. */ case PCI_UP_BASE - PCI_HOTPLUG_ADDR:
val = s->pci0_slot_device_present & s->pci0_hotplug_enable; /* Manufacture an "up" value to cause a device check on any hotplug
* slot with a device. Extra device checks are harmless. */
val = s->pci0_slot_device_present & s->pci0_hotplug_enable;
PIIX4_DPRINTF("pci_up_read %x\n", val);
break;
case PCI_DOWN_BASE - PCI_HOTPLUG_ADDR:
val = s->pci0_status.down;
PIIX4_DPRINTF("pci_down_read %x\n", val);
break;
case PCI_EJ_BASE - PCI_HOTPLUG_ADDR:
/* No feature defined yet */
PIIX4_DPRINTF("pci_features_read %x\n", val);
break;
case PCI_RMV_BASE - PCI_HOTPLUG_ADDR:
val = s->pci0_hotplug_enable;
break;
default:
break;
}
PIIX4_DPRINTF("pci_up_read %x\n", val);
return val; return val;
} }
static uint32_t pci_down_read(void *opaque, uint32_t addr) static void pci_write(void *opaque, hwaddr addr, uint64_t data,
unsigned int size)
{ {
PIIX4PMState *s = opaque; switch (addr) {
uint32_t val = s->pci0_status.down; case PCI_EJ_BASE - PCI_HOTPLUG_ADDR:
acpi_piix_eject_slot(opaque, (uint32_t)data);
PIIX4_DPRINTF("pci_down_read %x\n", val); PIIX4_DPRINTF("pciej write %" HWADDR_PRIx " <== % " PRIu64 "\n",
return val; addr, data);
} break;
default:
static uint32_t pci_features_read(void *opaque, uint32_t addr) break;
{ }
/* No feature defined yet */
PIIX4_DPRINTF("pci_features_read %x\n", 0);
return 0;
}
static void pciej_write(void *opaque, uint32_t addr, uint32_t val)
{
acpi_piix_eject_slot(opaque, val);
PIIX4_DPRINTF("pciej write %x <== %d\n", addr, val);
}
static uint32_t pcirmv_read(void *opaque, uint32_t addr)
{
PIIX4PMState *s = opaque;
return s->pci0_hotplug_enable;
} }
static const MemoryRegionOps piix4_pci_ops = { static const MemoryRegionOps piix4_pci_ops = {
.old_portio = (MemoryRegionPortio[]) { .read = pci_read,
{ .write = pci_write,
.offset = PCI_UP_BASE - PCI_HOTPLUG_ADDR, .len = 4, .size = 4,
.read = pci_up_read,
},{
.offset = PCI_DOWN_BASE - PCI_HOTPLUG_ADDR, .len = 4, .size = 4,
.read = pci_down_read,
},{
.offset = PCI_EJ_BASE - PCI_HOTPLUG_ADDR, .len = 4, .size = 4,
.read = pci_features_read,
.write = pciej_write,
},{
.offset = PCI_RMV_BASE - PCI_HOTPLUG_ADDR, .len = 4, .size = 4,
.read = pcirmv_read,
},
PORTIO_END_OF_LIST()
},
.endianness = DEVICE_LITTLE_ENDIAN, .endianness = DEVICE_LITTLE_ENDIAN,
.valid = {
.min_access_size = 4,
.max_access_size = 4,
},
}; };
static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev, static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev,