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target/sh4: Fix ADDV opcode

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The documentation says:

  ADDV Rm, Rn        Rn + Rm -> Rn, overflow -> T

But QEMU implementation was:

  ADDV Rm, Rn        Rn + Rm -> Rm, overflow -> T

Fix by filling the correct Rm register.

Add tests provided by Paul Cercueil.

Cc: qemu-stable@nongnu.org
Fixes: ad8d25a11f ("target-sh4: implement addv and subv using TCG")
Reported-by: Paul Cercueil <paul@crapouillou.net>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2317
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Message-Id: <20240430163125.77430-2-philmd@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé 2024-04-30 12:41:53 +02:00
parent a0dbef9f33
commit c365e6b070
3 changed files with 31 additions and 1 deletions
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2
target/sh4/translate.c
View File

@ -714,7 +714,7 @@ static void _decode_opc(DisasContext * ctx)
tcg_gen_xor_i32(t2, REG(B7_4), REG(B11_8));
tcg_gen_andc_i32(cpu_sr_t, t1, t2);
tcg_gen_shri_i32(cpu_sr_t, cpu_sr_t, 31);
tcg_gen_mov_i32(REG(B7_4), t0);
tcg_gen_mov_i32(REG(B11_8), t0);
}
return;
case 0x2009: /* and Rm,Rn */

3
tests/tcg/sh4/Makefile.target
View File

@ -17,3 +17,6 @@ TESTS += test-macl
test-macw: CFLAGS += -O -g
TESTS += test-macw
test-addv: CFLAGS += -O -g
TESTS += test-addv

27
tests/tcg/sh4/test-addv.c Normal file
View File

@ -0,0 +1,27 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <limits.h>
#include <stdio.h>
#include <stdlib.h>
static void addv(const int a, const int b, const int res, const int carry)
{
int o = a, c;
asm volatile("addv %2,%0\n"
"movt %1\n"
: "+r"(o), "=r"(c) : "r"(b) : );
if (c != carry || o != res) {
printf("ADDV %d, %d = %d/%d [T = %d/%d]\n", a, b, o, res, c, carry);
abort();
}
}
int main(void)
{
addv(INT_MAX, 1, INT_MIN, 1);
addv(INT_MAX - 1, 1, INT_MAX, 0);
return 0;
}