target-alpha: Move memory helpers to mem_helper.c.
This completes the transition away from AREG0. This patch must be last because it requires CONFIG_TCG_PASS_AREG0 set too. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Richard Henderson
Blue Swirl
parent
69163fbb0c
commit
c30827555d
@ -81,8 +81,10 @@ libobj-y += tcg/tcg.o tcg/optimize.o
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libobj-$(CONFIG_TCG_INTERPRETER) += tci.o
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libobj-y += fpu/softfloat.o
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ifneq ($(TARGET_BASE_ARCH), sparc)
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ifneq ($(TARGET_BASE_ARCH), alpha)
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libobj-y += op_helper.o
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endif
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endif
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libobj-y += helper.o
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ifeq ($(TARGET_BASE_ARCH), i386)
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libobj-y += cpuid.o
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@ -96,7 +98,7 @@ libobj-y += cpu_init.o
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endif
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libobj-$(TARGET_SPARC) += int32_helper.o
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libobj-$(TARGET_SPARC64) += int64_helper.o
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libobj-$(TARGET_ALPHA) += int_helper.o fpu_helper.o sys_helper.o
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libobj-$(TARGET_ALPHA) += int_helper.o fpu_helper.o sys_helper.o mem_helper.o
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libobj-y += disas.o
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libobj-$(CONFIG_TCI_DIS) += tci-dis.o
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2
configure
vendored
2
configure
vendored
@ -3608,7 +3608,7 @@ case "$target_arch2" in
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esac
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case "$target_arch2" in
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sparc*)
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alpha | sparc*)
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echo "CONFIG_TCG_PASS_AREG0=y" >> $config_target_mak
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;;
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esac
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@ -104,12 +104,12 @@ DEF_HELPER_2(hw_ret, void, env, i64)
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DEF_HELPER_1(ldl_phys, i64, i64)
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DEF_HELPER_1(ldq_phys, i64, i64)
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DEF_HELPER_1(ldl_l_phys, i64, i64)
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DEF_HELPER_1(ldq_l_phys, i64, i64)
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DEF_HELPER_2(ldl_l_phys, i64, env, i64)
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DEF_HELPER_2(ldq_l_phys, i64, env, i64)
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DEF_HELPER_2(stl_phys, void, i64, i64)
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DEF_HELPER_2(stq_phys, void, i64, i64)
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DEF_HELPER_2(stl_c_phys, i64, i64, i64)
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DEF_HELPER_2(stq_c_phys, i64, i64, i64)
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DEF_HELPER_3(stl_c_phys, i64, env, i64, i64)
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DEF_HELPER_3(stq_c_phys, i64, env, i64, i64)
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DEF_HELPER_FLAGS_1(tbia, TCG_CALL_CONST, void, env)
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DEF_HELPER_FLAGS_2(tbis, TCG_CALL_CONST, void, env, i64)
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@ -1,5 +1,5 @@
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/*
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* Alpha emulation cpu micro-operations helpers for qemu.
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* Helpers for loads and stores
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*
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* Copyright (c) 2007 Jocelyn Mayer
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*
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@ -18,17 +18,12 @@
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*/
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#include "cpu.h"
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#include "dyngen-exec.h"
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#include "host-utils.h"
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#include "softfloat.h"
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#include "helper.h"
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#include "sysemu.h"
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#include "qemu-timer.h"
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/*****************************************************************************/
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/* Softmmu support */
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#if !defined (CONFIG_USER_ONLY)
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#ifndef CONFIG_USER_ONLY
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uint64_t helper_ldl_phys(uint64_t p)
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{
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return (int32_t)ldl_phys(p);
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@ -39,16 +34,16 @@ uint64_t helper_ldq_phys(uint64_t p)
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return ldq_phys(p);
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}
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uint64_t helper_ldl_l_phys(uint64_t p)
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uint64_t helper_ldl_l_phys(CPUAlphaState *env, uint64_t p)
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{
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env->lock_addr = p;
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return env->lock_value = (int32_t)ldl_phys(p);
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}
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uint64_t helper_ldq_l_phys(uint64_t p)
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uint64_t helper_ldq_l_phys(CPUAlphaState *env, uint64_t p)
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{
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env->lock_addr = p;
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return env->lock_value = ldl_phys(p);
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return env->lock_value = ldq_phys(p);
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}
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void helper_stl_phys(uint64_t p, uint64_t v)
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@ -61,7 +56,7 @@ void helper_stq_phys(uint64_t p, uint64_t v)
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stq_phys(p, v);
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}
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uint64_t helper_stl_c_phys(uint64_t p, uint64_t v)
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uint64_t helper_stl_c_phys(CPUAlphaState *env, uint64_t p, uint64_t v)
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{
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uint64_t ret = 0;
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@ -77,7 +72,7 @@ uint64_t helper_stl_c_phys(uint64_t p, uint64_t v)
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return ret;
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}
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uint64_t helper_stq_c_phys(uint64_t p, uint64_t v)
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uint64_t helper_stq_c_phys(CPUAlphaState *env, uint64_t p, uint64_t v)
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{
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uint64_t ret = 0;
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@ -93,8 +88,8 @@ uint64_t helper_stq_c_phys(uint64_t p, uint64_t v)
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return ret;
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}
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static void QEMU_NORETURN do_unaligned_access(target_ulong addr, int is_write,
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int is_user, void *retaddr)
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static void do_unaligned_access(CPUAlphaState *env, target_ulong addr,
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int is_write, int is_user, void *retaddr)
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{
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uint64_t pc;
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uint32_t insn;
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@ -102,7 +97,7 @@ static void QEMU_NORETURN do_unaligned_access(target_ulong addr, int is_write,
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do_restore_state(env, retaddr);
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pc = env->pc;
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insn = ldl_code(pc);
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insn = cpu_ldl_code(env, pc);
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env->trap_arg0 = addr;
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env->trap_arg1 = insn >> 26; /* opcode */
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@ -112,14 +107,12 @@ static void QEMU_NORETURN do_unaligned_access(target_ulong addr, int is_write,
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cpu_loop_exit(env);
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}
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void QEMU_NORETURN cpu_unassigned_access(CPUAlphaState *env1,
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target_phys_addr_t addr, int is_write,
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int is_exec, int unused, int size)
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void cpu_unassigned_access(CPUAlphaState *env, target_phys_addr_t addr,
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int is_write, int is_exec, int unused, int size)
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{
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env = env1;
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env->trap_arg0 = addr;
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env->trap_arg1 = is_write;
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dynamic_excp(env1, GETPC(), EXCP_MCHK, 0);
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dynamic_excp(env, NULL, EXCP_MCHK, 0);
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}
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#include "softmmu_exec.h"
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@ -143,20 +136,16 @@ void QEMU_NORETURN cpu_unassigned_access(CPUAlphaState *env1,
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NULL, it means that the function was called in C code (i.e. not
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from generated code or from helper.c) */
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/* XXX: fix it to restore all registers */
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void tlb_fill(CPUAlphaState *env1, target_ulong addr, int is_write, int mmu_idx,
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void *retaddr)
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void tlb_fill(CPUAlphaState *env, target_ulong addr, int is_write,
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int mmu_idx, void *retaddr)
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{
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CPUAlphaState *saved_env;
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int ret;
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saved_env = env;
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env = env1;
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ret = cpu_alpha_handle_mmu_fault(env, addr, is_write, mmu_idx);
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if (unlikely(ret != 0)) {
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do_restore_state(env, retaddr);
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/* Exception index and error code are already set */
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cpu_loop_exit(env);
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}
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env = saved_env;
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}
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#endif
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#endif /* CONFIG_USER_ONLY */
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@ -2867,11 +2867,11 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
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break;
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case 0x2:
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/* Longword physical access with lock (hw_ldl_l/p) */
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gen_helper_ldl_l_phys(cpu_ir[ra], addr);
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gen_helper_ldl_l_phys(cpu_ir[ra], cpu_env, addr);
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break;
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case 0x3:
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/* Quadword physical access with lock (hw_ldq_l/p) */
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gen_helper_ldq_l_phys(cpu_ir[ra], addr);
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gen_helper_ldq_l_phys(cpu_ir[ra], cpu_env, addr);
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break;
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case 0x4:
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/* Longword virtual PTE fetch (hw_ldl/v) */
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@ -3180,11 +3180,11 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
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break;
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case 0x2:
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/* Longword physical access with lock */
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gen_helper_stl_c_phys(val, addr, val);
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gen_helper_stl_c_phys(val, cpu_env, addr, val);
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break;
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case 0x3:
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/* Quadword physical access with lock */
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gen_helper_stq_c_phys(val, addr, val);
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gen_helper_stq_c_phys(val, cpu_env, addr, val);
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break;
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case 0x4:
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/* Longword virtual access */
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@ -3420,7 +3420,7 @@ static inline void gen_intermediate_code_internal(CPUAlphaState *env,
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}
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if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
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gen_io_start();
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insn = ldl_code(ctx.pc);
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insn = cpu_ldl_code(env, ctx.pc);
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num_insns++;
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if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
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