Merge remote branch 'origin/master' into pci
This commit is contained in:
Michael S. Tsirkin
commit
c2e08bddcd
@ -2767,7 +2767,6 @@ print_insn_cris_generic (bfd_vma memaddr,
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}
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/* Disassemble, prefixing register names with `$'. CRIS v0..v10. */
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#if 0
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static int
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print_insn_cris_with_register_prefix (bfd_vma vma,
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disassemble_info *info)
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@ -2777,7 +2776,6 @@ print_insn_cris_with_register_prefix (bfd_vma vma,
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return -1;
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return print_insn_cris_generic (vma, info, true);
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}
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#endif
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/* Disassemble, prefixing register names with `$'. CRIS v32. */
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static int
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@ -2842,6 +2840,13 @@ print_insn_crisv10_v32_without_register_prefix (bfd_vma vma,
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}
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#endif
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int
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print_insn_crisv10 (bfd_vma vma,
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disassemble_info *info)
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{
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return print_insn_cris_with_register_prefix(vma, info);
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}
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int
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print_insn_crisv32 (bfd_vma vma,
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disassemble_info *info)
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@ -397,6 +397,7 @@ extern int print_insn_tic30 (bfd_vma, disassemble_info*);
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extern int print_insn_ppc (bfd_vma, disassemble_info*);
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extern int print_insn_s390 (bfd_vma, disassemble_info*);
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extern int print_insn_crisv32 (bfd_vma, disassemble_info*);
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extern int print_insn_crisv10 (bfd_vma, disassemble_info*);
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extern int print_insn_microblaze (bfd_vma, disassemble_info*);
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extern int print_insn_ia64 (bfd_vma, disassemble_info*);
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9
disas.c
9
disas.c
@ -208,8 +208,13 @@ void target_disas(FILE *out, target_ulong code, target_ulong size, int flags)
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disasm_info.mach = bfd_mach_alpha;
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print_insn = print_insn_alpha;
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#elif defined(TARGET_CRIS)
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disasm_info.mach = bfd_mach_cris_v32;
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print_insn = print_insn_crisv32;
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if (flags != 32) {
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disasm_info.mach = bfd_mach_cris_v0_v10;
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print_insn = print_insn_crisv10;
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} else {
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disasm_info.mach = bfd_mach_cris_v32;
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print_insn = print_insn_crisv32;
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}
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#elif defined(TARGET_MICROBLAZE)
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disasm_info.mach = bfd_arch_microblaze;
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print_insn = print_insn_microblaze;
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@ -120,9 +120,10 @@ typedef struct DisasContext {
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unsigned int tb_flags; /* tb dependent flags. */
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int is_jmp;
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#define JMP_NOJMP 0
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#define JMP_DIRECT 1
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#define JMP_INDIRECT 2
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#define JMP_NOJMP 0
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#define JMP_DIRECT 1
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#define JMP_DIRECT_CC 2
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#define JMP_INDIRECT 3
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int jmp; /* 0=nojmp, 1=direct, 2=indirect. */
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uint32_t jmp_pc;
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@ -1127,7 +1128,7 @@ static void gen_tst_cc (DisasContext *dc, TCGv cc, int cond)
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static void cris_store_direct_jmp(DisasContext *dc)
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{
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/* Store the direct jmp state into the cpu-state. */
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if (dc->jmp == JMP_DIRECT) {
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if (dc->jmp == JMP_DIRECT || dc->jmp == JMP_DIRECT_CC) {
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tcg_gen_movi_tl(env_btarget, dc->jmp_pc);
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dc->jmp = JMP_INDIRECT;
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}
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@ -1139,7 +1140,7 @@ static void cris_prepare_cc_branch (DisasContext *dc,
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/* This helps us re-schedule the micro-code to insns in delay-slots
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before the actual jump. */
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dc->delayed_branch = 2;
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dc->jmp = JMP_DIRECT;
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dc->jmp = JMP_DIRECT_CC;
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dc->jmp_pc = dc->pc + offset;
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gen_tst_cc (dc, env_btaken, cond);
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@ -1155,7 +1156,9 @@ static inline void cris_prepare_jmp (DisasContext *dc, unsigned int type)
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before the actual jump. */
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dc->delayed_branch = 2;
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dc->jmp = type;
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tcg_gen_movi_tl(env_btaken, 1);
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if (type == JMP_INDIRECT) {
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tcg_gen_movi_tl(env_btaken, 1);
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}
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}
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static void gen_load64(DisasContext *dc, TCGv_i64 dst, TCGv addr)
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@ -3182,7 +3185,7 @@ gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
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{
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uint16_t *gen_opc_end;
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uint32_t pc_start;
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unsigned int insn_len, orig_flags;
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unsigned int insn_len;
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int j, lj;
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struct DisasContext ctx;
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struct DisasContext *dc = &ctx;
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@ -3193,10 +3196,13 @@ gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
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qemu_log_try_set_file(stderr);
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if (env->pregs[PR_VR] == 32)
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if (env->pregs[PR_VR] == 32) {
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dc->decoder = crisv32_decoder;
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else
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dc->clear_locked_irq = 0;
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} else {
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dc->decoder = crisv10_decoder;
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dc->clear_locked_irq = 1;
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}
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/* Odd PC indicates that branch is rexecuting due to exception in the
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* delayslot, like in real hw.
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@ -3218,13 +3224,12 @@ gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
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dc->cc_mask = 0;
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dc->update_cc = 0;
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dc->clear_prefix = 0;
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dc->clear_locked_irq = 1;
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cris_update_cc_op(dc, CC_OP_FLAGS, 4);
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dc->cc_size_uptodate = -1;
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/* Decode TB flags. */
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orig_flags = dc->tb_flags = tb->flags & (S_FLAG | P_FLAG | U_FLAG \
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dc->tb_flags = tb->flags & (S_FLAG | P_FLAG | U_FLAG \
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| X_FLAG | PFIX_FLAG);
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dc->delayed_branch = !!(tb->flags & 7);
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if (dc->delayed_branch)
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@ -3312,7 +3317,14 @@ gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
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|| (dc->flags_x != (tb->flags & X_FLAG))) {
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cris_store_direct_jmp(dc);
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}
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if (dc->jmp == JMP_DIRECT) {
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if (dc->clear_locked_irq) {
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dc->clear_locked_irq = 0;
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t_gen_mov_env_TN(locked_irq,
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tcg_const_tl(0));
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}
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if (dc->jmp == JMP_DIRECT_CC) {
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int l1;
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l1 = gen_new_label();
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@ -3326,6 +3338,11 @@ gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
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gen_goto_tb(dc, 0, dc->pc);
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dc->is_jmp = DISAS_TB_JUMP;
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dc->jmp = JMP_NOJMP;
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} else if (dc->jmp == JMP_DIRECT) {
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cris_evaluate_flags(dc);
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gen_goto_tb(dc, 0, dc->jmp_pc);
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dc->is_jmp = DISAS_TB_JUMP;
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dc->jmp = JMP_NOJMP;
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} else {
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t_gen_cc_jmp(env_btarget,
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tcg_const_tl(dc->pc));
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@ -1060,15 +1060,15 @@ static unsigned int dec10_ind(DisasContext *dc)
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break;
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case CRISV10_IND_JUMP_M:
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if (dc->src == 15) {
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LOG_DIS("jump.%d %d r%d r%d\n", size,
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LOG_DIS("jump.%d %d r%d r%d direct\n", size,
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dc->opcode, dc->src, dc->dst);
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imm = ldl_code(dc->pc + 2);
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if (dc->mode == CRISV10_MODE_AUTOINC)
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insn_len += size;
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t_gen_mov_preg_TN(dc, dc->dst, tcg_const_tl(dc->pc + insn_len));
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tcg_gen_movi_tl(env_btarget, imm);
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cris_prepare_jmp(dc, JMP_INDIRECT);
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dc->jmp_pc = imm;
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cris_prepare_jmp(dc, JMP_DIRECT);
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dc->delayed_branch--; /* v10 has no dslot here. */
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} else {
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if (dc->dst == 14) {
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@ -1184,7 +1184,9 @@ static unsigned int crisv10_decoder(DisasContext *dc)
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if (dc->clear_prefix && dc->tb_flags & PFIX_FLAG) {
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dc->tb_flags &= ~PFIX_FLAG;
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tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~PFIX_FLAG);
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dc->cpustate_changed = 1;
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if (dc->tb_flags != dc->tb->flags) {
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dc->cpustate_changed = 1;
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}
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}
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/* CRISv10 locks out interrupts on dslots. */
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