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target-openrisc: Update OpenRISCCPU to QOM realizefn

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Update the openrisc_cpu_realize() signature, hook it up to
DeviceClass::realize and set realized = true in cpu_openrisc_init().

qapi/error.h is now included through qdev and no longer needed.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Cc: Jia Liu <proljc@gmail.com>
This commit is contained in:
Andreas Färber 2013-01-05 14:11:07 +01:00
parent 2b6f294cac
commit c296262bc9
2 changed files with 12 additions and 5 deletions
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13
target-openrisc/cpu.c
View File

@ -62,12 +62,15 @@ static inline void set_feature(OpenRISCCPU *cpu, int feature)
cpu->env.cpucfgr = cpu->feature; cpu->env.cpucfgr = cpu->feature;
} }
void openrisc_cpu_realize(Object *obj, Error **errp) static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp)
{ {
OpenRISCCPU *cpu = OPENRISC_CPU(obj); OpenRISCCPU *cpu = OPENRISC_CPU(dev);
OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(dev);
qemu_init_vcpu(&cpu->env); qemu_init_vcpu(&cpu->env);
cpu_reset(CPU(cpu)); cpu_reset(CPU(cpu));
occ->parent_realize(dev, errp);
} }
static void openrisc_cpu_initfn(Object *obj) static void openrisc_cpu_initfn(Object *obj)
@ -134,6 +137,10 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
{ {
OpenRISCCPUClass *occ = OPENRISC_CPU_CLASS(oc); OpenRISCCPUClass *occ = OPENRISC_CPU_CLASS(oc);
CPUClass *cc = CPU_CLASS(occ); CPUClass *cc = CPU_CLASS(occ);
DeviceClass *dc = DEVICE_CLASS(oc);
occ->parent_realize = dc->realize;
dc->realize = openrisc_cpu_realizefn;
occ->parent_reset = cc->reset; occ->parent_reset = cc->reset;
cc->reset = openrisc_cpu_reset; cc->reset = openrisc_cpu_reset;
@ -187,7 +194,7 @@ OpenRISCCPU *cpu_openrisc_init(const char *cpu_model)
cpu = OPENRISC_CPU(object_new(object_class_get_name(oc))); cpu = OPENRISC_CPU(object_new(object_class_get_name(oc)));
cpu->env.cpu_model_str = cpu_model; cpu->env.cpu_model_str = cpu_model;
openrisc_cpu_realize(OBJECT(cpu), NULL); object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
return cpu; return cpu;
} }

4
target-openrisc/cpu.h
View File

@ -33,7 +33,6 @@ struct OpenRISCCPU;
#include "exec/cpu-defs.h" #include "exec/cpu-defs.h"
#include "fpu/softfloat.h" #include "fpu/softfloat.h"
#include "qom/cpu.h" #include "qom/cpu.h"
#include "qapi/error.h"
#define TYPE_OPENRISC_CPU "or32-cpu" #define TYPE_OPENRISC_CPU "or32-cpu"
@ -46,6 +45,7 @@ struct OpenRISCCPU;
/** /**
* OpenRISCCPUClass: * OpenRISCCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_reset: The parent class' reset handler. * @parent_reset: The parent class' reset handler.
* *
* A OpenRISC CPU model. * A OpenRISC CPU model.
@ -55,6 +55,7 @@ typedef struct OpenRISCCPUClass {
CPUClass parent_class; CPUClass parent_class;
/*< public >*/ /*< public >*/
DeviceRealize parent_realize;
void (*parent_reset)(CPUState *cpu); void (*parent_reset)(CPUState *cpu);
} OpenRISCCPUClass; } OpenRISCCPUClass;
@ -340,7 +341,6 @@ static inline OpenRISCCPU *openrisc_env_get_cpu(CPUOpenRISCState *env)
#define ENV_GET_CPU(e) CPU(openrisc_env_get_cpu(e)) #define ENV_GET_CPU(e) CPU(openrisc_env_get_cpu(e))
OpenRISCCPU *cpu_openrisc_init(const char *cpu_model); OpenRISCCPU *cpu_openrisc_init(const char *cpu_model);
void openrisc_cpu_realize(Object *obj, Error **errp);
void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf); void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf);
int cpu_openrisc_exec(CPUOpenRISCState *s); int cpu_openrisc_exec(CPUOpenRISCState *s);