hw/nvram: Add BCM2835 OTP device
The OTP device registers are currently stubbed. For now, the device houses the OTP rows which will be accessed directly by other peripherals. Signed-off-by: Rayhan Faizel <rayhan.faizel@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Rayhan Faizel
Peter Maydell
parent
b6d32a06fc
commit
c1bf754041
187
hw/nvram/bcm2835_otp.c
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187
hw/nvram/bcm2835_otp.c
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@ -0,0 +1,187 @@
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/*
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* BCM2835 One-Time Programmable (OTP) Memory
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*
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* The OTP implementation is mostly a stub except for the OTP rows
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* which are accessed directly by other peripherals such as the mailbox.
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*
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* The OTP registers are unimplemented due to lack of documentation.
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*
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* Copyright (c) 2024 Rayhan Faizel <rayhan.faizel@gmail.com>
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*
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* SPDX-License-Identifier: MIT
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "hw/nvram/bcm2835_otp.h"
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#include "migration/vmstate.h"
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/* OTP rows are 1-indexed */
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uint32_t bcm2835_otp_get_row(BCM2835OTPState *s, unsigned int row)
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{
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assert(row <= BCM2835_OTP_ROW_COUNT && row >= 1);
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return s->otp_rows[row - 1];
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}
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void bcm2835_otp_set_row(BCM2835OTPState *s, unsigned int row,
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uint32_t value)
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{
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assert(row <= BCM2835_OTP_ROW_COUNT && row >= 1);
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/* Real OTP rows work as e-fuses */
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s->otp_rows[row - 1] |= value;
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}
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static uint64_t bcm2835_otp_read(void *opaque, hwaddr addr, unsigned size)
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{
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switch (addr) {
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case BCM2835_OTP_BOOTMODE_REG:
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qemu_log_mask(LOG_UNIMP,
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"bcm2835_otp: BCM2835_OTP_BOOTMODE_REG\n");
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break;
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case BCM2835_OTP_CONFIG_REG:
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qemu_log_mask(LOG_UNIMP,
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"bcm2835_otp: BCM2835_OTP_CONFIG_REG\n");
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break;
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case BCM2835_OTP_CTRL_LO_REG:
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qemu_log_mask(LOG_UNIMP,
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"bcm2835_otp: BCM2835_OTP_CTRL_LO_REG\n");
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break;
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case BCM2835_OTP_CTRL_HI_REG:
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qemu_log_mask(LOG_UNIMP,
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"bcm2835_otp: BCM2835_OTP_CTRL_HI_REG\n");
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break;
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case BCM2835_OTP_STATUS_REG:
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qemu_log_mask(LOG_UNIMP,
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"bcm2835_otp: BCM2835_OTP_STATUS_REG\n");
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break;
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case BCM2835_OTP_BITSEL_REG:
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qemu_log_mask(LOG_UNIMP,
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"bcm2835_otp: BCM2835_OTP_BITSEL_REG\n");
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break;
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case BCM2835_OTP_DATA_REG:
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qemu_log_mask(LOG_UNIMP,
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"bcm2835_otp: BCM2835_OTP_DATA_REG\n");
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break;
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case BCM2835_OTP_ADDR_REG:
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qemu_log_mask(LOG_UNIMP,
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"bcm2835_otp: BCM2835_OTP_ADDR_REG\n");
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break;
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case BCM2835_OTP_WRITE_DATA_READ_REG:
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qemu_log_mask(LOG_UNIMP,
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"bcm2835_otp: BCM2835_OTP_WRITE_DATA_READ_REG\n");
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break;
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case BCM2835_OTP_INIT_STATUS_REG:
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qemu_log_mask(LOG_UNIMP,
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"bcm2835_otp: BCM2835_OTP_INIT_STATUS_REG\n");
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, addr);
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}
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return 0;
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}
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static void bcm2835_otp_write(void *opaque, hwaddr addr,
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uint64_t value, unsigned int size)
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{
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switch (addr) {
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case BCM2835_OTP_BOOTMODE_REG:
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qemu_log_mask(LOG_UNIMP,
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"bcm2835_otp: BCM2835_OTP_BOOTMODE_REG\n");
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break;
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case BCM2835_OTP_CONFIG_REG:
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qemu_log_mask(LOG_UNIMP,
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"bcm2835_otp: BCM2835_OTP_CONFIG_REG\n");
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break;
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case BCM2835_OTP_CTRL_LO_REG:
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qemu_log_mask(LOG_UNIMP,
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"bcm2835_otp: BCM2835_OTP_CTRL_LO_REG\n");
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break;
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case BCM2835_OTP_CTRL_HI_REG:
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qemu_log_mask(LOG_UNIMP,
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"bcm2835_otp: BCM2835_OTP_CTRL_HI_REG\n");
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break;
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case BCM2835_OTP_STATUS_REG:
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qemu_log_mask(LOG_UNIMP,
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"bcm2835_otp: BCM2835_OTP_STATUS_REG\n");
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break;
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case BCM2835_OTP_BITSEL_REG:
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qemu_log_mask(LOG_UNIMP,
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"bcm2835_otp: BCM2835_OTP_BITSEL_REG\n");
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break;
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case BCM2835_OTP_DATA_REG:
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qemu_log_mask(LOG_UNIMP,
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"bcm2835_otp: BCM2835_OTP_DATA_REG\n");
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break;
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case BCM2835_OTP_ADDR_REG:
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qemu_log_mask(LOG_UNIMP,
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"bcm2835_otp: BCM2835_OTP_ADDR_REG\n");
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break;
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case BCM2835_OTP_WRITE_DATA_READ_REG:
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qemu_log_mask(LOG_UNIMP,
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"bcm2835_otp: BCM2835_OTP_WRITE_DATA_READ_REG\n");
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break;
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case BCM2835_OTP_INIT_STATUS_REG:
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qemu_log_mask(LOG_UNIMP,
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"bcm2835_otp: BCM2835_OTP_INIT_STATUS_REG\n");
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, addr);
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}
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}
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static const MemoryRegionOps bcm2835_otp_ops = {
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.read = bcm2835_otp_read,
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.write = bcm2835_otp_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.impl = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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static void bcm2835_otp_realize(DeviceState *dev, Error **errp)
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{
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BCM2835OTPState *s = BCM2835_OTP(dev);
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memory_region_init_io(&s->iomem, OBJECT(dev), &bcm2835_otp_ops, s,
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TYPE_BCM2835_OTP, 0x80);
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sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
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memset(s->otp_rows, 0x00, sizeof(s->otp_rows));
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}
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static const VMStateDescription vmstate_bcm2835_otp = {
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.name = TYPE_BCM2835_OTP,
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (const VMStateField[]) {
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VMSTATE_UINT32_ARRAY(otp_rows, BCM2835OTPState, BCM2835_OTP_ROW_COUNT),
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VMSTATE_END_OF_LIST()
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}
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};
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static void bcm2835_otp_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = bcm2835_otp_realize;
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dc->vmsd = &vmstate_bcm2835_otp;
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}
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static const TypeInfo bcm2835_otp_info = {
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.name = TYPE_BCM2835_OTP,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(BCM2835OTPState),
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.class_init = bcm2835_otp_class_init,
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};
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static void bcm2835_otp_register_types(void)
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{
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type_register_static(&bcm2835_otp_info);
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}
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type_init(bcm2835_otp_register_types)
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@ -1,5 +1,6 @@
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system_ss.add(files('fw_cfg-interface.c'))
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system_ss.add(files('fw_cfg.c'))
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system_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_otp.c'))
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system_ss.add(when: 'CONFIG_CHRP_NVRAM', if_true: files('chrp_nvram.c'))
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system_ss.add(when: 'CONFIG_DS1225Y', if_true: files('ds1225y.c'))
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system_ss.add(when: 'CONFIG_NMC93XX_EEPROM', if_true: files('eeprom93xx.c'))
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68
include/hw/nvram/bcm2835_otp.h
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68
include/hw/nvram/bcm2835_otp.h
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@ -0,0 +1,68 @@
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/*
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* BCM2835 One-Time Programmable (OTP) Memory
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*
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* Copyright (c) 2024 Rayhan Faizel <rayhan.faizel@gmail.com>
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*
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* SPDX-License-Identifier: MIT
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*/
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#ifndef BCM2835_OTP_H
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#define BCM2835_OTP_H
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#include "hw/sysbus.h"
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#include "qom/object.h"
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#define TYPE_BCM2835_OTP "bcm2835-otp"
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OBJECT_DECLARE_SIMPLE_TYPE(BCM2835OTPState, BCM2835_OTP)
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#define BCM2835_OTP_ROW_COUNT 66
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/* https://elinux.org/BCM2835_registers#OTP */
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#define BCM2835_OTP_BOOTMODE_REG 0x00
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#define BCM2835_OTP_CONFIG_REG 0x04
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#define BCM2835_OTP_CTRL_LO_REG 0x08
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#define BCM2835_OTP_CTRL_HI_REG 0x0c
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#define BCM2835_OTP_STATUS_REG 0x10
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#define BCM2835_OTP_BITSEL_REG 0x14
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#define BCM2835_OTP_DATA_REG 0x18
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#define BCM2835_OTP_ADDR_REG 0x1c
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#define BCM2835_OTP_WRITE_DATA_READ_REG 0x20
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#define BCM2835_OTP_INIT_STATUS_REG 0x24
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/* -- Row 32: Undocumented -- */
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#define BCM2835_OTP_ROW_32 32
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/* Lock OTP Programming (Customer OTP and private key) */
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#define BCM2835_OTP_ROW_32_LOCK BIT(6)
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/* -- Row 36-43: Customer OTP -- */
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#define BCM2835_OTP_CUSTOMER_OTP 36
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#define BCM2835_OTP_CUSTOMER_OTP_LEN 8
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/* Magic numbers to lock programming of customer OTP and private key */
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#define BCM2835_OTP_LOCK_NUM1 0xffffffff
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#define BCM2835_OTP_LOCK_NUM2 0xaffe0000
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/* -- Row 56-63: Device-specific private key -- */
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#define BCM2835_OTP_PRIVATE_KEY 56
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#define BCM2835_OTP_PRIVATE_KEY_LEN 8
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struct BCM2835OTPState {
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/* <private> */
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SysBusDevice parent_obj;
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/* <public> */
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MemoryRegion iomem;
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uint32_t otp_rows[BCM2835_OTP_ROW_COUNT];
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};
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uint32_t bcm2835_otp_get_row(BCM2835OTPState *s, unsigned int row);
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void bcm2835_otp_set_row(BCM2835OTPState *s, unsigned int row, uint32_t value);
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#endif
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