target/arm: Implement LDG, STG, ST2G instructions
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200626033144.790098-16-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson
Peter Maydell
parent
0d1762e931
commit
c15294c1e3
@ -106,3 +106,10 @@ DEF_HELPER_FLAGS_2(xpacd, TCG_CALL_NO_RWG_SE, i64, env, i64)
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DEF_HELPER_FLAGS_3(irg, TCG_CALL_NO_RWG, i64, env, i64, i64)
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DEF_HELPER_FLAGS_4(addsubg, TCG_CALL_NO_RWG_SE, i64, env, i64, s32, i32)
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DEF_HELPER_FLAGS_3(ldg, TCG_CALL_NO_WG, i64, env, i64, i64)
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DEF_HELPER_FLAGS_3(stg, TCG_CALL_NO_WG, void, env, i64, i64)
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DEF_HELPER_FLAGS_3(stg_parallel, TCG_CALL_NO_WG, void, env, i64, i64)
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DEF_HELPER_FLAGS_2(stg_stub, TCG_CALL_NO_WG, void, env, i64)
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DEF_HELPER_FLAGS_3(st2g, TCG_CALL_NO_WG, void, env, i64, i64)
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DEF_HELPER_FLAGS_3(st2g_parallel, TCG_CALL_NO_WG, void, env, i64, i64)
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DEF_HELPER_FLAGS_2(st2g_stub, TCG_CALL_NO_WG, void, env, i64)
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@ -96,6 +96,8 @@ DEF_HELPER_FLAGS_1(rebuild_hflags_a32_newel, TCG_CALL_NO_RWG, void, env)
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DEF_HELPER_FLAGS_2(rebuild_hflags_a32, TCG_CALL_NO_RWG, void, env, int)
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DEF_HELPER_FLAGS_2(rebuild_hflags_a64, TCG_CALL_NO_RWG, void, env, int)
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DEF_HELPER_FLAGS_5(probe_access, TCG_CALL_NO_WG, void, env, tl, i32, i32, i32)
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DEF_HELPER_1(vfp_get_fpscr, i32, env)
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DEF_HELPER_2(vfp_set_fpscr, void, env, i32)
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@ -44,6 +44,40 @@ static int choose_nonexcluded_tag(int tag, int offset, uint16_t exclude)
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return tag;
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}
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/**
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* allocation_tag_mem:
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* @env: the cpu environment
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* @ptr_mmu_idx: the addressing regime to use for the virtual address
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* @ptr: the virtual address for which to look up tag memory
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* @ptr_access: the access to use for the virtual address
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* @ptr_size: the number of bytes in the normal memory access
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* @tag_access: the access to use for the tag memory
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* @tag_size: the number of bytes in the tag memory access
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* @ra: the return address for exception handling
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*
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* Our tag memory is formatted as a sequence of little-endian nibbles.
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* That is, the byte at (addr >> (LOG2_TAG_GRANULE + 1)) contains two
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* tags, with the tag at [3:0] for the lower addr and the tag at [7:4]
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* for the higher addr.
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*
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* Here, resolve the physical address from the virtual address, and return
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* a pointer to the corresponding tag byte. Exit with exception if the
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* virtual address is not accessible for @ptr_access.
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*
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* The @ptr_size and @tag_size values may not have an obvious relation
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* due to the alignment of @ptr, and the number of tag checks required.
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*
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* If there is no tag storage corresponding to @ptr, return NULL.
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*/
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static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx,
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uint64_t ptr, MMUAccessType ptr_access,
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int ptr_size, MMUAccessType tag_access,
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int tag_size, uintptr_t ra)
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{
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/* Tag storage not implemented. */
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return NULL;
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}
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uint64_t HELPER(irg)(CPUARMState *env, uint64_t rn, uint64_t rm)
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{
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int rtag;
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@ -80,3 +114,163 @@ uint64_t HELPER(addsubg)(CPUARMState *env, uint64_t ptr,
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return address_with_allocation_tag(ptr + offset, rtag);
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}
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static int load_tag1(uint64_t ptr, uint8_t *mem)
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{
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int ofs = extract32(ptr, LOG2_TAG_GRANULE, 1) * 4;
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return extract32(*mem, ofs, 4);
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}
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uint64_t HELPER(ldg)(CPUARMState *env, uint64_t ptr, uint64_t xt)
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{
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int mmu_idx = cpu_mmu_index(env, false);
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uint8_t *mem;
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int rtag = 0;
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/* Trap if accessing an invalid page. */
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mem = allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_LOAD, 1,
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MMU_DATA_LOAD, 1, GETPC());
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/* Load if page supports tags. */
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if (mem) {
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rtag = load_tag1(ptr, mem);
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}
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return address_with_allocation_tag(xt, rtag);
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}
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static void check_tag_aligned(CPUARMState *env, uint64_t ptr, uintptr_t ra)
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{
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if (unlikely(!QEMU_IS_ALIGNED(ptr, TAG_GRANULE))) {
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arm_cpu_do_unaligned_access(env_cpu(env), ptr, MMU_DATA_STORE,
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cpu_mmu_index(env, false), ra);
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g_assert_not_reached();
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}
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}
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/* For use in a non-parallel context, store to the given nibble. */
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static void store_tag1(uint64_t ptr, uint8_t *mem, int tag)
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{
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int ofs = extract32(ptr, LOG2_TAG_GRANULE, 1) * 4;
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*mem = deposit32(*mem, ofs, 4, tag);
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}
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/* For use in a parallel context, atomically store to the given nibble. */
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static void store_tag1_parallel(uint64_t ptr, uint8_t *mem, int tag)
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{
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int ofs = extract32(ptr, LOG2_TAG_GRANULE, 1) * 4;
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uint8_t old = atomic_read(mem);
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while (1) {
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uint8_t new = deposit32(old, ofs, 4, tag);
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uint8_t cmp = atomic_cmpxchg(mem, old, new);
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if (likely(cmp == old)) {
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return;
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}
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old = cmp;
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}
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}
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typedef void stg_store1(uint64_t, uint8_t *, int);
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static inline void do_stg(CPUARMState *env, uint64_t ptr, uint64_t xt,
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uintptr_t ra, stg_store1 store1)
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{
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int mmu_idx = cpu_mmu_index(env, false);
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uint8_t *mem;
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check_tag_aligned(env, ptr, ra);
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/* Trap if accessing an invalid page. */
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mem = allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_STORE, TAG_GRANULE,
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MMU_DATA_STORE, 1, ra);
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/* Store if page supports tags. */
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if (mem) {
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store1(ptr, mem, allocation_tag_from_addr(xt));
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}
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}
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void HELPER(stg)(CPUARMState *env, uint64_t ptr, uint64_t xt)
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{
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do_stg(env, ptr, xt, GETPC(), store_tag1);
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}
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void HELPER(stg_parallel)(CPUARMState *env, uint64_t ptr, uint64_t xt)
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{
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do_stg(env, ptr, xt, GETPC(), store_tag1_parallel);
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}
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void HELPER(stg_stub)(CPUARMState *env, uint64_t ptr)
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{
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int mmu_idx = cpu_mmu_index(env, false);
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uintptr_t ra = GETPC();
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check_tag_aligned(env, ptr, ra);
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probe_write(env, ptr, TAG_GRANULE, mmu_idx, ra);
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}
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static inline void do_st2g(CPUARMState *env, uint64_t ptr, uint64_t xt,
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uintptr_t ra, stg_store1 store1)
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{
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int mmu_idx = cpu_mmu_index(env, false);
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int tag = allocation_tag_from_addr(xt);
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uint8_t *mem1, *mem2;
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check_tag_aligned(env, ptr, ra);
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/*
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* Trap if accessing an invalid page(s).
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* This takes priority over !allocation_tag_access_enabled.
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*/
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if (ptr & TAG_GRANULE) {
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/* Two stores unaligned mod TAG_GRANULE*2 -- modify two bytes. */
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mem1 = allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_STORE,
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TAG_GRANULE, MMU_DATA_STORE, 1, ra);
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mem2 = allocation_tag_mem(env, mmu_idx, ptr + TAG_GRANULE,
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MMU_DATA_STORE, TAG_GRANULE,
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MMU_DATA_STORE, 1, ra);
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/* Store if page(s) support tags. */
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if (mem1) {
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store1(TAG_GRANULE, mem1, tag);
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}
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if (mem2) {
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store1(0, mem2, tag);
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}
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} else {
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/* Two stores aligned mod TAG_GRANULE*2 -- modify one byte. */
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mem1 = allocation_tag_mem(env, mmu_idx, ptr, MMU_DATA_STORE,
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2 * TAG_GRANULE, MMU_DATA_STORE, 1, ra);
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if (mem1) {
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tag |= tag << 4;
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atomic_set(mem1, tag);
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}
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}
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}
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void HELPER(st2g)(CPUARMState *env, uint64_t ptr, uint64_t xt)
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{
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do_st2g(env, ptr, xt, GETPC(), store_tag1);
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}
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void HELPER(st2g_parallel)(CPUARMState *env, uint64_t ptr, uint64_t xt)
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{
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do_st2g(env, ptr, xt, GETPC(), store_tag1_parallel);
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}
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void HELPER(st2g_stub)(CPUARMState *env, uint64_t ptr)
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{
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int mmu_idx = cpu_mmu_index(env, false);
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uintptr_t ra = GETPC();
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int in_page = -(ptr | TARGET_PAGE_MASK);
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check_tag_aligned(env, ptr, ra);
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if (likely(in_page >= 2 * TAG_GRANULE)) {
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probe_write(env, ptr, 2 * TAG_GRANULE, mmu_idx, ra);
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} else {
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probe_write(env, ptr, TAG_GRANULE, mmu_idx, ra);
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probe_write(env, ptr + TAG_GRANULE, TAG_GRANULE, mmu_idx, ra);
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}
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}
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@ -935,3 +935,19 @@ uint32_t HELPER(ror_cc)(CPUARMState *env, uint32_t x, uint32_t i)
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return ((uint32_t)x >> shift) | (x << (32 - shift));
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}
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}
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void HELPER(probe_access)(CPUARMState *env, target_ulong ptr,
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uint32_t access_type, uint32_t mmu_idx,
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uint32_t size)
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{
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uint32_t in_page = -((uint32_t)ptr | TARGET_PAGE_SIZE);
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uintptr_t ra = GETPC();
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if (likely(size <= in_page)) {
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probe_access(env, ptr, size, access_type, mmu_idx, ra);
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} else {
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probe_access(env, ptr, in_page, access_type, mmu_idx, ra);
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probe_access(env, ptr + in_page, size - in_page,
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access_type, mmu_idx, ra);
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}
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}
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@ -232,6 +232,19 @@ static void gen_address_with_allocation_tag0(TCGv_i64 dst, TCGv_i64 src)
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tcg_gen_andi_i64(dst, src, ~MAKE_64BIT_MASK(56, 4));
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}
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static void gen_probe_access(DisasContext *s, TCGv_i64 ptr,
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MMUAccessType acc, int log2_size)
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{
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TCGv_i32 t_acc = tcg_const_i32(acc);
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TCGv_i32 t_idx = tcg_const_i32(get_mem_index(s));
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TCGv_i32 t_size = tcg_const_i32(1 << log2_size);
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gen_helper_probe_access(cpu_env, ptr, t_acc, t_idx, t_size);
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tcg_temp_free_i32(t_acc);
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tcg_temp_free_i32(t_idx);
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tcg_temp_free_i32(t_size);
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}
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typedef struct DisasCompare64 {
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TCGCond cond;
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TCGv_i64 value;
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@ -3685,6 +3698,154 @@ static void disas_ldst_single_struct(DisasContext *s, uint32_t insn)
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}
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}
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/*
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* Load/Store memory tags
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*
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* 31 30 29 24 22 21 12 10 5 0
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* +-----+-------------+-----+---+------+-----+------+------+
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* | 1 1 | 0 1 1 0 0 1 | op1 | 1 | imm9 | op2 | Rn | Rt |
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* +-----+-------------+-----+---+------+-----+------+------+
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*/
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static void disas_ldst_tag(DisasContext *s, uint32_t insn)
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{
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int rt = extract32(insn, 0, 5);
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int rn = extract32(insn, 5, 5);
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uint64_t offset = sextract64(insn, 12, 9) << LOG2_TAG_GRANULE;
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int op2 = extract32(insn, 10, 2);
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int op1 = extract32(insn, 22, 2);
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bool is_load = false, is_pair = false, is_zero = false;
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int index = 0;
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TCGv_i64 addr, clean_addr, tcg_rt;
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/* We checked insn bits [29:24,21] in the caller. */
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if (extract32(insn, 30, 2) != 3) {
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goto do_unallocated;
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}
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/*
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* @index is a tri-state variable which has 3 states:
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* < 0 : post-index, writeback
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* = 0 : signed offset
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* > 0 : pre-index, writeback
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*/
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switch (op1) {
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case 0:
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if (op2 != 0) {
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/* STG */
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index = op2 - 2;
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break;
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}
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goto do_unallocated;
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case 1:
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if (op2 != 0) {
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/* STZG */
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is_zero = true;
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index = op2 - 2;
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} else {
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/* LDG */
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is_load = true;
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}
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break;
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case 2:
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if (op2 != 0) {
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/* ST2G */
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is_pair = true;
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index = op2 - 2;
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break;
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}
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goto do_unallocated;
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case 3:
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if (op2 != 0) {
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/* STZ2G */
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is_pair = is_zero = true;
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index = op2 - 2;
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break;
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}
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goto do_unallocated;
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default:
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do_unallocated:
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unallocated_encoding(s);
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return;
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}
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if (!dc_isar_feature(aa64_mte_insn_reg, s)) {
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goto do_unallocated;
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}
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if (rn == 31) {
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gen_check_sp_alignment(s);
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}
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addr = read_cpu_reg_sp(s, rn, true);
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if (index >= 0) {
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/* pre-index or signed offset */
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tcg_gen_addi_i64(addr, addr, offset);
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}
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if (is_load) {
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tcg_gen_andi_i64(addr, addr, -TAG_GRANULE);
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tcg_rt = cpu_reg(s, rt);
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if (s->ata) {
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gen_helper_ldg(tcg_rt, cpu_env, addr, tcg_rt);
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} else {
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clean_addr = clean_data_tbi(s, addr);
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gen_probe_access(s, clean_addr, MMU_DATA_LOAD, MO_8);
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gen_address_with_allocation_tag0(tcg_rt, addr);
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}
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} else {
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tcg_rt = cpu_reg_sp(s, rt);
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if (!s->ata) {
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/*
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* For STG and ST2G, we need to check alignment and probe memory.
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* TODO: For STZG and STZ2G, we could rely on the stores below,
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* at least for system mode; user-only won't enforce alignment.
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*/
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if (is_pair) {
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gen_helper_st2g_stub(cpu_env, addr);
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} else {
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gen_helper_stg_stub(cpu_env, addr);
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}
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} else if (tb_cflags(s->base.tb) & CF_PARALLEL) {
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if (is_pair) {
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gen_helper_st2g_parallel(cpu_env, addr, tcg_rt);
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} else {
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gen_helper_stg_parallel(cpu_env, addr, tcg_rt);
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}
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} else {
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if (is_pair) {
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gen_helper_st2g(cpu_env, addr, tcg_rt);
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} else {
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gen_helper_stg(cpu_env, addr, tcg_rt);
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}
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}
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}
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if (is_zero) {
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TCGv_i64 clean_addr = clean_data_tbi(s, addr);
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TCGv_i64 tcg_zero = tcg_const_i64(0);
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int mem_index = get_mem_index(s);
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int i, n = (1 + is_pair) << LOG2_TAG_GRANULE;
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tcg_gen_qemu_st_i64(tcg_zero, clean_addr, mem_index,
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MO_Q | MO_ALIGN_16);
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for (i = 8; i < n; i += 8) {
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tcg_gen_addi_i64(clean_addr, clean_addr, 8);
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tcg_gen_qemu_st_i64(tcg_zero, clean_addr, mem_index, MO_Q);
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}
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tcg_temp_free_i64(tcg_zero);
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}
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if (index != 0) {
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/* pre-index or post-index */
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if (index < 0) {
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/* post-index */
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tcg_gen_addi_i64(addr, addr, offset);
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}
|
||||
tcg_gen_mov_i64(cpu_reg_sp(s, rn), addr);
|
||||
}
|
||||
}
|
||||
|
||||
/* Loads and stores */
|
||||
static void disas_ldst(DisasContext *s, uint32_t insn)
|
||||
{
|
||||
@ -3709,13 +3870,14 @@ static void disas_ldst(DisasContext *s, uint32_t insn)
|
||||
case 0x0d: /* AdvSIMD load/store single structure */
|
||||
disas_ldst_single_struct(s, insn);
|
||||
break;
|
||||
case 0x19: /* LDAPR/STLR (unscaled immediate) */
|
||||
if (extract32(insn, 10, 2) != 0 ||
|
||||
extract32(insn, 21, 1) != 0) {
|
||||
case 0x19:
|
||||
if (extract32(insn, 21, 1) != 0) {
|
||||
disas_ldst_tag(s, insn);
|
||||
} else if (extract32(insn, 10, 2) == 0) {
|
||||
disas_ldst_ldapr_stlr(s, insn);
|
||||
} else {
|
||||
unallocated_encoding(s);
|
||||
break;
|
||||
}
|
||||
disas_ldst_ldapr_stlr(s, insn);
|
||||
break;
|
||||
default:
|
||||
unallocated_encoding(s);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user