force IOPL=3
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@257 c046a42c-6fe2-441c-8c8c-71466251a162
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@ -73,17 +73,17 @@ void save_v86_state(CPUX86State *env)
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ts->target_v86->regs.ebp = tswap32(env->regs[R_EBP]);
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ts->target_v86->regs.esp = tswap32(env->regs[R_ESP]);
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ts->target_v86->regs.eip = tswap32(env->eip);
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ts->target_v86->regs.cs = tswap16(env->segs[R_CS]);
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ts->target_v86->regs.ss = tswap16(env->segs[R_SS]);
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ts->target_v86->regs.ds = tswap16(env->segs[R_DS]);
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ts->target_v86->regs.es = tswap16(env->segs[R_ES]);
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ts->target_v86->regs.fs = tswap16(env->segs[R_FS]);
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ts->target_v86->regs.gs = tswap16(env->segs[R_GS]);
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ts->target_v86->regs.cs = tswap16(env->segs[R_CS].selector);
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ts->target_v86->regs.ss = tswap16(env->segs[R_SS].selector);
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ts->target_v86->regs.ds = tswap16(env->segs[R_DS].selector);
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ts->target_v86->regs.es = tswap16(env->segs[R_ES].selector);
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ts->target_v86->regs.fs = tswap16(env->segs[R_FS].selector);
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ts->target_v86->regs.gs = tswap16(env->segs[R_GS].selector);
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set_flags(env->eflags, ts->v86flags, VIF_MASK | ts->v86mask);
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ts->target_v86->regs.eflags = tswap32(env->eflags);
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#ifdef DEBUG_VM86
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fprintf(logfile, "save_v86_state: eflags=%08x cs:ip=%04x:%04x\n",
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env->eflags, env->segs[R_CS], env->eip);
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env->eflags, env->segs[R_CS].selector, env->eip);
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#endif
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/* restore 32 bit registers */
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@ -180,6 +180,7 @@ static inline unsigned int get_vflags(CPUX86State *env)
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flags = env->eflags & RETURN_MASK;
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if (ts->v86flags & VIF_MASK)
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flags |= IF_MASK;
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flags |= IOPL_MASK;
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return flags | (ts->v86flags & ts->v86mask);
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}
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@ -194,7 +195,7 @@ static void do_int(CPUX86State *env, int intno)
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uint8_t *ssp;
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unsigned int sp;
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if (env->segs[R_CS] == TARGET_BIOSSEG)
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if (env->segs[R_CS].selector == TARGET_BIOSSEG)
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goto cannot_handle;
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if (is_revectored(intno, &ts->vm86plus.int_revectored))
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goto cannot_handle;
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@ -210,10 +211,10 @@ static void do_int(CPUX86State *env, int intno)
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intno, segoffs >> 16, segoffs & 0xffff);
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#endif
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/* save old state */
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ssp = (uint8_t *)(env->segs[R_SS] << 4);
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ssp = (uint8_t *)(env->segs[R_SS].selector << 4);
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sp = env->regs[R_ESP] & 0xffff;
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vm_putw(ssp, sp - 2, get_vflags(env));
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vm_putw(ssp, sp - 4, env->segs[R_CS]);
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vm_putw(ssp, sp - 4, env->segs[R_CS].selector);
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vm_putw(ssp, sp - 6, env->eip);
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ADD16(env->regs[R_ESP], -6);
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/* goto interrupt handler */
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@ -257,16 +258,16 @@ void handle_vm86_fault(CPUX86State *env)
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unsigned int ip, sp, newflags, newip, newcs, opcode, intno;
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int data32, pref_done;
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csp = (uint8_t *)(env->segs[R_CS] << 4);
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csp = (uint8_t *)(env->segs[R_CS].selector << 4);
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ip = env->eip & 0xffff;
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pc = csp + ip;
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ssp = (uint8_t *)(env->segs[R_SS] << 4);
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ssp = (uint8_t *)(env->segs[R_SS].selector << 4);
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sp = env->regs[R_ESP] & 0xffff;
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#if defined(DEBUG_VM86)
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fprintf(logfile, "VM86 exception %04x:%08x %02x %02x\n",
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env->segs[R_CS], env->eip, pc[0], pc[1]);
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env->segs[R_CS].selector, env->eip, pc[0], pc[1]);
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#endif
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data32 = 0;
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@ -413,12 +414,12 @@ int do_vm86(CPUX86State *env, long subfunction,
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ts->vm86_saved_regs.esp = env->regs[R_ESP];
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ts->vm86_saved_regs.eflags = env->eflags;
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ts->vm86_saved_regs.eip = env->eip;
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ts->vm86_saved_regs.cs = env->segs[R_CS];
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ts->vm86_saved_regs.ss = env->segs[R_SS];
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ts->vm86_saved_regs.ds = env->segs[R_DS];
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ts->vm86_saved_regs.es = env->segs[R_ES];
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ts->vm86_saved_regs.fs = env->segs[R_FS];
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ts->vm86_saved_regs.gs = env->segs[R_GS];
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ts->vm86_saved_regs.cs = env->segs[R_CS].selector;
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ts->vm86_saved_regs.ss = env->segs[R_SS].selector;
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ts->vm86_saved_regs.ds = env->segs[R_DS].selector;
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ts->vm86_saved_regs.es = env->segs[R_ES].selector;
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ts->vm86_saved_regs.fs = env->segs[R_FS].selector;
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ts->vm86_saved_regs.gs = env->segs[R_GS].selector;
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/* build vm86 CPU state */
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ts->v86flags = tswap32(target_v86->regs.eflags);
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@ -466,7 +467,8 @@ int do_vm86(CPUX86State *env, long subfunction,
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target_v86->vm86plus.vm86dbg_intxxtab, 32);
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#ifdef DEBUG_VM86
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fprintf(logfile, "do_vm86: cs:ip=%04x:%04x\n", env->segs[R_CS], env->eip);
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fprintf(logfile, "do_vm86: cs:ip=%04x:%04x\n",
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env->segs[R_CS].selector, env->eip);
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#endif
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/* now the virtual CPU is ready for vm86 execution ! */
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out:
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