tcg/ppc: Implement field extraction opcodes
Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Richard Henderson <rth@twiddle.net>
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@ -69,7 +69,7 @@ typedef enum {
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#define TCG_TARGET_HAS_nand_i32 1
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#define TCG_TARGET_HAS_nor_i32 1
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#define TCG_TARGET_HAS_deposit_i32 1
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#define TCG_TARGET_HAS_extract_i32 0
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#define TCG_TARGET_HAS_extract_i32 1
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#define TCG_TARGET_HAS_sextract_i32 0
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#define TCG_TARGET_HAS_movcond_i32 1
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#define TCG_TARGET_HAS_mulu2_i32 0
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@ -102,7 +102,7 @@ typedef enum {
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#define TCG_TARGET_HAS_nand_i64 1
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#define TCG_TARGET_HAS_nor_i64 1
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#define TCG_TARGET_HAS_deposit_i64 1
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#define TCG_TARGET_HAS_extract_i64 0
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#define TCG_TARGET_HAS_extract_i64 1
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#define TCG_TARGET_HAS_sextract_i64 0
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#define TCG_TARGET_HAS_movcond_i64 1
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#define TCG_TARGET_HAS_add2_i64 1
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@ -2396,6 +2396,14 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
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}
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break;
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case INDEX_op_extract_i32:
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tcg_out_rlw(s, RLWINM, args[0], args[1],
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32 - args[2], 32 - args[3], 31);
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break;
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case INDEX_op_extract_i64:
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tcg_out_rld(s, RLDICL, args[0], args[1], 64 - args[2], 64 - args[3]);
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break;
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case INDEX_op_movcond_i32:
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tcg_out_movcond(s, TCG_TYPE_I32, args[5], args[0], args[1], args[2],
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args[3], args[4], const_args[2]);
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@ -2530,6 +2538,7 @@ static const TCGTargetOpDef ppc_op_defs[] = {
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{ INDEX_op_movcond_i32, { "r", "r", "ri", "rZ", "rZ" } },
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{ INDEX_op_deposit_i32, { "r", "0", "rZ" } },
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{ INDEX_op_extract_i32, { "r", "r" } },
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{ INDEX_op_muluh_i32, { "r", "r", "r" } },
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{ INDEX_op_mulsh_i32, { "r", "r", "r" } },
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@ -2585,6 +2594,7 @@ static const TCGTargetOpDef ppc_op_defs[] = {
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{ INDEX_op_movcond_i64, { "r", "r", "ri", "rZ", "rZ" } },
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{ INDEX_op_deposit_i64, { "r", "0", "rZ" } },
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{ INDEX_op_extract_i64, { "r", "r" } },
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{ INDEX_op_mulsh_i64, { "r", "r", "r" } },
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{ INDEX_op_muluh_i64, { "r", "r", "r" } },
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