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tcg/s390x: Use tgen_movcond_int in tgen_clz 

Reuse code from movcond to conditionally copy a2 to dest,
based on the condition codes produced by FLOGR.

Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2022-02-24 03:03:20 +00:00
parent 0bbf0f7acf
commit bfff851842
2 changed files with 12 additions and 9 deletions
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1
tcg/s390x/tcg-target-con-set.h
View File

@ -24,6 +24,7 @@ C_O1_I2(r, 0, rI)
C_O1_I2(r, 0, rJ)
C_O1_I2(r, r, r)
C_O1_I2(r, r, ri)
C_O1_I2(r, r, rI)
C_O1_I2(r, r, rJ)
C_O1_I2(r, r, rK)
C_O1_I2(r, r, rKR)

20
tcg/s390x/tcg-target.c.inc
View File

@ -1424,15 +1424,15 @@ static void tgen_clz(TCGContext *s, TCGReg dest, TCGReg a1,
if (a2const && a2 == 64) {
tcg_out_mov(s, TCG_TYPE_I64, dest, TCG_REG_R0);
} else {
if (a2const) {
tcg_out_movi(s, TCG_TYPE_I64, dest, a2);
} else {
tcg_out_mov(s, TCG_TYPE_I64, dest, a2);
}
/* Emit: if (one bit found) dest = r0. */
tcg_out_insn(s, RRFc, LOCGR, dest, TCG_REG_R0, 2);
return;
}
/*
* Conditions from FLOGR are:
* 2 -> one bit found
* 8 -> no one bit found
*/
tgen_movcond_int(s, TCG_TYPE_I64, dest, a2, a2const, TCG_REG_R0, 8, 2);
}
static void tgen_deposit(TCGContext *s, TCGReg dest, TCGReg src,
@ -3070,11 +3070,13 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
case INDEX_op_rotl_i64:
case INDEX_op_rotr_i32:
case INDEX_op_rotr_i64:
case INDEX_op_clz_i64:
case INDEX_op_setcond_i32:
case INDEX_op_setcond_i64:
return C_O1_I2(r, r, ri);
case INDEX_op_clz_i64:
return C_O1_I2(r, r, rI);
case INDEX_op_sub_i32:
case INDEX_op_sub_i64:
case INDEX_op_and_i32: