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target/riscv: Extend pc for runtime pc write

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In some cases, we must restore the guest PC to the address of the start of
the TB, such as when the instruction counter hits zero. So extend pc register
according to current xlen for these cases.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-8-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
LIU Zhiwei 2022-01-20 20:20:34 +08:00 committed by Alistair Francis
parent 8c796f1a15
commit bf9e776ec1
1 changed files with 19 additions and 3 deletions
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22
target/riscv/cpu.c
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@ -355,7 +355,12 @@ static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
{
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
env->pc = value;
if (env->xl == MXL_RV32) {
env->pc = (int32_t)value;
} else {
env->pc = value;
}
}
static void riscv_cpu_synchronize_from_tb(CPUState *cs,
@ -363,7 +368,13 @@ static void riscv_cpu_synchronize_from_tb(CPUState *cs,
{
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
env->pc = tb->pc;
RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
if (xl == MXL_RV32) {
env->pc = (int32_t)tb->pc;
} else {
env->pc = tb->pc;
}
}
static bool riscv_cpu_has_work(CPUState *cs)
@ -384,7 +395,12 @@ static bool riscv_cpu_has_work(CPUState *cs)
void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb,
target_ulong *data)
{
env->pc = data[0];
RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
if (xl == MXL_RV32) {
env->pc = (int32_t)data[0];
} else {
env->pc = data[0];
}
}
static void riscv_cpu_reset(DeviceState *dev)