monitor: remove target-specific code from monitor.c
Move target-specific code out of /monitor.c to /target-*/monitor.c, this will avoid code cluttering and using random ifdeffery. The solution is quite simple, but solves the issue of the separation of target-specific code from monitor. Signed-off-by: Pavel Butsykin <pbutsykin@virtuozzo.com> Signed-off-by: Denis V. Lunev <den@openvz.org> CC: Paolo Bonzini <pbonzini@redhat.com> CC: Peter Maydell <peter.maydell@linaro.org> Message-Id: <1441899541-1856-3-git-send-email-den@openvz.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Pavel Butsykin
Paolo Bonzini
parent
da76ee76f7
commit
bf95728400
45
include/monitor/hmp-target.h
Normal file
45
include/monitor/hmp-target.h
Normal file
@ -0,0 +1,45 @@
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/*
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* QEMU monitor
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*
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* Copyright (c) 2003-2004 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef MONITOR_COMMON_H
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#define MONITOR_COMMON_H
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#define MD_TLONG 0
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#define MD_I32 1
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struct MonitorDef {
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const char *name;
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int offset;
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target_long (*get_value)(const struct MonitorDef *md, int val);
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int type;
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};
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const MonitorDef *target_monitor_defs(void);
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CPUArchState *mon_get_cpu_env(void);
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void hmp_info_mem(Monitor *mon, const QDict *qdict);
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void hmp_info_tlb(Monitor *mon, const QDict *qdict);
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void hmp_mce(Monitor *mon, const QDict *qdict);
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#endif /* MONITOR_COMMON */
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@ -80,5 +80,6 @@ typedef struct SSIBus SSIBus;
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typedef struct uWireSlave uWireSlave;
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typedef struct uWireSlave uWireSlave;
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typedef struct VirtIODevice VirtIODevice;
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typedef struct VirtIODevice VirtIODevice;
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typedef struct Visitor Visitor;
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typedef struct Visitor Visitor;
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typedef struct MonitorDef MonitorDef;
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#endif /* QEMU_TYPEDEFS_H */
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#endif /* QEMU_TYPEDEFS_H */
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860
monitor.c
860
monitor.c
@ -63,6 +63,7 @@
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#include "cpu.h"
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#include "cpu.h"
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#include "trace.h"
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#include "trace.h"
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#include "trace/control.h"
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#include "trace/control.h"
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#include "monitor/hmp-target.h"
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#ifdef CONFIG_TRACE_SIMPLE
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#ifdef CONFIG_TRACE_SIMPLE
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#include "trace/simple.h"
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#include "trace/simple.h"
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#endif
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#endif
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@ -950,7 +951,7 @@ static CPUState *mon_get_cpu(void)
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return cur_mon->mon_cpu;
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return cur_mon->mon_cpu;
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}
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}
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static CPUArchState *mon_get_cpu_env(void)
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CPUArchState *mon_get_cpu_env(void)
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{
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{
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return mon_get_cpu()->env_ptr;
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return mon_get_cpu()->env_ptr;
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}
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}
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@ -1424,442 +1425,6 @@ static void hmp_boot_set(Monitor *mon, const QDict *qdict)
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}
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}
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}
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}
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#if defined(TARGET_I386)
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static void print_pte(Monitor *mon, hwaddr addr,
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hwaddr pte,
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hwaddr mask)
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{
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#ifdef TARGET_X86_64
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if (addr & (1ULL << 47)) {
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addr |= -1LL << 48;
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}
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#endif
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monitor_printf(mon, TARGET_FMT_plx ": " TARGET_FMT_plx
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" %c%c%c%c%c%c%c%c%c\n",
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addr,
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pte & mask,
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pte & PG_NX_MASK ? 'X' : '-',
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pte & PG_GLOBAL_MASK ? 'G' : '-',
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pte & PG_PSE_MASK ? 'P' : '-',
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pte & PG_DIRTY_MASK ? 'D' : '-',
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pte & PG_ACCESSED_MASK ? 'A' : '-',
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pte & PG_PCD_MASK ? 'C' : '-',
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pte & PG_PWT_MASK ? 'T' : '-',
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pte & PG_USER_MASK ? 'U' : '-',
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pte & PG_RW_MASK ? 'W' : '-');
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}
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static void tlb_info_32(Monitor *mon, CPUArchState *env)
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{
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unsigned int l1, l2;
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uint32_t pgd, pde, pte;
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pgd = env->cr[3] & ~0xfff;
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for(l1 = 0; l1 < 1024; l1++) {
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cpu_physical_memory_read(pgd + l1 * 4, &pde, 4);
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pde = le32_to_cpu(pde);
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if (pde & PG_PRESENT_MASK) {
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if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) {
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/* 4M pages */
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print_pte(mon, (l1 << 22), pde, ~((1 << 21) - 1));
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} else {
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for(l2 = 0; l2 < 1024; l2++) {
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cpu_physical_memory_read((pde & ~0xfff) + l2 * 4, &pte, 4);
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pte = le32_to_cpu(pte);
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if (pte & PG_PRESENT_MASK) {
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print_pte(mon, (l1 << 22) + (l2 << 12),
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pte & ~PG_PSE_MASK,
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~0xfff);
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}
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}
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}
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}
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}
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}
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static void tlb_info_pae32(Monitor *mon, CPUArchState *env)
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{
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unsigned int l1, l2, l3;
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uint64_t pdpe, pde, pte;
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uint64_t pdp_addr, pd_addr, pt_addr;
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pdp_addr = env->cr[3] & ~0x1f;
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for (l1 = 0; l1 < 4; l1++) {
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cpu_physical_memory_read(pdp_addr + l1 * 8, &pdpe, 8);
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pdpe = le64_to_cpu(pdpe);
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if (pdpe & PG_PRESENT_MASK) {
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pd_addr = pdpe & 0x3fffffffff000ULL;
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for (l2 = 0; l2 < 512; l2++) {
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cpu_physical_memory_read(pd_addr + l2 * 8, &pde, 8);
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pde = le64_to_cpu(pde);
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if (pde & PG_PRESENT_MASK) {
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if (pde & PG_PSE_MASK) {
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/* 2M pages with PAE, CR4.PSE is ignored */
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print_pte(mon, (l1 << 30 ) + (l2 << 21), pde,
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~((hwaddr)(1 << 20) - 1));
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} else {
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pt_addr = pde & 0x3fffffffff000ULL;
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for (l3 = 0; l3 < 512; l3++) {
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cpu_physical_memory_read(pt_addr + l3 * 8, &pte, 8);
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pte = le64_to_cpu(pte);
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if (pte & PG_PRESENT_MASK) {
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print_pte(mon, (l1 << 30 ) + (l2 << 21)
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+ (l3 << 12),
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pte & ~PG_PSE_MASK,
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~(hwaddr)0xfff);
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}
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}
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}
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}
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}
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}
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}
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}
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#ifdef TARGET_X86_64
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static void tlb_info_64(Monitor *mon, CPUArchState *env)
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{
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uint64_t l1, l2, l3, l4;
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uint64_t pml4e, pdpe, pde, pte;
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uint64_t pml4_addr, pdp_addr, pd_addr, pt_addr;
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pml4_addr = env->cr[3] & 0x3fffffffff000ULL;
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for (l1 = 0; l1 < 512; l1++) {
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cpu_physical_memory_read(pml4_addr + l1 * 8, &pml4e, 8);
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pml4e = le64_to_cpu(pml4e);
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if (pml4e & PG_PRESENT_MASK) {
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pdp_addr = pml4e & 0x3fffffffff000ULL;
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for (l2 = 0; l2 < 512; l2++) {
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cpu_physical_memory_read(pdp_addr + l2 * 8, &pdpe, 8);
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pdpe = le64_to_cpu(pdpe);
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if (pdpe & PG_PRESENT_MASK) {
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if (pdpe & PG_PSE_MASK) {
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/* 1G pages, CR4.PSE is ignored */
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print_pte(mon, (l1 << 39) + (l2 << 30), pdpe,
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0x3ffffc0000000ULL);
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} else {
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pd_addr = pdpe & 0x3fffffffff000ULL;
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for (l3 = 0; l3 < 512; l3++) {
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cpu_physical_memory_read(pd_addr + l3 * 8, &pde, 8);
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pde = le64_to_cpu(pde);
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if (pde & PG_PRESENT_MASK) {
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if (pde & PG_PSE_MASK) {
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/* 2M pages, CR4.PSE is ignored */
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print_pte(mon, (l1 << 39) + (l2 << 30) +
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(l3 << 21), pde,
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0x3ffffffe00000ULL);
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} else {
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pt_addr = pde & 0x3fffffffff000ULL;
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for (l4 = 0; l4 < 512; l4++) {
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cpu_physical_memory_read(pt_addr
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+ l4 * 8,
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&pte, 8);
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pte = le64_to_cpu(pte);
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if (pte & PG_PRESENT_MASK) {
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print_pte(mon, (l1 << 39) +
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(l2 << 30) +
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(l3 << 21) + (l4 << 12),
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pte & ~PG_PSE_MASK,
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0x3fffffffff000ULL);
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}
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}
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}
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}
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}
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}
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}
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}
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}
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}
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}
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#endif
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static void hmp_info_tlb(Monitor *mon, const QDict *qdict)
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{
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CPUArchState *env;
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env = mon_get_cpu_env();
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if (!(env->cr[0] & CR0_PG_MASK)) {
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monitor_printf(mon, "PG disabled\n");
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return;
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}
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if (env->cr[4] & CR4_PAE_MASK) {
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#ifdef TARGET_X86_64
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if (env->hflags & HF_LMA_MASK) {
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tlb_info_64(mon, env);
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} else
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#endif
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{
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tlb_info_pae32(mon, env);
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}
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} else {
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tlb_info_32(mon, env);
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}
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}
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static void mem_print(Monitor *mon, hwaddr *pstart,
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int *plast_prot,
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hwaddr end, int prot)
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{
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int prot1;
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prot1 = *plast_prot;
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if (prot != prot1) {
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if (*pstart != -1) {
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monitor_printf(mon, TARGET_FMT_plx "-" TARGET_FMT_plx " "
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TARGET_FMT_plx " %c%c%c\n",
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*pstart, end, end - *pstart,
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prot1 & PG_USER_MASK ? 'u' : '-',
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'r',
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prot1 & PG_RW_MASK ? 'w' : '-');
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}
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if (prot != 0)
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*pstart = end;
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else
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*pstart = -1;
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*plast_prot = prot;
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}
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}
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static void mem_info_32(Monitor *mon, CPUArchState *env)
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{
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unsigned int l1, l2;
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int prot, last_prot;
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uint32_t pgd, pde, pte;
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hwaddr start, end;
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pgd = env->cr[3] & ~0xfff;
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last_prot = 0;
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start = -1;
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for(l1 = 0; l1 < 1024; l1++) {
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cpu_physical_memory_read(pgd + l1 * 4, &pde, 4);
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pde = le32_to_cpu(pde);
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end = l1 << 22;
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if (pde & PG_PRESENT_MASK) {
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if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) {
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prot = pde & (PG_USER_MASK | PG_RW_MASK | PG_PRESENT_MASK);
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mem_print(mon, &start, &last_prot, end, prot);
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} else {
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for(l2 = 0; l2 < 1024; l2++) {
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cpu_physical_memory_read((pde & ~0xfff) + l2 * 4, &pte, 4);
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pte = le32_to_cpu(pte);
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end = (l1 << 22) + (l2 << 12);
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if (pte & PG_PRESENT_MASK) {
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prot = pte & pde &
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(PG_USER_MASK | PG_RW_MASK | PG_PRESENT_MASK);
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} else {
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prot = 0;
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}
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mem_print(mon, &start, &last_prot, end, prot);
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}
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}
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} else {
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prot = 0;
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mem_print(mon, &start, &last_prot, end, prot);
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}
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}
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/* Flush last range */
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mem_print(mon, &start, &last_prot, (hwaddr)1 << 32, 0);
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}
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static void mem_info_pae32(Monitor *mon, CPUArchState *env)
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{
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unsigned int l1, l2, l3;
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int prot, last_prot;
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uint64_t pdpe, pde, pte;
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uint64_t pdp_addr, pd_addr, pt_addr;
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hwaddr start, end;
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pdp_addr = env->cr[3] & ~0x1f;
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last_prot = 0;
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start = -1;
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for (l1 = 0; l1 < 4; l1++) {
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cpu_physical_memory_read(pdp_addr + l1 * 8, &pdpe, 8);
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pdpe = le64_to_cpu(pdpe);
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end = l1 << 30;
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if (pdpe & PG_PRESENT_MASK) {
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pd_addr = pdpe & 0x3fffffffff000ULL;
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for (l2 = 0; l2 < 512; l2++) {
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cpu_physical_memory_read(pd_addr + l2 * 8, &pde, 8);
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pde = le64_to_cpu(pde);
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end = (l1 << 30) + (l2 << 21);
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if (pde & PG_PRESENT_MASK) {
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if (pde & PG_PSE_MASK) {
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prot = pde & (PG_USER_MASK | PG_RW_MASK |
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PG_PRESENT_MASK);
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mem_print(mon, &start, &last_prot, end, prot);
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} else {
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pt_addr = pde & 0x3fffffffff000ULL;
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for (l3 = 0; l3 < 512; l3++) {
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|
||||||
cpu_physical_memory_read(pt_addr + l3 * 8, &pte, 8);
|
|
||||||
pte = le64_to_cpu(pte);
|
|
||||||
end = (l1 << 30) + (l2 << 21) + (l3 << 12);
|
|
||||||
if (pte & PG_PRESENT_MASK) {
|
|
||||||
prot = pte & pde & (PG_USER_MASK | PG_RW_MASK |
|
|
||||||
PG_PRESENT_MASK);
|
|
||||||
} else {
|
|
||||||
prot = 0;
|
|
||||||
}
|
|
||||||
mem_print(mon, &start, &last_prot, end, prot);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
} else {
|
|
||||||
prot = 0;
|
|
||||||
mem_print(mon, &start, &last_prot, end, prot);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
} else {
|
|
||||||
prot = 0;
|
|
||||||
mem_print(mon, &start, &last_prot, end, prot);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
/* Flush last range */
|
|
||||||
mem_print(mon, &start, &last_prot, (hwaddr)1 << 32, 0);
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
#ifdef TARGET_X86_64
|
|
||||||
static void mem_info_64(Monitor *mon, CPUArchState *env)
|
|
||||||
{
|
|
||||||
int prot, last_prot;
|
|
||||||
uint64_t l1, l2, l3, l4;
|
|
||||||
uint64_t pml4e, pdpe, pde, pte;
|
|
||||||
uint64_t pml4_addr, pdp_addr, pd_addr, pt_addr, start, end;
|
|
||||||
|
|
||||||
pml4_addr = env->cr[3] & 0x3fffffffff000ULL;
|
|
||||||
last_prot = 0;
|
|
||||||
start = -1;
|
|
||||||
for (l1 = 0; l1 < 512; l1++) {
|
|
||||||
cpu_physical_memory_read(pml4_addr + l1 * 8, &pml4e, 8);
|
|
||||||
pml4e = le64_to_cpu(pml4e);
|
|
||||||
end = l1 << 39;
|
|
||||||
if (pml4e & PG_PRESENT_MASK) {
|
|
||||||
pdp_addr = pml4e & 0x3fffffffff000ULL;
|
|
||||||
for (l2 = 0; l2 < 512; l2++) {
|
|
||||||
cpu_physical_memory_read(pdp_addr + l2 * 8, &pdpe, 8);
|
|
||||||
pdpe = le64_to_cpu(pdpe);
|
|
||||||
end = (l1 << 39) + (l2 << 30);
|
|
||||||
if (pdpe & PG_PRESENT_MASK) {
|
|
||||||
if (pdpe & PG_PSE_MASK) {
|
|
||||||
prot = pdpe & (PG_USER_MASK | PG_RW_MASK |
|
|
||||||
PG_PRESENT_MASK);
|
|
||||||
prot &= pml4e;
|
|
||||||
mem_print(mon, &start, &last_prot, end, prot);
|
|
||||||
} else {
|
|
||||||
pd_addr = pdpe & 0x3fffffffff000ULL;
|
|
||||||
for (l3 = 0; l3 < 512; l3++) {
|
|
||||||
cpu_physical_memory_read(pd_addr + l3 * 8, &pde, 8);
|
|
||||||
pde = le64_to_cpu(pde);
|
|
||||||
end = (l1 << 39) + (l2 << 30) + (l3 << 21);
|
|
||||||
if (pde & PG_PRESENT_MASK) {
|
|
||||||
if (pde & PG_PSE_MASK) {
|
|
||||||
prot = pde & (PG_USER_MASK | PG_RW_MASK |
|
|
||||||
PG_PRESENT_MASK);
|
|
||||||
prot &= pml4e & pdpe;
|
|
||||||
mem_print(mon, &start, &last_prot, end, prot);
|
|
||||||
} else {
|
|
||||||
pt_addr = pde & 0x3fffffffff000ULL;
|
|
||||||
for (l4 = 0; l4 < 512; l4++) {
|
|
||||||
cpu_physical_memory_read(pt_addr
|
|
||||||
+ l4 * 8,
|
|
||||||
&pte, 8);
|
|
||||||
pte = le64_to_cpu(pte);
|
|
||||||
end = (l1 << 39) + (l2 << 30) +
|
|
||||||
(l3 << 21) + (l4 << 12);
|
|
||||||
if (pte & PG_PRESENT_MASK) {
|
|
||||||
prot = pte & (PG_USER_MASK | PG_RW_MASK |
|
|
||||||
PG_PRESENT_MASK);
|
|
||||||
prot &= pml4e & pdpe & pde;
|
|
||||||
} else {
|
|
||||||
prot = 0;
|
|
||||||
}
|
|
||||||
mem_print(mon, &start, &last_prot, end, prot);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
} else {
|
|
||||||
prot = 0;
|
|
||||||
mem_print(mon, &start, &last_prot, end, prot);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
} else {
|
|
||||||
prot = 0;
|
|
||||||
mem_print(mon, &start, &last_prot, end, prot);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
} else {
|
|
||||||
prot = 0;
|
|
||||||
mem_print(mon, &start, &last_prot, end, prot);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
/* Flush last range */
|
|
||||||
mem_print(mon, &start, &last_prot, (hwaddr)1 << 48, 0);
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
static void hmp_info_mem(Monitor *mon, const QDict *qdict)
|
|
||||||
{
|
|
||||||
CPUArchState *env;
|
|
||||||
|
|
||||||
env = mon_get_cpu_env();
|
|
||||||
|
|
||||||
if (!(env->cr[0] & CR0_PG_MASK)) {
|
|
||||||
monitor_printf(mon, "PG disabled\n");
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
if (env->cr[4] & CR4_PAE_MASK) {
|
|
||||||
#ifdef TARGET_X86_64
|
|
||||||
if (env->hflags & HF_LMA_MASK) {
|
|
||||||
mem_info_64(mon, env);
|
|
||||||
} else
|
|
||||||
#endif
|
|
||||||
{
|
|
||||||
mem_info_pae32(mon, env);
|
|
||||||
}
|
|
||||||
} else {
|
|
||||||
mem_info_32(mon, env);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(TARGET_SH4)
|
|
||||||
|
|
||||||
static void print_tlb(Monitor *mon, int idx, tlb_t *tlb)
|
|
||||||
{
|
|
||||||
monitor_printf(mon, " tlb%i:\t"
|
|
||||||
"asid=%hhu vpn=%x\tppn=%x\tsz=%hhu size=%u\t"
|
|
||||||
"v=%hhu shared=%hhu cached=%hhu prot=%hhu "
|
|
||||||
"dirty=%hhu writethrough=%hhu\n",
|
|
||||||
idx,
|
|
||||||
tlb->asid, tlb->vpn, tlb->ppn, tlb->sz, tlb->size,
|
|
||||||
tlb->v, tlb->sh, tlb->c, tlb->pr,
|
|
||||||
tlb->d, tlb->wt);
|
|
||||||
}
|
|
||||||
|
|
||||||
static void hmp_info_tlb(Monitor *mon, const QDict *qdict)
|
|
||||||
{
|
|
||||||
CPUArchState *env = mon_get_cpu_env();
|
|
||||||
int i;
|
|
||||||
|
|
||||||
monitor_printf (mon, "ITLB:\n");
|
|
||||||
for (i = 0 ; i < ITLB_SIZE ; i++)
|
|
||||||
print_tlb (mon, i, &env->itlb[i]);
|
|
||||||
monitor_printf (mon, "UTLB:\n");
|
|
||||||
for (i = 0 ; i < UTLB_SIZE ; i++)
|
|
||||||
print_tlb (mon, i, &env->utlb[i]);
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(TARGET_SPARC) || defined(TARGET_PPC) || defined(TARGET_XTENSA)
|
|
||||||
static void hmp_info_tlb(Monitor *mon, const QDict *qdict)
|
|
||||||
{
|
|
||||||
CPUArchState *env1 = mon_get_cpu_env();
|
|
||||||
|
|
||||||
dump_mmu((FILE*)mon, (fprintf_function)monitor_printf, env1);
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
static void hmp_info_mtree(Monitor *mon, const QDict *qdict)
|
static void hmp_info_mtree(Monitor *mon, const QDict *qdict)
|
||||||
{
|
{
|
||||||
mtree_info((fprintf_function)monitor_printf, mon);
|
mtree_info((fprintf_function)monitor_printf, mon);
|
||||||
@ -2070,31 +1635,6 @@ static void hmp_acl_remove(Monitor *mon, const QDict *qdict)
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
#if defined(TARGET_I386)
|
|
||||||
static void hmp_mce(Monitor *mon, const QDict *qdict)
|
|
||||||
{
|
|
||||||
X86CPU *cpu;
|
|
||||||
CPUState *cs;
|
|
||||||
int cpu_index = qdict_get_int(qdict, "cpu_index");
|
|
||||||
int bank = qdict_get_int(qdict, "bank");
|
|
||||||
uint64_t status = qdict_get_int(qdict, "status");
|
|
||||||
uint64_t mcg_status = qdict_get_int(qdict, "mcg_status");
|
|
||||||
uint64_t addr = qdict_get_int(qdict, "addr");
|
|
||||||
uint64_t misc = qdict_get_int(qdict, "misc");
|
|
||||||
int flags = MCE_INJECT_UNCOND_AO;
|
|
||||||
|
|
||||||
if (qdict_get_try_bool(qdict, "broadcast", false)) {
|
|
||||||
flags |= MCE_INJECT_BROADCAST;
|
|
||||||
}
|
|
||||||
cs = qemu_get_cpu(cpu_index);
|
|
||||||
if (cs != NULL) {
|
|
||||||
cpu = X86_CPU(cs);
|
|
||||||
cpu_x86_inject_mce(mon, cpu, bank, status, mcg_status, addr, misc,
|
|
||||||
flags);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
void qmp_getfd(const char *fdname, Error **errp)
|
void qmp_getfd(const char *fdname, Error **errp)
|
||||||
{
|
{
|
||||||
mon_fd_t *monfd;
|
mon_fd_t *monfd;
|
||||||
@ -2533,394 +2073,6 @@ static const mon_cmd_t qmp_cmds[] = {
|
|||||||
static const char *pch;
|
static const char *pch;
|
||||||
static sigjmp_buf expr_env;
|
static sigjmp_buf expr_env;
|
||||||
|
|
||||||
#define MD_TLONG 0
|
|
||||||
#define MD_I32 1
|
|
||||||
|
|
||||||
typedef struct MonitorDef {
|
|
||||||
const char *name;
|
|
||||||
int offset;
|
|
||||||
target_long (*get_value)(const struct MonitorDef *md, int val);
|
|
||||||
int type;
|
|
||||||
} MonitorDef;
|
|
||||||
|
|
||||||
#if defined(TARGET_I386)
|
|
||||||
static target_long monitor_get_pc (const struct MonitorDef *md, int val)
|
|
||||||
{
|
|
||||||
CPUArchState *env = mon_get_cpu_env();
|
|
||||||
return env->eip + env->segs[R_CS].base;
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(TARGET_PPC)
|
|
||||||
static target_long monitor_get_ccr (const struct MonitorDef *md, int val)
|
|
||||||
{
|
|
||||||
CPUArchState *env = mon_get_cpu_env();
|
|
||||||
unsigned int u;
|
|
||||||
int i;
|
|
||||||
|
|
||||||
u = 0;
|
|
||||||
for (i = 0; i < 8; i++)
|
|
||||||
u |= env->crf[i] << (32 - (4 * (i + 1)));
|
|
||||||
|
|
||||||
return u;
|
|
||||||
}
|
|
||||||
|
|
||||||
static target_long monitor_get_msr (const struct MonitorDef *md, int val)
|
|
||||||
{
|
|
||||||
CPUArchState *env = mon_get_cpu_env();
|
|
||||||
return env->msr;
|
|
||||||
}
|
|
||||||
|
|
||||||
static target_long monitor_get_xer (const struct MonitorDef *md, int val)
|
|
||||||
{
|
|
||||||
CPUArchState *env = mon_get_cpu_env();
|
|
||||||
return env->xer;
|
|
||||||
}
|
|
||||||
|
|
||||||
static target_long monitor_get_decr (const struct MonitorDef *md, int val)
|
|
||||||
{
|
|
||||||
CPUArchState *env = mon_get_cpu_env();
|
|
||||||
return cpu_ppc_load_decr(env);
|
|
||||||
}
|
|
||||||
|
|
||||||
static target_long monitor_get_tbu (const struct MonitorDef *md, int val)
|
|
||||||
{
|
|
||||||
CPUArchState *env = mon_get_cpu_env();
|
|
||||||
return cpu_ppc_load_tbu(env);
|
|
||||||
}
|
|
||||||
|
|
||||||
static target_long monitor_get_tbl (const struct MonitorDef *md, int val)
|
|
||||||
{
|
|
||||||
CPUArchState *env = mon_get_cpu_env();
|
|
||||||
return cpu_ppc_load_tbl(env);
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#if defined(TARGET_SPARC)
|
|
||||||
#ifndef TARGET_SPARC64
|
|
||||||
static target_long monitor_get_psr (const struct MonitorDef *md, int val)
|
|
||||||
{
|
|
||||||
CPUArchState *env = mon_get_cpu_env();
|
|
||||||
|
|
||||||
return cpu_get_psr(env);
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
static target_long monitor_get_reg(const struct MonitorDef *md, int val)
|
|
||||||
{
|
|
||||||
CPUArchState *env = mon_get_cpu_env();
|
|
||||||
return env->regwptr[val];
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
static const MonitorDef monitor_defs[] = {
|
|
||||||
#ifdef TARGET_I386
|
|
||||||
|
|
||||||
#define SEG(name, seg) \
|
|
||||||
{ name, offsetof(CPUX86State, segs[seg].selector), NULL, MD_I32 },\
|
|
||||||
{ name ".base", offsetof(CPUX86State, segs[seg].base) },\
|
|
||||||
{ name ".limit", offsetof(CPUX86State, segs[seg].limit), NULL, MD_I32 },
|
|
||||||
|
|
||||||
{ "eax", offsetof(CPUX86State, regs[0]) },
|
|
||||||
{ "ecx", offsetof(CPUX86State, regs[1]) },
|
|
||||||
{ "edx", offsetof(CPUX86State, regs[2]) },
|
|
||||||
{ "ebx", offsetof(CPUX86State, regs[3]) },
|
|
||||||
{ "esp|sp", offsetof(CPUX86State, regs[4]) },
|
|
||||||
{ "ebp|fp", offsetof(CPUX86State, regs[5]) },
|
|
||||||
{ "esi", offsetof(CPUX86State, regs[6]) },
|
|
||||||
{ "edi", offsetof(CPUX86State, regs[7]) },
|
|
||||||
#ifdef TARGET_X86_64
|
|
||||||
{ "r8", offsetof(CPUX86State, regs[8]) },
|
|
||||||
{ "r9", offsetof(CPUX86State, regs[9]) },
|
|
||||||
{ "r10", offsetof(CPUX86State, regs[10]) },
|
|
||||||
{ "r11", offsetof(CPUX86State, regs[11]) },
|
|
||||||
{ "r12", offsetof(CPUX86State, regs[12]) },
|
|
||||||
{ "r13", offsetof(CPUX86State, regs[13]) },
|
|
||||||
{ "r14", offsetof(CPUX86State, regs[14]) },
|
|
||||||
{ "r15", offsetof(CPUX86State, regs[15]) },
|
|
||||||
#endif
|
|
||||||
{ "eflags", offsetof(CPUX86State, eflags) },
|
|
||||||
{ "eip", offsetof(CPUX86State, eip) },
|
|
||||||
SEG("cs", R_CS)
|
|
||||||
SEG("ds", R_DS)
|
|
||||||
SEG("es", R_ES)
|
|
||||||
SEG("ss", R_SS)
|
|
||||||
SEG("fs", R_FS)
|
|
||||||
SEG("gs", R_GS)
|
|
||||||
{ "pc", 0, monitor_get_pc, },
|
|
||||||
#elif defined(TARGET_PPC)
|
|
||||||
/* General purpose registers */
|
|
||||||
{ "r0", offsetof(CPUPPCState, gpr[0]) },
|
|
||||||
{ "r1", offsetof(CPUPPCState, gpr[1]) },
|
|
||||||
{ "r2", offsetof(CPUPPCState, gpr[2]) },
|
|
||||||
{ "r3", offsetof(CPUPPCState, gpr[3]) },
|
|
||||||
{ "r4", offsetof(CPUPPCState, gpr[4]) },
|
|
||||||
{ "r5", offsetof(CPUPPCState, gpr[5]) },
|
|
||||||
{ "r6", offsetof(CPUPPCState, gpr[6]) },
|
|
||||||
{ "r7", offsetof(CPUPPCState, gpr[7]) },
|
|
||||||
{ "r8", offsetof(CPUPPCState, gpr[8]) },
|
|
||||||
{ "r9", offsetof(CPUPPCState, gpr[9]) },
|
|
||||||
{ "r10", offsetof(CPUPPCState, gpr[10]) },
|
|
||||||
{ "r11", offsetof(CPUPPCState, gpr[11]) },
|
|
||||||
{ "r12", offsetof(CPUPPCState, gpr[12]) },
|
|
||||||
{ "r13", offsetof(CPUPPCState, gpr[13]) },
|
|
||||||
{ "r14", offsetof(CPUPPCState, gpr[14]) },
|
|
||||||
{ "r15", offsetof(CPUPPCState, gpr[15]) },
|
|
||||||
{ "r16", offsetof(CPUPPCState, gpr[16]) },
|
|
||||||
{ "r17", offsetof(CPUPPCState, gpr[17]) },
|
|
||||||
{ "r18", offsetof(CPUPPCState, gpr[18]) },
|
|
||||||
{ "r19", offsetof(CPUPPCState, gpr[19]) },
|
|
||||||
{ "r20", offsetof(CPUPPCState, gpr[20]) },
|
|
||||||
{ "r21", offsetof(CPUPPCState, gpr[21]) },
|
|
||||||
{ "r22", offsetof(CPUPPCState, gpr[22]) },
|
|
||||||
{ "r23", offsetof(CPUPPCState, gpr[23]) },
|
|
||||||
{ "r24", offsetof(CPUPPCState, gpr[24]) },
|
|
||||||
{ "r25", offsetof(CPUPPCState, gpr[25]) },
|
|
||||||
{ "r26", offsetof(CPUPPCState, gpr[26]) },
|
|
||||||
{ "r27", offsetof(CPUPPCState, gpr[27]) },
|
|
||||||
{ "r28", offsetof(CPUPPCState, gpr[28]) },
|
|
||||||
{ "r29", offsetof(CPUPPCState, gpr[29]) },
|
|
||||||
{ "r30", offsetof(CPUPPCState, gpr[30]) },
|
|
||||||
{ "r31", offsetof(CPUPPCState, gpr[31]) },
|
|
||||||
/* Floating point registers */
|
|
||||||
{ "f0", offsetof(CPUPPCState, fpr[0]) },
|
|
||||||
{ "f1", offsetof(CPUPPCState, fpr[1]) },
|
|
||||||
{ "f2", offsetof(CPUPPCState, fpr[2]) },
|
|
||||||
{ "f3", offsetof(CPUPPCState, fpr[3]) },
|
|
||||||
{ "f4", offsetof(CPUPPCState, fpr[4]) },
|
|
||||||
{ "f5", offsetof(CPUPPCState, fpr[5]) },
|
|
||||||
{ "f6", offsetof(CPUPPCState, fpr[6]) },
|
|
||||||
{ "f7", offsetof(CPUPPCState, fpr[7]) },
|
|
||||||
{ "f8", offsetof(CPUPPCState, fpr[8]) },
|
|
||||||
{ "f9", offsetof(CPUPPCState, fpr[9]) },
|
|
||||||
{ "f10", offsetof(CPUPPCState, fpr[10]) },
|
|
||||||
{ "f11", offsetof(CPUPPCState, fpr[11]) },
|
|
||||||
{ "f12", offsetof(CPUPPCState, fpr[12]) },
|
|
||||||
{ "f13", offsetof(CPUPPCState, fpr[13]) },
|
|
||||||
{ "f14", offsetof(CPUPPCState, fpr[14]) },
|
|
||||||
{ "f15", offsetof(CPUPPCState, fpr[15]) },
|
|
||||||
{ "f16", offsetof(CPUPPCState, fpr[16]) },
|
|
||||||
{ "f17", offsetof(CPUPPCState, fpr[17]) },
|
|
||||||
{ "f18", offsetof(CPUPPCState, fpr[18]) },
|
|
||||||
{ "f19", offsetof(CPUPPCState, fpr[19]) },
|
|
||||||
{ "f20", offsetof(CPUPPCState, fpr[20]) },
|
|
||||||
{ "f21", offsetof(CPUPPCState, fpr[21]) },
|
|
||||||
{ "f22", offsetof(CPUPPCState, fpr[22]) },
|
|
||||||
{ "f23", offsetof(CPUPPCState, fpr[23]) },
|
|
||||||
{ "f24", offsetof(CPUPPCState, fpr[24]) },
|
|
||||||
{ "f25", offsetof(CPUPPCState, fpr[25]) },
|
|
||||||
{ "f26", offsetof(CPUPPCState, fpr[26]) },
|
|
||||||
{ "f27", offsetof(CPUPPCState, fpr[27]) },
|
|
||||||
{ "f28", offsetof(CPUPPCState, fpr[28]) },
|
|
||||||
{ "f29", offsetof(CPUPPCState, fpr[29]) },
|
|
||||||
{ "f30", offsetof(CPUPPCState, fpr[30]) },
|
|
||||||
{ "f31", offsetof(CPUPPCState, fpr[31]) },
|
|
||||||
{ "fpscr", offsetof(CPUPPCState, fpscr) },
|
|
||||||
/* Next instruction pointer */
|
|
||||||
{ "nip|pc", offsetof(CPUPPCState, nip) },
|
|
||||||
{ "lr", offsetof(CPUPPCState, lr) },
|
|
||||||
{ "ctr", offsetof(CPUPPCState, ctr) },
|
|
||||||
{ "decr", 0, &monitor_get_decr, },
|
|
||||||
{ "ccr", 0, &monitor_get_ccr, },
|
|
||||||
/* Machine state register */
|
|
||||||
{ "msr", 0, &monitor_get_msr, },
|
|
||||||
{ "xer", 0, &monitor_get_xer, },
|
|
||||||
{ "tbu", 0, &monitor_get_tbu, },
|
|
||||||
{ "tbl", 0, &monitor_get_tbl, },
|
|
||||||
/* Segment registers */
|
|
||||||
{ "sdr1", offsetof(CPUPPCState, spr[SPR_SDR1]) },
|
|
||||||
{ "sr0", offsetof(CPUPPCState, sr[0]) },
|
|
||||||
{ "sr1", offsetof(CPUPPCState, sr[1]) },
|
|
||||||
{ "sr2", offsetof(CPUPPCState, sr[2]) },
|
|
||||||
{ "sr3", offsetof(CPUPPCState, sr[3]) },
|
|
||||||
{ "sr4", offsetof(CPUPPCState, sr[4]) },
|
|
||||||
{ "sr5", offsetof(CPUPPCState, sr[5]) },
|
|
||||||
{ "sr6", offsetof(CPUPPCState, sr[6]) },
|
|
||||||
{ "sr7", offsetof(CPUPPCState, sr[7]) },
|
|
||||||
{ "sr8", offsetof(CPUPPCState, sr[8]) },
|
|
||||||
{ "sr9", offsetof(CPUPPCState, sr[9]) },
|
|
||||||
{ "sr10", offsetof(CPUPPCState, sr[10]) },
|
|
||||||
{ "sr11", offsetof(CPUPPCState, sr[11]) },
|
|
||||||
{ "sr12", offsetof(CPUPPCState, sr[12]) },
|
|
||||||
{ "sr13", offsetof(CPUPPCState, sr[13]) },
|
|
||||||
{ "sr14", offsetof(CPUPPCState, sr[14]) },
|
|
||||||
{ "sr15", offsetof(CPUPPCState, sr[15]) },
|
|
||||||
/* Too lazy to put BATs... */
|
|
||||||
{ "pvr", offsetof(CPUPPCState, spr[SPR_PVR]) },
|
|
||||||
|
|
||||||
{ "srr0", offsetof(CPUPPCState, spr[SPR_SRR0]) },
|
|
||||||
{ "srr1", offsetof(CPUPPCState, spr[SPR_SRR1]) },
|
|
||||||
{ "dar", offsetof(CPUPPCState, spr[SPR_DAR]) },
|
|
||||||
{ "dsisr", offsetof(CPUPPCState, spr[SPR_DSISR]) },
|
|
||||||
{ "cfar", offsetof(CPUPPCState, spr[SPR_CFAR]) },
|
|
||||||
{ "sprg0", offsetof(CPUPPCState, spr[SPR_SPRG0]) },
|
|
||||||
{ "sprg1", offsetof(CPUPPCState, spr[SPR_SPRG1]) },
|
|
||||||
{ "sprg2", offsetof(CPUPPCState, spr[SPR_SPRG2]) },
|
|
||||||
{ "sprg3", offsetof(CPUPPCState, spr[SPR_SPRG3]) },
|
|
||||||
{ "sprg4", offsetof(CPUPPCState, spr[SPR_SPRG4]) },
|
|
||||||
{ "sprg5", offsetof(CPUPPCState, spr[SPR_SPRG5]) },
|
|
||||||
{ "sprg6", offsetof(CPUPPCState, spr[SPR_SPRG6]) },
|
|
||||||
{ "sprg7", offsetof(CPUPPCState, spr[SPR_SPRG7]) },
|
|
||||||
{ "pid", offsetof(CPUPPCState, spr[SPR_BOOKE_PID]) },
|
|
||||||
{ "csrr0", offsetof(CPUPPCState, spr[SPR_BOOKE_CSRR0]) },
|
|
||||||
{ "csrr1", offsetof(CPUPPCState, spr[SPR_BOOKE_CSRR1]) },
|
|
||||||
{ "esr", offsetof(CPUPPCState, spr[SPR_BOOKE_ESR]) },
|
|
||||||
{ "dear", offsetof(CPUPPCState, spr[SPR_BOOKE_DEAR]) },
|
|
||||||
{ "mcsr", offsetof(CPUPPCState, spr[SPR_BOOKE_MCSR]) },
|
|
||||||
{ "tsr", offsetof(CPUPPCState, spr[SPR_BOOKE_TSR]) },
|
|
||||||
{ "tcr", offsetof(CPUPPCState, spr[SPR_BOOKE_TCR]) },
|
|
||||||
{ "vrsave", offsetof(CPUPPCState, spr[SPR_VRSAVE]) },
|
|
||||||
{ "pir", offsetof(CPUPPCState, spr[SPR_BOOKE_PIR]) },
|
|
||||||
{ "mcsrr0", offsetof(CPUPPCState, spr[SPR_BOOKE_MCSRR0]) },
|
|
||||||
{ "mcsrr1", offsetof(CPUPPCState, spr[SPR_BOOKE_MCSRR1]) },
|
|
||||||
{ "decar", offsetof(CPUPPCState, spr[SPR_BOOKE_DECAR]) },
|
|
||||||
{ "ivpr", offsetof(CPUPPCState, spr[SPR_BOOKE_IVPR]) },
|
|
||||||
{ "epcr", offsetof(CPUPPCState, spr[SPR_BOOKE_EPCR]) },
|
|
||||||
{ "sprg8", offsetof(CPUPPCState, spr[SPR_BOOKE_SPRG8]) },
|
|
||||||
{ "ivor0", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR0]) },
|
|
||||||
{ "ivor1", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR1]) },
|
|
||||||
{ "ivor2", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR2]) },
|
|
||||||
{ "ivor3", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR3]) },
|
|
||||||
{ "ivor4", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR4]) },
|
|
||||||
{ "ivor5", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR5]) },
|
|
||||||
{ "ivor6", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR6]) },
|
|
||||||
{ "ivor7", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR7]) },
|
|
||||||
{ "ivor8", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR8]) },
|
|
||||||
{ "ivor9", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR9]) },
|
|
||||||
{ "ivor10", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR10]) },
|
|
||||||
{ "ivor11", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR11]) },
|
|
||||||
{ "ivor12", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR12]) },
|
|
||||||
{ "ivor13", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR13]) },
|
|
||||||
{ "ivor14", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR14]) },
|
|
||||||
{ "ivor15", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR15]) },
|
|
||||||
{ "ivor32", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR32]) },
|
|
||||||
{ "ivor33", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR33]) },
|
|
||||||
{ "ivor34", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR34]) },
|
|
||||||
{ "ivor35", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR35]) },
|
|
||||||
{ "ivor36", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR36]) },
|
|
||||||
{ "ivor37", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR37]) },
|
|
||||||
{ "mas0", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS0]) },
|
|
||||||
{ "mas1", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS1]) },
|
|
||||||
{ "mas2", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS2]) },
|
|
||||||
{ "mas3", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS3]) },
|
|
||||||
{ "mas4", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS4]) },
|
|
||||||
{ "mas6", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS6]) },
|
|
||||||
{ "mas7", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS7]) },
|
|
||||||
{ "mmucfg", offsetof(CPUPPCState, spr[SPR_MMUCFG]) },
|
|
||||||
{ "tlb0cfg", offsetof(CPUPPCState, spr[SPR_BOOKE_TLB0CFG]) },
|
|
||||||
{ "tlb1cfg", offsetof(CPUPPCState, spr[SPR_BOOKE_TLB1CFG]) },
|
|
||||||
{ "epr", offsetof(CPUPPCState, spr[SPR_BOOKE_EPR]) },
|
|
||||||
{ "eplc", offsetof(CPUPPCState, spr[SPR_BOOKE_EPLC]) },
|
|
||||||
{ "epsc", offsetof(CPUPPCState, spr[SPR_BOOKE_EPSC]) },
|
|
||||||
{ "svr", offsetof(CPUPPCState, spr[SPR_E500_SVR]) },
|
|
||||||
{ "mcar", offsetof(CPUPPCState, spr[SPR_Exxx_MCAR]) },
|
|
||||||
{ "pid1", offsetof(CPUPPCState, spr[SPR_BOOKE_PID1]) },
|
|
||||||
{ "pid2", offsetof(CPUPPCState, spr[SPR_BOOKE_PID2]) },
|
|
||||||
{ "hid0", offsetof(CPUPPCState, spr[SPR_HID0]) },
|
|
||||||
|
|
||||||
#elif defined(TARGET_SPARC)
|
|
||||||
{ "g0", offsetof(CPUSPARCState, gregs[0]) },
|
|
||||||
{ "g1", offsetof(CPUSPARCState, gregs[1]) },
|
|
||||||
{ "g2", offsetof(CPUSPARCState, gregs[2]) },
|
|
||||||
{ "g3", offsetof(CPUSPARCState, gregs[3]) },
|
|
||||||
{ "g4", offsetof(CPUSPARCState, gregs[4]) },
|
|
||||||
{ "g5", offsetof(CPUSPARCState, gregs[5]) },
|
|
||||||
{ "g6", offsetof(CPUSPARCState, gregs[6]) },
|
|
||||||
{ "g7", offsetof(CPUSPARCState, gregs[7]) },
|
|
||||||
{ "o0", 0, monitor_get_reg },
|
|
||||||
{ "o1", 1, monitor_get_reg },
|
|
||||||
{ "o2", 2, monitor_get_reg },
|
|
||||||
{ "o3", 3, monitor_get_reg },
|
|
||||||
{ "o4", 4, monitor_get_reg },
|
|
||||||
{ "o5", 5, monitor_get_reg },
|
|
||||||
{ "o6", 6, monitor_get_reg },
|
|
||||||
{ "o7", 7, monitor_get_reg },
|
|
||||||
{ "l0", 8, monitor_get_reg },
|
|
||||||
{ "l1", 9, monitor_get_reg },
|
|
||||||
{ "l2", 10, monitor_get_reg },
|
|
||||||
{ "l3", 11, monitor_get_reg },
|
|
||||||
{ "l4", 12, monitor_get_reg },
|
|
||||||
{ "l5", 13, monitor_get_reg },
|
|
||||||
{ "l6", 14, monitor_get_reg },
|
|
||||||
{ "l7", 15, monitor_get_reg },
|
|
||||||
{ "i0", 16, monitor_get_reg },
|
|
||||||
{ "i1", 17, monitor_get_reg },
|
|
||||||
{ "i2", 18, monitor_get_reg },
|
|
||||||
{ "i3", 19, monitor_get_reg },
|
|
||||||
{ "i4", 20, monitor_get_reg },
|
|
||||||
{ "i5", 21, monitor_get_reg },
|
|
||||||
{ "i6", 22, monitor_get_reg },
|
|
||||||
{ "i7", 23, monitor_get_reg },
|
|
||||||
{ "pc", offsetof(CPUSPARCState, pc) },
|
|
||||||
{ "npc", offsetof(CPUSPARCState, npc) },
|
|
||||||
{ "y", offsetof(CPUSPARCState, y) },
|
|
||||||
#ifndef TARGET_SPARC64
|
|
||||||
{ "psr", 0, &monitor_get_psr, },
|
|
||||||
{ "wim", offsetof(CPUSPARCState, wim) },
|
|
||||||
#endif
|
|
||||||
{ "tbr", offsetof(CPUSPARCState, tbr) },
|
|
||||||
{ "fsr", offsetof(CPUSPARCState, fsr) },
|
|
||||||
{ "f0", offsetof(CPUSPARCState, fpr[0].l.upper) },
|
|
||||||
{ "f1", offsetof(CPUSPARCState, fpr[0].l.lower) },
|
|
||||||
{ "f2", offsetof(CPUSPARCState, fpr[1].l.upper) },
|
|
||||||
{ "f3", offsetof(CPUSPARCState, fpr[1].l.lower) },
|
|
||||||
{ "f4", offsetof(CPUSPARCState, fpr[2].l.upper) },
|
|
||||||
{ "f5", offsetof(CPUSPARCState, fpr[2].l.lower) },
|
|
||||||
{ "f6", offsetof(CPUSPARCState, fpr[3].l.upper) },
|
|
||||||
{ "f7", offsetof(CPUSPARCState, fpr[3].l.lower) },
|
|
||||||
{ "f8", offsetof(CPUSPARCState, fpr[4].l.upper) },
|
|
||||||
{ "f9", offsetof(CPUSPARCState, fpr[4].l.lower) },
|
|
||||||
{ "f10", offsetof(CPUSPARCState, fpr[5].l.upper) },
|
|
||||||
{ "f11", offsetof(CPUSPARCState, fpr[5].l.lower) },
|
|
||||||
{ "f12", offsetof(CPUSPARCState, fpr[6].l.upper) },
|
|
||||||
{ "f13", offsetof(CPUSPARCState, fpr[6].l.lower) },
|
|
||||||
{ "f14", offsetof(CPUSPARCState, fpr[7].l.upper) },
|
|
||||||
{ "f15", offsetof(CPUSPARCState, fpr[7].l.lower) },
|
|
||||||
{ "f16", offsetof(CPUSPARCState, fpr[8].l.upper) },
|
|
||||||
{ "f17", offsetof(CPUSPARCState, fpr[8].l.lower) },
|
|
||||||
{ "f18", offsetof(CPUSPARCState, fpr[9].l.upper) },
|
|
||||||
{ "f19", offsetof(CPUSPARCState, fpr[9].l.lower) },
|
|
||||||
{ "f20", offsetof(CPUSPARCState, fpr[10].l.upper) },
|
|
||||||
{ "f21", offsetof(CPUSPARCState, fpr[10].l.lower) },
|
|
||||||
{ "f22", offsetof(CPUSPARCState, fpr[11].l.upper) },
|
|
||||||
{ "f23", offsetof(CPUSPARCState, fpr[11].l.lower) },
|
|
||||||
{ "f24", offsetof(CPUSPARCState, fpr[12].l.upper) },
|
|
||||||
{ "f25", offsetof(CPUSPARCState, fpr[12].l.lower) },
|
|
||||||
{ "f26", offsetof(CPUSPARCState, fpr[13].l.upper) },
|
|
||||||
{ "f27", offsetof(CPUSPARCState, fpr[13].l.lower) },
|
|
||||||
{ "f28", offsetof(CPUSPARCState, fpr[14].l.upper) },
|
|
||||||
{ "f29", offsetof(CPUSPARCState, fpr[14].l.lower) },
|
|
||||||
{ "f30", offsetof(CPUSPARCState, fpr[15].l.upper) },
|
|
||||||
{ "f31", offsetof(CPUSPARCState, fpr[15].l.lower) },
|
|
||||||
#ifdef TARGET_SPARC64
|
|
||||||
{ "f32", offsetof(CPUSPARCState, fpr[16]) },
|
|
||||||
{ "f34", offsetof(CPUSPARCState, fpr[17]) },
|
|
||||||
{ "f36", offsetof(CPUSPARCState, fpr[18]) },
|
|
||||||
{ "f38", offsetof(CPUSPARCState, fpr[19]) },
|
|
||||||
{ "f40", offsetof(CPUSPARCState, fpr[20]) },
|
|
||||||
{ "f42", offsetof(CPUSPARCState, fpr[21]) },
|
|
||||||
{ "f44", offsetof(CPUSPARCState, fpr[22]) },
|
|
||||||
{ "f46", offsetof(CPUSPARCState, fpr[23]) },
|
|
||||||
{ "f48", offsetof(CPUSPARCState, fpr[24]) },
|
|
||||||
{ "f50", offsetof(CPUSPARCState, fpr[25]) },
|
|
||||||
{ "f52", offsetof(CPUSPARCState, fpr[26]) },
|
|
||||||
{ "f54", offsetof(CPUSPARCState, fpr[27]) },
|
|
||||||
{ "f56", offsetof(CPUSPARCState, fpr[28]) },
|
|
||||||
{ "f58", offsetof(CPUSPARCState, fpr[29]) },
|
|
||||||
{ "f60", offsetof(CPUSPARCState, fpr[30]) },
|
|
||||||
{ "f62", offsetof(CPUSPARCState, fpr[31]) },
|
|
||||||
{ "asi", offsetof(CPUSPARCState, asi) },
|
|
||||||
{ "pstate", offsetof(CPUSPARCState, pstate) },
|
|
||||||
{ "cansave", offsetof(CPUSPARCState, cansave) },
|
|
||||||
{ "canrestore", offsetof(CPUSPARCState, canrestore) },
|
|
||||||
{ "otherwin", offsetof(CPUSPARCState, otherwin) },
|
|
||||||
{ "wstate", offsetof(CPUSPARCState, wstate) },
|
|
||||||
{ "cleanwin", offsetof(CPUSPARCState, cleanwin) },
|
|
||||||
{ "fprs", offsetof(CPUSPARCState, fprs) },
|
|
||||||
#endif
|
|
||||||
#endif
|
|
||||||
{ NULL },
|
|
||||||
};
|
|
||||||
|
|
||||||
static void GCC_FMT_ATTR(2, 3) QEMU_NORETURN
|
static void GCC_FMT_ATTR(2, 3) QEMU_NORETURN
|
||||||
expr_error(Monitor *mon, const char *fmt, ...)
|
expr_error(Monitor *mon, const char *fmt, ...)
|
||||||
@ -2936,10 +2088,14 @@ expr_error(Monitor *mon, const char *fmt, ...)
|
|||||||
/* return 0 if OK, -1 if not found */
|
/* return 0 if OK, -1 if not found */
|
||||||
static int get_monitor_def(target_long *pval, const char *name)
|
static int get_monitor_def(target_long *pval, const char *name)
|
||||||
{
|
{
|
||||||
const MonitorDef *md;
|
const MonitorDef *md = target_monitor_defs();
|
||||||
void *ptr;
|
void *ptr;
|
||||||
|
|
||||||
for(md = monitor_defs; md->name != NULL; md++) {
|
if (md == NULL) {
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
for(; md->name != NULL; md++) {
|
||||||
if (compare_cmd(name, md->name)) {
|
if (compare_cmd(name, md->name)) {
|
||||||
if (md->get_value) {
|
if (md->get_value) {
|
||||||
*pval = md->get_value(md, md->offset);
|
*pval = md->get_value(md, md->offset);
|
||||||
|
|||||||
@ -38,3 +38,4 @@ stub-obj-$(CONFIG_WIN32) += fd-register.o
|
|||||||
stub-obj-y += cpus.o
|
stub-obj-y += cpus.o
|
||||||
stub-obj-y += kvm.o
|
stub-obj-y += kvm.o
|
||||||
stub-obj-y += qmp_pc_dimm_device_list.o
|
stub-obj-y += qmp_pc_dimm_device_list.o
|
||||||
|
stub-obj-y += target-monitor-defs.o
|
||||||
|
|||||||
9
stubs/target-monitor-defs.c
Normal file
9
stubs/target-monitor-defs.c
Normal file
@ -0,0 +1,9 @@
|
|||||||
|
#include "stddef.h"
|
||||||
|
#include "qemu/typedefs.h"
|
||||||
|
|
||||||
|
const MonitorDef *target_monitor_defs(void);
|
||||||
|
|
||||||
|
const MonitorDef *target_monitor_defs(void)
|
||||||
|
{
|
||||||
|
return NULL;
|
||||||
|
}
|
||||||
@ -2,6 +2,6 @@ obj-y += translate.o helper.o cpu.o
|
|||||||
obj-y += excp_helper.o fpu_helper.o cc_helper.o int_helper.o svm_helper.o
|
obj-y += excp_helper.o fpu_helper.o cc_helper.o int_helper.o svm_helper.o
|
||||||
obj-y += smm_helper.o misc_helper.o mem_helper.o seg_helper.o
|
obj-y += smm_helper.o misc_helper.o mem_helper.o seg_helper.o
|
||||||
obj-y += gdbstub.o
|
obj-y += gdbstub.o
|
||||||
obj-$(CONFIG_SOFTMMU) += machine.o arch_memory_mapping.o arch_dump.o
|
obj-$(CONFIG_SOFTMMU) += machine.o arch_memory_mapping.o arch_dump.o monitor.o
|
||||||
obj-$(CONFIG_KVM) += kvm.o
|
obj-$(CONFIG_KVM) += kvm.o
|
||||||
obj-$(call lnot,$(CONFIG_KVM)) += kvm-stub.o
|
obj-$(call lnot,$(CONFIG_KVM)) += kvm-stub.o
|
||||||
|
|||||||
494
target-i386/monitor.c
Normal file
494
target-i386/monitor.c
Normal file
@ -0,0 +1,494 @@
|
|||||||
|
/*
|
||||||
|
* QEMU monitor
|
||||||
|
*
|
||||||
|
* Copyright (c) 2003-2004 Fabrice Bellard
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||||
|
* of this software and associated documentation files (the "Software"), to deal
|
||||||
|
* in the Software without restriction, including without limitation the rights
|
||||||
|
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||||
|
* copies of the Software, and to permit persons to whom the Software is
|
||||||
|
* furnished to do so, subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in
|
||||||
|
* all copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||||
|
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||||
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||||
|
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||||
|
* THE SOFTWARE.
|
||||||
|
*/
|
||||||
|
#include "cpu.h"
|
||||||
|
#include "monitor/monitor.h"
|
||||||
|
#include "monitor/hmp-target.h"
|
||||||
|
#include "hmp.h"
|
||||||
|
|
||||||
|
|
||||||
|
static void print_pte(Monitor *mon, hwaddr addr,
|
||||||
|
hwaddr pte,
|
||||||
|
hwaddr mask)
|
||||||
|
{
|
||||||
|
#ifdef TARGET_X86_64
|
||||||
|
if (addr & (1ULL << 47)) {
|
||||||
|
addr |= -1LL << 48;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
monitor_printf(mon, TARGET_FMT_plx ": " TARGET_FMT_plx
|
||||||
|
" %c%c%c%c%c%c%c%c%c\n",
|
||||||
|
addr,
|
||||||
|
pte & mask,
|
||||||
|
pte & PG_NX_MASK ? 'X' : '-',
|
||||||
|
pte & PG_GLOBAL_MASK ? 'G' : '-',
|
||||||
|
pte & PG_PSE_MASK ? 'P' : '-',
|
||||||
|
pte & PG_DIRTY_MASK ? 'D' : '-',
|
||||||
|
pte & PG_ACCESSED_MASK ? 'A' : '-',
|
||||||
|
pte & PG_PCD_MASK ? 'C' : '-',
|
||||||
|
pte & PG_PWT_MASK ? 'T' : '-',
|
||||||
|
pte & PG_USER_MASK ? 'U' : '-',
|
||||||
|
pte & PG_RW_MASK ? 'W' : '-');
|
||||||
|
}
|
||||||
|
|
||||||
|
static void tlb_info_32(Monitor *mon, CPUArchState *env)
|
||||||
|
{
|
||||||
|
unsigned int l1, l2;
|
||||||
|
uint32_t pgd, pde, pte;
|
||||||
|
|
||||||
|
pgd = env->cr[3] & ~0xfff;
|
||||||
|
for(l1 = 0; l1 < 1024; l1++) {
|
||||||
|
cpu_physical_memory_read(pgd + l1 * 4, &pde, 4);
|
||||||
|
pde = le32_to_cpu(pde);
|
||||||
|
if (pde & PG_PRESENT_MASK) {
|
||||||
|
if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) {
|
||||||
|
/* 4M pages */
|
||||||
|
print_pte(mon, (l1 << 22), pde, ~((1 << 21) - 1));
|
||||||
|
} else {
|
||||||
|
for(l2 = 0; l2 < 1024; l2++) {
|
||||||
|
cpu_physical_memory_read((pde & ~0xfff) + l2 * 4, &pte, 4);
|
||||||
|
pte = le32_to_cpu(pte);
|
||||||
|
if (pte & PG_PRESENT_MASK) {
|
||||||
|
print_pte(mon, (l1 << 22) + (l2 << 12),
|
||||||
|
pte & ~PG_PSE_MASK,
|
||||||
|
~0xfff);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static void tlb_info_pae32(Monitor *mon, CPUArchState *env)
|
||||||
|
{
|
||||||
|
unsigned int l1, l2, l3;
|
||||||
|
uint64_t pdpe, pde, pte;
|
||||||
|
uint64_t pdp_addr, pd_addr, pt_addr;
|
||||||
|
|
||||||
|
pdp_addr = env->cr[3] & ~0x1f;
|
||||||
|
for (l1 = 0; l1 < 4; l1++) {
|
||||||
|
cpu_physical_memory_read(pdp_addr + l1 * 8, &pdpe, 8);
|
||||||
|
pdpe = le64_to_cpu(pdpe);
|
||||||
|
if (pdpe & PG_PRESENT_MASK) {
|
||||||
|
pd_addr = pdpe & 0x3fffffffff000ULL;
|
||||||
|
for (l2 = 0; l2 < 512; l2++) {
|
||||||
|
cpu_physical_memory_read(pd_addr + l2 * 8, &pde, 8);
|
||||||
|
pde = le64_to_cpu(pde);
|
||||||
|
if (pde & PG_PRESENT_MASK) {
|
||||||
|
if (pde & PG_PSE_MASK) {
|
||||||
|
/* 2M pages with PAE, CR4.PSE is ignored */
|
||||||
|
print_pte(mon, (l1 << 30 ) + (l2 << 21), pde,
|
||||||
|
~((hwaddr)(1 << 20) - 1));
|
||||||
|
} else {
|
||||||
|
pt_addr = pde & 0x3fffffffff000ULL;
|
||||||
|
for (l3 = 0; l3 < 512; l3++) {
|
||||||
|
cpu_physical_memory_read(pt_addr + l3 * 8, &pte, 8);
|
||||||
|
pte = le64_to_cpu(pte);
|
||||||
|
if (pte & PG_PRESENT_MASK) {
|
||||||
|
print_pte(mon, (l1 << 30 ) + (l2 << 21)
|
||||||
|
+ (l3 << 12),
|
||||||
|
pte & ~PG_PSE_MASK,
|
||||||
|
~(hwaddr)0xfff);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef TARGET_X86_64
|
||||||
|
static void tlb_info_64(Monitor *mon, CPUArchState *env)
|
||||||
|
{
|
||||||
|
uint64_t l1, l2, l3, l4;
|
||||||
|
uint64_t pml4e, pdpe, pde, pte;
|
||||||
|
uint64_t pml4_addr, pdp_addr, pd_addr, pt_addr;
|
||||||
|
|
||||||
|
pml4_addr = env->cr[3] & 0x3fffffffff000ULL;
|
||||||
|
for (l1 = 0; l1 < 512; l1++) {
|
||||||
|
cpu_physical_memory_read(pml4_addr + l1 * 8, &pml4e, 8);
|
||||||
|
pml4e = le64_to_cpu(pml4e);
|
||||||
|
if (pml4e & PG_PRESENT_MASK) {
|
||||||
|
pdp_addr = pml4e & 0x3fffffffff000ULL;
|
||||||
|
for (l2 = 0; l2 < 512; l2++) {
|
||||||
|
cpu_physical_memory_read(pdp_addr + l2 * 8, &pdpe, 8);
|
||||||
|
pdpe = le64_to_cpu(pdpe);
|
||||||
|
if (pdpe & PG_PRESENT_MASK) {
|
||||||
|
if (pdpe & PG_PSE_MASK) {
|
||||||
|
/* 1G pages, CR4.PSE is ignored */
|
||||||
|
print_pte(mon, (l1 << 39) + (l2 << 30), pdpe,
|
||||||
|
0x3ffffc0000000ULL);
|
||||||
|
} else {
|
||||||
|
pd_addr = pdpe & 0x3fffffffff000ULL;
|
||||||
|
for (l3 = 0; l3 < 512; l3++) {
|
||||||
|
cpu_physical_memory_read(pd_addr + l3 * 8, &pde, 8);
|
||||||
|
pde = le64_to_cpu(pde);
|
||||||
|
if (pde & PG_PRESENT_MASK) {
|
||||||
|
if (pde & PG_PSE_MASK) {
|
||||||
|
/* 2M pages, CR4.PSE is ignored */
|
||||||
|
print_pte(mon, (l1 << 39) + (l2 << 30) +
|
||||||
|
(l3 << 21), pde,
|
||||||
|
0x3ffffffe00000ULL);
|
||||||
|
} else {
|
||||||
|
pt_addr = pde & 0x3fffffffff000ULL;
|
||||||
|
for (l4 = 0; l4 < 512; l4++) {
|
||||||
|
cpu_physical_memory_read(pt_addr
|
||||||
|
+ l4 * 8,
|
||||||
|
&pte, 8);
|
||||||
|
pte = le64_to_cpu(pte);
|
||||||
|
if (pte & PG_PRESENT_MASK) {
|
||||||
|
print_pte(mon, (l1 << 39) +
|
||||||
|
(l2 << 30) +
|
||||||
|
(l3 << 21) + (l4 << 12),
|
||||||
|
pte & ~PG_PSE_MASK,
|
||||||
|
0x3fffffffff000ULL);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#endif /* TARGET_X86_64 */
|
||||||
|
|
||||||
|
void hmp_info_tlb(Monitor *mon, const QDict *qdict)
|
||||||
|
{
|
||||||
|
CPUArchState *env;
|
||||||
|
|
||||||
|
env = mon_get_cpu_env();
|
||||||
|
|
||||||
|
if (!(env->cr[0] & CR0_PG_MASK)) {
|
||||||
|
monitor_printf(mon, "PG disabled\n");
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
if (env->cr[4] & CR4_PAE_MASK) {
|
||||||
|
#ifdef TARGET_X86_64
|
||||||
|
if (env->hflags & HF_LMA_MASK) {
|
||||||
|
tlb_info_64(mon, env);
|
||||||
|
} else
|
||||||
|
#endif
|
||||||
|
{
|
||||||
|
tlb_info_pae32(mon, env);
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
tlb_info_32(mon, env);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static void mem_print(Monitor *mon, hwaddr *pstart,
|
||||||
|
int *plast_prot,
|
||||||
|
hwaddr end, int prot)
|
||||||
|
{
|
||||||
|
int prot1;
|
||||||
|
prot1 = *plast_prot;
|
||||||
|
if (prot != prot1) {
|
||||||
|
if (*pstart != -1) {
|
||||||
|
monitor_printf(mon, TARGET_FMT_plx "-" TARGET_FMT_plx " "
|
||||||
|
TARGET_FMT_plx " %c%c%c\n",
|
||||||
|
*pstart, end, end - *pstart,
|
||||||
|
prot1 & PG_USER_MASK ? 'u' : '-',
|
||||||
|
'r',
|
||||||
|
prot1 & PG_RW_MASK ? 'w' : '-');
|
||||||
|
}
|
||||||
|
if (prot != 0)
|
||||||
|
*pstart = end;
|
||||||
|
else
|
||||||
|
*pstart = -1;
|
||||||
|
*plast_prot = prot;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static void mem_info_32(Monitor *mon, CPUArchState *env)
|
||||||
|
{
|
||||||
|
unsigned int l1, l2;
|
||||||
|
int prot, last_prot;
|
||||||
|
uint32_t pgd, pde, pte;
|
||||||
|
hwaddr start, end;
|
||||||
|
|
||||||
|
pgd = env->cr[3] & ~0xfff;
|
||||||
|
last_prot = 0;
|
||||||
|
start = -1;
|
||||||
|
for(l1 = 0; l1 < 1024; l1++) {
|
||||||
|
cpu_physical_memory_read(pgd + l1 * 4, &pde, 4);
|
||||||
|
pde = le32_to_cpu(pde);
|
||||||
|
end = l1 << 22;
|
||||||
|
if (pde & PG_PRESENT_MASK) {
|
||||||
|
if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) {
|
||||||
|
prot = pde & (PG_USER_MASK | PG_RW_MASK | PG_PRESENT_MASK);
|
||||||
|
mem_print(mon, &start, &last_prot, end, prot);
|
||||||
|
} else {
|
||||||
|
for(l2 = 0; l2 < 1024; l2++) {
|
||||||
|
cpu_physical_memory_read((pde & ~0xfff) + l2 * 4, &pte, 4);
|
||||||
|
pte = le32_to_cpu(pte);
|
||||||
|
end = (l1 << 22) + (l2 << 12);
|
||||||
|
if (pte & PG_PRESENT_MASK) {
|
||||||
|
prot = pte & pde &
|
||||||
|
(PG_USER_MASK | PG_RW_MASK | PG_PRESENT_MASK);
|
||||||
|
} else {
|
||||||
|
prot = 0;
|
||||||
|
}
|
||||||
|
mem_print(mon, &start, &last_prot, end, prot);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
prot = 0;
|
||||||
|
mem_print(mon, &start, &last_prot, end, prot);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
/* Flush last range */
|
||||||
|
mem_print(mon, &start, &last_prot, (hwaddr)1 << 32, 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void mem_info_pae32(Monitor *mon, CPUArchState *env)
|
||||||
|
{
|
||||||
|
unsigned int l1, l2, l3;
|
||||||
|
int prot, last_prot;
|
||||||
|
uint64_t pdpe, pde, pte;
|
||||||
|
uint64_t pdp_addr, pd_addr, pt_addr;
|
||||||
|
hwaddr start, end;
|
||||||
|
|
||||||
|
pdp_addr = env->cr[3] & ~0x1f;
|
||||||
|
last_prot = 0;
|
||||||
|
start = -1;
|
||||||
|
for (l1 = 0; l1 < 4; l1++) {
|
||||||
|
cpu_physical_memory_read(pdp_addr + l1 * 8, &pdpe, 8);
|
||||||
|
pdpe = le64_to_cpu(pdpe);
|
||||||
|
end = l1 << 30;
|
||||||
|
if (pdpe & PG_PRESENT_MASK) {
|
||||||
|
pd_addr = pdpe & 0x3fffffffff000ULL;
|
||||||
|
for (l2 = 0; l2 < 512; l2++) {
|
||||||
|
cpu_physical_memory_read(pd_addr + l2 * 8, &pde, 8);
|
||||||
|
pde = le64_to_cpu(pde);
|
||||||
|
end = (l1 << 30) + (l2 << 21);
|
||||||
|
if (pde & PG_PRESENT_MASK) {
|
||||||
|
if (pde & PG_PSE_MASK) {
|
||||||
|
prot = pde & (PG_USER_MASK | PG_RW_MASK |
|
||||||
|
PG_PRESENT_MASK);
|
||||||
|
mem_print(mon, &start, &last_prot, end, prot);
|
||||||
|
} else {
|
||||||
|
pt_addr = pde & 0x3fffffffff000ULL;
|
||||||
|
for (l3 = 0; l3 < 512; l3++) {
|
||||||
|
cpu_physical_memory_read(pt_addr + l3 * 8, &pte, 8);
|
||||||
|
pte = le64_to_cpu(pte);
|
||||||
|
end = (l1 << 30) + (l2 << 21) + (l3 << 12);
|
||||||
|
if (pte & PG_PRESENT_MASK) {
|
||||||
|
prot = pte & pde & (PG_USER_MASK | PG_RW_MASK |
|
||||||
|
PG_PRESENT_MASK);
|
||||||
|
} else {
|
||||||
|
prot = 0;
|
||||||
|
}
|
||||||
|
mem_print(mon, &start, &last_prot, end, prot);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
prot = 0;
|
||||||
|
mem_print(mon, &start, &last_prot, end, prot);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
prot = 0;
|
||||||
|
mem_print(mon, &start, &last_prot, end, prot);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
/* Flush last range */
|
||||||
|
mem_print(mon, &start, &last_prot, (hwaddr)1 << 32, 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef TARGET_X86_64
|
||||||
|
static void mem_info_64(Monitor *mon, CPUArchState *env)
|
||||||
|
{
|
||||||
|
int prot, last_prot;
|
||||||
|
uint64_t l1, l2, l3, l4;
|
||||||
|
uint64_t pml4e, pdpe, pde, pte;
|
||||||
|
uint64_t pml4_addr, pdp_addr, pd_addr, pt_addr, start, end;
|
||||||
|
|
||||||
|
pml4_addr = env->cr[3] & 0x3fffffffff000ULL;
|
||||||
|
last_prot = 0;
|
||||||
|
start = -1;
|
||||||
|
for (l1 = 0; l1 < 512; l1++) {
|
||||||
|
cpu_physical_memory_read(pml4_addr + l1 * 8, &pml4e, 8);
|
||||||
|
pml4e = le64_to_cpu(pml4e);
|
||||||
|
end = l1 << 39;
|
||||||
|
if (pml4e & PG_PRESENT_MASK) {
|
||||||
|
pdp_addr = pml4e & 0x3fffffffff000ULL;
|
||||||
|
for (l2 = 0; l2 < 512; l2++) {
|
||||||
|
cpu_physical_memory_read(pdp_addr + l2 * 8, &pdpe, 8);
|
||||||
|
pdpe = le64_to_cpu(pdpe);
|
||||||
|
end = (l1 << 39) + (l2 << 30);
|
||||||
|
if (pdpe & PG_PRESENT_MASK) {
|
||||||
|
if (pdpe & PG_PSE_MASK) {
|
||||||
|
prot = pdpe & (PG_USER_MASK | PG_RW_MASK |
|
||||||
|
PG_PRESENT_MASK);
|
||||||
|
prot &= pml4e;
|
||||||
|
mem_print(mon, &start, &last_prot, end, prot);
|
||||||
|
} else {
|
||||||
|
pd_addr = pdpe & 0x3fffffffff000ULL;
|
||||||
|
for (l3 = 0; l3 < 512; l3++) {
|
||||||
|
cpu_physical_memory_read(pd_addr + l3 * 8, &pde, 8);
|
||||||
|
pde = le64_to_cpu(pde);
|
||||||
|
end = (l1 << 39) + (l2 << 30) + (l3 << 21);
|
||||||
|
if (pde & PG_PRESENT_MASK) {
|
||||||
|
if (pde & PG_PSE_MASK) {
|
||||||
|
prot = pde & (PG_USER_MASK | PG_RW_MASK |
|
||||||
|
PG_PRESENT_MASK);
|
||||||
|
prot &= pml4e & pdpe;
|
||||||
|
mem_print(mon, &start, &last_prot, end, prot);
|
||||||
|
} else {
|
||||||
|
pt_addr = pde & 0x3fffffffff000ULL;
|
||||||
|
for (l4 = 0; l4 < 512; l4++) {
|
||||||
|
cpu_physical_memory_read(pt_addr
|
||||||
|
+ l4 * 8,
|
||||||
|
&pte, 8);
|
||||||
|
pte = le64_to_cpu(pte);
|
||||||
|
end = (l1 << 39) + (l2 << 30) +
|
||||||
|
(l3 << 21) + (l4 << 12);
|
||||||
|
if (pte & PG_PRESENT_MASK) {
|
||||||
|
prot = pte & (PG_USER_MASK | PG_RW_MASK |
|
||||||
|
PG_PRESENT_MASK);
|
||||||
|
prot &= pml4e & pdpe & pde;
|
||||||
|
} else {
|
||||||
|
prot = 0;
|
||||||
|
}
|
||||||
|
mem_print(mon, &start, &last_prot, end, prot);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
prot = 0;
|
||||||
|
mem_print(mon, &start, &last_prot, end, prot);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
prot = 0;
|
||||||
|
mem_print(mon, &start, &last_prot, end, prot);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
prot = 0;
|
||||||
|
mem_print(mon, &start, &last_prot, end, prot);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
/* Flush last range */
|
||||||
|
mem_print(mon, &start, &last_prot, (hwaddr)1 << 48, 0);
|
||||||
|
}
|
||||||
|
#endif /* TARGET_X86_64 */
|
||||||
|
|
||||||
|
void hmp_info_mem(Monitor *mon, const QDict *qdict)
|
||||||
|
{
|
||||||
|
CPUArchState *env;
|
||||||
|
|
||||||
|
env = mon_get_cpu_env();
|
||||||
|
|
||||||
|
if (!(env->cr[0] & CR0_PG_MASK)) {
|
||||||
|
monitor_printf(mon, "PG disabled\n");
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
if (env->cr[4] & CR4_PAE_MASK) {
|
||||||
|
#ifdef TARGET_X86_64
|
||||||
|
if (env->hflags & HF_LMA_MASK) {
|
||||||
|
mem_info_64(mon, env);
|
||||||
|
} else
|
||||||
|
#endif
|
||||||
|
{
|
||||||
|
mem_info_pae32(mon, env);
|
||||||
|
}
|
||||||
|
} else {
|
||||||
|
mem_info_32(mon, env);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void hmp_mce(Monitor *mon, const QDict *qdict)
|
||||||
|
{
|
||||||
|
X86CPU *cpu;
|
||||||
|
CPUState *cs;
|
||||||
|
int cpu_index = qdict_get_int(qdict, "cpu_index");
|
||||||
|
int bank = qdict_get_int(qdict, "bank");
|
||||||
|
uint64_t status = qdict_get_int(qdict, "status");
|
||||||
|
uint64_t mcg_status = qdict_get_int(qdict, "mcg_status");
|
||||||
|
uint64_t addr = qdict_get_int(qdict, "addr");
|
||||||
|
uint64_t misc = qdict_get_int(qdict, "misc");
|
||||||
|
int flags = MCE_INJECT_UNCOND_AO;
|
||||||
|
|
||||||
|
if (qdict_get_try_bool(qdict, "broadcast", false)) {
|
||||||
|
flags |= MCE_INJECT_BROADCAST;
|
||||||
|
}
|
||||||
|
cs = qemu_get_cpu(cpu_index);
|
||||||
|
if (cs != NULL) {
|
||||||
|
cpu = X86_CPU(cs);
|
||||||
|
cpu_x86_inject_mce(mon, cpu, bank, status, mcg_status, addr, misc,
|
||||||
|
flags);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static target_long monitor_get_pc(const struct MonitorDef *md, int val)
|
||||||
|
{
|
||||||
|
CPUArchState *env = mon_get_cpu_env();
|
||||||
|
return env->eip + env->segs[R_CS].base;
|
||||||
|
}
|
||||||
|
|
||||||
|
const MonitorDef monitor_defs[] = {
|
||||||
|
#define SEG(name, seg) \
|
||||||
|
{ name, offsetof(CPUX86State, segs[seg].selector), NULL, MD_I32 },\
|
||||||
|
{ name ".base", offsetof(CPUX86State, segs[seg].base) },\
|
||||||
|
{ name ".limit", offsetof(CPUX86State, segs[seg].limit), NULL, MD_I32 },
|
||||||
|
|
||||||
|
{ "eax", offsetof(CPUX86State, regs[0]) },
|
||||||
|
{ "ecx", offsetof(CPUX86State, regs[1]) },
|
||||||
|
{ "edx", offsetof(CPUX86State, regs[2]) },
|
||||||
|
{ "ebx", offsetof(CPUX86State, regs[3]) },
|
||||||
|
{ "esp|sp", offsetof(CPUX86State, regs[4]) },
|
||||||
|
{ "ebp|fp", offsetof(CPUX86State, regs[5]) },
|
||||||
|
{ "esi", offsetof(CPUX86State, regs[6]) },
|
||||||
|
{ "edi", offsetof(CPUX86State, regs[7]) },
|
||||||
|
#ifdef TARGET_X86_64
|
||||||
|
{ "r8", offsetof(CPUX86State, regs[8]) },
|
||||||
|
{ "r9", offsetof(CPUX86State, regs[9]) },
|
||||||
|
{ "r10", offsetof(CPUX86State, regs[10]) },
|
||||||
|
{ "r11", offsetof(CPUX86State, regs[11]) },
|
||||||
|
{ "r12", offsetof(CPUX86State, regs[12]) },
|
||||||
|
{ "r13", offsetof(CPUX86State, regs[13]) },
|
||||||
|
{ "r14", offsetof(CPUX86State, regs[14]) },
|
||||||
|
{ "r15", offsetof(CPUX86State, regs[15]) },
|
||||||
|
#endif
|
||||||
|
{ "eflags", offsetof(CPUX86State, eflags) },
|
||||||
|
{ "eip", offsetof(CPUX86State, eip) },
|
||||||
|
SEG("cs", R_CS)
|
||||||
|
SEG("ds", R_DS)
|
||||||
|
SEG("es", R_ES)
|
||||||
|
SEG("ss", R_SS)
|
||||||
|
SEG("fs", R_FS)
|
||||||
|
SEG("gs", R_GS)
|
||||||
|
{ "pc", 0, monitor_get_pc, },
|
||||||
|
{ NULL },
|
||||||
|
};
|
||||||
|
|
||||||
|
const MonitorDef *target_monitor_defs(void)
|
||||||
|
{
|
||||||
|
return monitor_defs;
|
||||||
|
}
|
||||||
@ -1,7 +1,7 @@
|
|||||||
obj-y += cpu-models.o
|
obj-y += cpu-models.o
|
||||||
obj-y += translate.o
|
obj-y += translate.o
|
||||||
ifeq ($(CONFIG_SOFTMMU),y)
|
ifeq ($(CONFIG_SOFTMMU),y)
|
||||||
obj-y += machine.o mmu_helper.o mmu-hash32.o
|
obj-y += machine.o mmu_helper.o mmu-hash32.o monitor.o
|
||||||
obj-$(TARGET_PPC64) += mmu-hash64.o arch_dump.o
|
obj-$(TARGET_PPC64) += mmu-hash64.o arch_dump.o
|
||||||
endif
|
endif
|
||||||
obj-$(CONFIG_KVM) += kvm.o kvm_ppc.o
|
obj-$(CONFIG_KVM) += kvm.o kvm_ppc.o
|
||||||
|
|||||||
255
target-ppc/monitor.c
Normal file
255
target-ppc/monitor.c
Normal file
@ -0,0 +1,255 @@
|
|||||||
|
/*
|
||||||
|
* QEMU monitor
|
||||||
|
*
|
||||||
|
* Copyright (c) 2003-2004 Fabrice Bellard
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||||
|
* of this software and associated documentation files (the "Software"), to deal
|
||||||
|
* in the Software without restriction, including without limitation the rights
|
||||||
|
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||||
|
* copies of the Software, and to permit persons to whom the Software is
|
||||||
|
* furnished to do so, subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in
|
||||||
|
* all copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||||
|
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||||
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||||
|
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||||
|
* THE SOFTWARE.
|
||||||
|
*/
|
||||||
|
#include "cpu.h"
|
||||||
|
#include "monitor/monitor.h"
|
||||||
|
#include "monitor/hmp-target.h"
|
||||||
|
#include "hmp.h"
|
||||||
|
|
||||||
|
static target_long monitor_get_ccr (const struct MonitorDef *md, int val)
|
||||||
|
{
|
||||||
|
CPUArchState *env = mon_get_cpu_env();
|
||||||
|
unsigned int u;
|
||||||
|
int i;
|
||||||
|
|
||||||
|
u = 0;
|
||||||
|
for (i = 0; i < 8; i++)
|
||||||
|
u |= env->crf[i] << (32 - (4 * (i + 1)));
|
||||||
|
|
||||||
|
return u;
|
||||||
|
}
|
||||||
|
|
||||||
|
static target_long monitor_get_msr (const struct MonitorDef *md, int val)
|
||||||
|
{
|
||||||
|
CPUArchState *env = mon_get_cpu_env();
|
||||||
|
return env->msr;
|
||||||
|
}
|
||||||
|
|
||||||
|
static target_long monitor_get_xer (const struct MonitorDef *md, int val)
|
||||||
|
{
|
||||||
|
CPUArchState *env = mon_get_cpu_env();
|
||||||
|
return env->xer;
|
||||||
|
}
|
||||||
|
|
||||||
|
static target_long monitor_get_decr (const struct MonitorDef *md, int val)
|
||||||
|
{
|
||||||
|
CPUArchState *env = mon_get_cpu_env();
|
||||||
|
return cpu_ppc_load_decr(env);
|
||||||
|
}
|
||||||
|
|
||||||
|
static target_long monitor_get_tbu (const struct MonitorDef *md, int val)
|
||||||
|
{
|
||||||
|
CPUArchState *env = mon_get_cpu_env();
|
||||||
|
return cpu_ppc_load_tbu(env);
|
||||||
|
}
|
||||||
|
|
||||||
|
static target_long monitor_get_tbl (const struct MonitorDef *md, int val)
|
||||||
|
{
|
||||||
|
CPUArchState *env = mon_get_cpu_env();
|
||||||
|
return cpu_ppc_load_tbl(env);
|
||||||
|
}
|
||||||
|
|
||||||
|
void hmp_info_tlb(Monitor *mon, const QDict *qdict)
|
||||||
|
{
|
||||||
|
CPUArchState *env1 = mon_get_cpu_env();
|
||||||
|
|
||||||
|
dump_mmu((FILE*)mon, (fprintf_function)monitor_printf, env1);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
const MonitorDef monitor_defs[] = {
|
||||||
|
/* General purpose registers */
|
||||||
|
{ "r0", offsetof(CPUPPCState, gpr[0]) },
|
||||||
|
{ "r1", offsetof(CPUPPCState, gpr[1]) },
|
||||||
|
{ "r2", offsetof(CPUPPCState, gpr[2]) },
|
||||||
|
{ "r3", offsetof(CPUPPCState, gpr[3]) },
|
||||||
|
{ "r4", offsetof(CPUPPCState, gpr[4]) },
|
||||||
|
{ "r5", offsetof(CPUPPCState, gpr[5]) },
|
||||||
|
{ "r6", offsetof(CPUPPCState, gpr[6]) },
|
||||||
|
{ "r7", offsetof(CPUPPCState, gpr[7]) },
|
||||||
|
{ "r8", offsetof(CPUPPCState, gpr[8]) },
|
||||||
|
{ "r9", offsetof(CPUPPCState, gpr[9]) },
|
||||||
|
{ "r10", offsetof(CPUPPCState, gpr[10]) },
|
||||||
|
{ "r11", offsetof(CPUPPCState, gpr[11]) },
|
||||||
|
{ "r12", offsetof(CPUPPCState, gpr[12]) },
|
||||||
|
{ "r13", offsetof(CPUPPCState, gpr[13]) },
|
||||||
|
{ "r14", offsetof(CPUPPCState, gpr[14]) },
|
||||||
|
{ "r15", offsetof(CPUPPCState, gpr[15]) },
|
||||||
|
{ "r16", offsetof(CPUPPCState, gpr[16]) },
|
||||||
|
{ "r17", offsetof(CPUPPCState, gpr[17]) },
|
||||||
|
{ "r18", offsetof(CPUPPCState, gpr[18]) },
|
||||||
|
{ "r19", offsetof(CPUPPCState, gpr[19]) },
|
||||||
|
{ "r20", offsetof(CPUPPCState, gpr[20]) },
|
||||||
|
{ "r21", offsetof(CPUPPCState, gpr[21]) },
|
||||||
|
{ "r22", offsetof(CPUPPCState, gpr[22]) },
|
||||||
|
{ "r23", offsetof(CPUPPCState, gpr[23]) },
|
||||||
|
{ "r24", offsetof(CPUPPCState, gpr[24]) },
|
||||||
|
{ "r25", offsetof(CPUPPCState, gpr[25]) },
|
||||||
|
{ "r26", offsetof(CPUPPCState, gpr[26]) },
|
||||||
|
{ "r27", offsetof(CPUPPCState, gpr[27]) },
|
||||||
|
{ "r28", offsetof(CPUPPCState, gpr[28]) },
|
||||||
|
{ "r29", offsetof(CPUPPCState, gpr[29]) },
|
||||||
|
{ "r30", offsetof(CPUPPCState, gpr[30]) },
|
||||||
|
{ "r31", offsetof(CPUPPCState, gpr[31]) },
|
||||||
|
/* Floating point registers */
|
||||||
|
{ "f0", offsetof(CPUPPCState, fpr[0]) },
|
||||||
|
{ "f1", offsetof(CPUPPCState, fpr[1]) },
|
||||||
|
{ "f2", offsetof(CPUPPCState, fpr[2]) },
|
||||||
|
{ "f3", offsetof(CPUPPCState, fpr[3]) },
|
||||||
|
{ "f4", offsetof(CPUPPCState, fpr[4]) },
|
||||||
|
{ "f5", offsetof(CPUPPCState, fpr[5]) },
|
||||||
|
{ "f6", offsetof(CPUPPCState, fpr[6]) },
|
||||||
|
{ "f7", offsetof(CPUPPCState, fpr[7]) },
|
||||||
|
{ "f8", offsetof(CPUPPCState, fpr[8]) },
|
||||||
|
{ "f9", offsetof(CPUPPCState, fpr[9]) },
|
||||||
|
{ "f10", offsetof(CPUPPCState, fpr[10]) },
|
||||||
|
{ "f11", offsetof(CPUPPCState, fpr[11]) },
|
||||||
|
{ "f12", offsetof(CPUPPCState, fpr[12]) },
|
||||||
|
{ "f13", offsetof(CPUPPCState, fpr[13]) },
|
||||||
|
{ "f14", offsetof(CPUPPCState, fpr[14]) },
|
||||||
|
{ "f15", offsetof(CPUPPCState, fpr[15]) },
|
||||||
|
{ "f16", offsetof(CPUPPCState, fpr[16]) },
|
||||||
|
{ "f17", offsetof(CPUPPCState, fpr[17]) },
|
||||||
|
{ "f18", offsetof(CPUPPCState, fpr[18]) },
|
||||||
|
{ "f19", offsetof(CPUPPCState, fpr[19]) },
|
||||||
|
{ "f20", offsetof(CPUPPCState, fpr[20]) },
|
||||||
|
{ "f21", offsetof(CPUPPCState, fpr[21]) },
|
||||||
|
{ "f22", offsetof(CPUPPCState, fpr[22]) },
|
||||||
|
{ "f23", offsetof(CPUPPCState, fpr[23]) },
|
||||||
|
{ "f24", offsetof(CPUPPCState, fpr[24]) },
|
||||||
|
{ "f25", offsetof(CPUPPCState, fpr[25]) },
|
||||||
|
{ "f26", offsetof(CPUPPCState, fpr[26]) },
|
||||||
|
{ "f27", offsetof(CPUPPCState, fpr[27]) },
|
||||||
|
{ "f28", offsetof(CPUPPCState, fpr[28]) },
|
||||||
|
{ "f29", offsetof(CPUPPCState, fpr[29]) },
|
||||||
|
{ "f30", offsetof(CPUPPCState, fpr[30]) },
|
||||||
|
{ "f31", offsetof(CPUPPCState, fpr[31]) },
|
||||||
|
{ "fpscr", offsetof(CPUPPCState, fpscr) },
|
||||||
|
/* Next instruction pointer */
|
||||||
|
{ "nip|pc", offsetof(CPUPPCState, nip) },
|
||||||
|
{ "lr", offsetof(CPUPPCState, lr) },
|
||||||
|
{ "ctr", offsetof(CPUPPCState, ctr) },
|
||||||
|
{ "decr", 0, &monitor_get_decr, },
|
||||||
|
{ "ccr", 0, &monitor_get_ccr, },
|
||||||
|
/* Machine state register */
|
||||||
|
{ "msr", 0, &monitor_get_msr, },
|
||||||
|
{ "xer", 0, &monitor_get_xer, },
|
||||||
|
{ "tbu", 0, &monitor_get_tbu, },
|
||||||
|
{ "tbl", 0, &monitor_get_tbl, },
|
||||||
|
/* Segment registers */
|
||||||
|
{ "sdr1", offsetof(CPUPPCState, spr[SPR_SDR1]) },
|
||||||
|
{ "sr0", offsetof(CPUPPCState, sr[0]) },
|
||||||
|
{ "sr1", offsetof(CPUPPCState, sr[1]) },
|
||||||
|
{ "sr2", offsetof(CPUPPCState, sr[2]) },
|
||||||
|
{ "sr3", offsetof(CPUPPCState, sr[3]) },
|
||||||
|
{ "sr4", offsetof(CPUPPCState, sr[4]) },
|
||||||
|
{ "sr5", offsetof(CPUPPCState, sr[5]) },
|
||||||
|
{ "sr6", offsetof(CPUPPCState, sr[6]) },
|
||||||
|
{ "sr7", offsetof(CPUPPCState, sr[7]) },
|
||||||
|
{ "sr8", offsetof(CPUPPCState, sr[8]) },
|
||||||
|
{ "sr9", offsetof(CPUPPCState, sr[9]) },
|
||||||
|
{ "sr10", offsetof(CPUPPCState, sr[10]) },
|
||||||
|
{ "sr11", offsetof(CPUPPCState, sr[11]) },
|
||||||
|
{ "sr12", offsetof(CPUPPCState, sr[12]) },
|
||||||
|
{ "sr13", offsetof(CPUPPCState, sr[13]) },
|
||||||
|
{ "sr14", offsetof(CPUPPCState, sr[14]) },
|
||||||
|
{ "sr15", offsetof(CPUPPCState, sr[15]) },
|
||||||
|
/* Too lazy to put BATs... */
|
||||||
|
{ "pvr", offsetof(CPUPPCState, spr[SPR_PVR]) },
|
||||||
|
|
||||||
|
{ "srr0", offsetof(CPUPPCState, spr[SPR_SRR0]) },
|
||||||
|
{ "srr1", offsetof(CPUPPCState, spr[SPR_SRR1]) },
|
||||||
|
{ "dar", offsetof(CPUPPCState, spr[SPR_DAR]) },
|
||||||
|
{ "dsisr", offsetof(CPUPPCState, spr[SPR_DSISR]) },
|
||||||
|
{ "cfar", offsetof(CPUPPCState, spr[SPR_CFAR]) },
|
||||||
|
{ "sprg0", offsetof(CPUPPCState, spr[SPR_SPRG0]) },
|
||||||
|
{ "sprg1", offsetof(CPUPPCState, spr[SPR_SPRG1]) },
|
||||||
|
{ "sprg2", offsetof(CPUPPCState, spr[SPR_SPRG2]) },
|
||||||
|
{ "sprg3", offsetof(CPUPPCState, spr[SPR_SPRG3]) },
|
||||||
|
{ "sprg4", offsetof(CPUPPCState, spr[SPR_SPRG4]) },
|
||||||
|
{ "sprg5", offsetof(CPUPPCState, spr[SPR_SPRG5]) },
|
||||||
|
{ "sprg6", offsetof(CPUPPCState, spr[SPR_SPRG6]) },
|
||||||
|
{ "sprg7", offsetof(CPUPPCState, spr[SPR_SPRG7]) },
|
||||||
|
{ "pid", offsetof(CPUPPCState, spr[SPR_BOOKE_PID]) },
|
||||||
|
{ "csrr0", offsetof(CPUPPCState, spr[SPR_BOOKE_CSRR0]) },
|
||||||
|
{ "csrr1", offsetof(CPUPPCState, spr[SPR_BOOKE_CSRR1]) },
|
||||||
|
{ "esr", offsetof(CPUPPCState, spr[SPR_BOOKE_ESR]) },
|
||||||
|
{ "dear", offsetof(CPUPPCState, spr[SPR_BOOKE_DEAR]) },
|
||||||
|
{ "mcsr", offsetof(CPUPPCState, spr[SPR_BOOKE_MCSR]) },
|
||||||
|
{ "tsr", offsetof(CPUPPCState, spr[SPR_BOOKE_TSR]) },
|
||||||
|
{ "tcr", offsetof(CPUPPCState, spr[SPR_BOOKE_TCR]) },
|
||||||
|
{ "vrsave", offsetof(CPUPPCState, spr[SPR_VRSAVE]) },
|
||||||
|
{ "pir", offsetof(CPUPPCState, spr[SPR_BOOKE_PIR]) },
|
||||||
|
{ "mcsrr0", offsetof(CPUPPCState, spr[SPR_BOOKE_MCSRR0]) },
|
||||||
|
{ "mcsrr1", offsetof(CPUPPCState, spr[SPR_BOOKE_MCSRR1]) },
|
||||||
|
{ "decar", offsetof(CPUPPCState, spr[SPR_BOOKE_DECAR]) },
|
||||||
|
{ "ivpr", offsetof(CPUPPCState, spr[SPR_BOOKE_IVPR]) },
|
||||||
|
{ "epcr", offsetof(CPUPPCState, spr[SPR_BOOKE_EPCR]) },
|
||||||
|
{ "sprg8", offsetof(CPUPPCState, spr[SPR_BOOKE_SPRG8]) },
|
||||||
|
{ "ivor0", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR0]) },
|
||||||
|
{ "ivor1", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR1]) },
|
||||||
|
{ "ivor2", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR2]) },
|
||||||
|
{ "ivor3", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR3]) },
|
||||||
|
{ "ivor4", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR4]) },
|
||||||
|
{ "ivor5", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR5]) },
|
||||||
|
{ "ivor6", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR6]) },
|
||||||
|
{ "ivor7", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR7]) },
|
||||||
|
{ "ivor8", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR8]) },
|
||||||
|
{ "ivor9", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR9]) },
|
||||||
|
{ "ivor10", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR10]) },
|
||||||
|
{ "ivor11", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR11]) },
|
||||||
|
{ "ivor12", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR12]) },
|
||||||
|
{ "ivor13", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR13]) },
|
||||||
|
{ "ivor14", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR14]) },
|
||||||
|
{ "ivor15", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR15]) },
|
||||||
|
{ "ivor32", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR32]) },
|
||||||
|
{ "ivor33", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR33]) },
|
||||||
|
{ "ivor34", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR34]) },
|
||||||
|
{ "ivor35", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR35]) },
|
||||||
|
{ "ivor36", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR36]) },
|
||||||
|
{ "ivor37", offsetof(CPUPPCState, spr[SPR_BOOKE_IVOR37]) },
|
||||||
|
{ "mas0", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS0]) },
|
||||||
|
{ "mas1", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS1]) },
|
||||||
|
{ "mas2", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS2]) },
|
||||||
|
{ "mas3", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS3]) },
|
||||||
|
{ "mas4", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS4]) },
|
||||||
|
{ "mas6", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS6]) },
|
||||||
|
{ "mas7", offsetof(CPUPPCState, spr[SPR_BOOKE_MAS7]) },
|
||||||
|
{ "mmucfg", offsetof(CPUPPCState, spr[SPR_MMUCFG]) },
|
||||||
|
{ "tlb0cfg", offsetof(CPUPPCState, spr[SPR_BOOKE_TLB0CFG]) },
|
||||||
|
{ "tlb1cfg", offsetof(CPUPPCState, spr[SPR_BOOKE_TLB1CFG]) },
|
||||||
|
{ "epr", offsetof(CPUPPCState, spr[SPR_BOOKE_EPR]) },
|
||||||
|
{ "eplc", offsetof(CPUPPCState, spr[SPR_BOOKE_EPLC]) },
|
||||||
|
{ "epsc", offsetof(CPUPPCState, spr[SPR_BOOKE_EPSC]) },
|
||||||
|
{ "svr", offsetof(CPUPPCState, spr[SPR_E500_SVR]) },
|
||||||
|
{ "mcar", offsetof(CPUPPCState, spr[SPR_Exxx_MCAR]) },
|
||||||
|
{ "pid1", offsetof(CPUPPCState, spr[SPR_BOOKE_PID1]) },
|
||||||
|
{ "pid2", offsetof(CPUPPCState, spr[SPR_BOOKE_PID2]) },
|
||||||
|
{ "hid0", offsetof(CPUPPCState, spr[SPR_HID0]) },
|
||||||
|
{ NULL },
|
||||||
|
};
|
||||||
|
|
||||||
|
const MonitorDef *target_monitor_defs(void)
|
||||||
|
{
|
||||||
|
return monitor_defs;
|
||||||
|
}
|
||||||
@ -1,2 +1,3 @@
|
|||||||
obj-y += translate.o op_helper.o helper.o cpu.o
|
obj-y += translate.o op_helper.o helper.o cpu.o
|
||||||
|
obj-$(CONFIG_SOFTMMU) += monitor.o
|
||||||
obj-y += gdbstub.o
|
obj-y += gdbstub.o
|
||||||
|
|||||||
52
target-sh4/monitor.c
Normal file
52
target-sh4/monitor.c
Normal file
@ -0,0 +1,52 @@
|
|||||||
|
/*
|
||||||
|
* QEMU monitor
|
||||||
|
*
|
||||||
|
* Copyright (c) 2003-2004 Fabrice Bellard
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||||
|
* of this software and associated documentation files (the "Software"), to deal
|
||||||
|
* in the Software without restriction, including without limitation the rights
|
||||||
|
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||||
|
* copies of the Software, and to permit persons to whom the Software is
|
||||||
|
* furnished to do so, subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in
|
||||||
|
* all copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||||
|
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||||
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||||
|
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||||
|
* THE SOFTWARE.
|
||||||
|
*/
|
||||||
|
#include "cpu.h"
|
||||||
|
#include "monitor/monitor.h"
|
||||||
|
#include "monitor/hmp-target.h"
|
||||||
|
#include "hmp.h"
|
||||||
|
|
||||||
|
static void print_tlb(Monitor *mon, int idx, tlb_t *tlb)
|
||||||
|
{
|
||||||
|
monitor_printf(mon, " tlb%i:\t"
|
||||||
|
"asid=%hhu vpn=%x\tppn=%x\tsz=%hhu size=%u\t"
|
||||||
|
"v=%hhu shared=%hhu cached=%hhu prot=%hhu "
|
||||||
|
"dirty=%hhu writethrough=%hhu\n",
|
||||||
|
idx,
|
||||||
|
tlb->asid, tlb->vpn, tlb->ppn, tlb->sz, tlb->size,
|
||||||
|
tlb->v, tlb->sh, tlb->c, tlb->pr,
|
||||||
|
tlb->d, tlb->wt);
|
||||||
|
}
|
||||||
|
|
||||||
|
void hmp_info_tlb(Monitor *mon, const QDict *qdict)
|
||||||
|
{
|
||||||
|
CPUArchState *env = mon_get_cpu_env();
|
||||||
|
int i;
|
||||||
|
|
||||||
|
monitor_printf (mon, "ITLB:\n");
|
||||||
|
for (i = 0 ; i < ITLB_SIZE ; i++)
|
||||||
|
print_tlb (mon, i, &env->itlb[i]);
|
||||||
|
monitor_printf (mon, "UTLB:\n");
|
||||||
|
for (i = 0 ; i < UTLB_SIZE ; i++)
|
||||||
|
print_tlb (mon, i, &env->utlb[i]);
|
||||||
|
}
|
||||||
@ -1,4 +1,4 @@
|
|||||||
obj-$(CONFIG_SOFTMMU) += machine.o
|
obj-$(CONFIG_SOFTMMU) += machine.o monitor.o
|
||||||
obj-y += translate.o helper.o cpu.o
|
obj-y += translate.o helper.o cpu.o
|
||||||
obj-y += fop_helper.o cc_helper.o win_helper.o mmu_helper.o ldst_helper.o
|
obj-y += fop_helper.o cc_helper.o win_helper.o mmu_helper.o ldst_helper.o
|
||||||
obj-$(TARGET_SPARC) += int32_helper.o
|
obj-$(TARGET_SPARC) += int32_helper.o
|
||||||
|
|||||||
158
target-sparc/monitor.c
Normal file
158
target-sparc/monitor.c
Normal file
@ -0,0 +1,158 @@
|
|||||||
|
/*
|
||||||
|
* QEMU monitor
|
||||||
|
*
|
||||||
|
* Copyright (c) 2003-2004 Fabrice Bellard
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||||
|
* of this software and associated documentation files (the "Software"), to deal
|
||||||
|
* in the Software without restriction, including without limitation the rights
|
||||||
|
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||||
|
* copies of the Software, and to permit persons to whom the Software is
|
||||||
|
* furnished to do so, subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in
|
||||||
|
* all copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||||
|
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||||
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||||
|
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||||
|
* THE SOFTWARE.
|
||||||
|
*/
|
||||||
|
#include "cpu.h"
|
||||||
|
#include "monitor/monitor.h"
|
||||||
|
#include "monitor/hmp-target.h"
|
||||||
|
#include "hmp.h"
|
||||||
|
|
||||||
|
|
||||||
|
void hmp_info_tlb(Monitor *mon, const QDict *qdict)
|
||||||
|
{
|
||||||
|
CPUArchState *env1 = mon_get_cpu_env();
|
||||||
|
|
||||||
|
dump_mmu((FILE*)mon, (fprintf_function)monitor_printf, env1);
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifndef TARGET_SPARC64
|
||||||
|
static target_long monitor_get_psr (const struct MonitorDef *md, int val)
|
||||||
|
{
|
||||||
|
CPUArchState *env = mon_get_cpu_env();
|
||||||
|
|
||||||
|
return cpu_get_psr(env);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
static target_long monitor_get_reg(const struct MonitorDef *md, int val)
|
||||||
|
{
|
||||||
|
CPUArchState *env = mon_get_cpu_env();
|
||||||
|
return env->regwptr[val];
|
||||||
|
}
|
||||||
|
|
||||||
|
const MonitorDef monitor_defs[] = {
|
||||||
|
{ "g0", offsetof(CPUSPARCState, gregs[0]) },
|
||||||
|
{ "g1", offsetof(CPUSPARCState, gregs[1]) },
|
||||||
|
{ "g2", offsetof(CPUSPARCState, gregs[2]) },
|
||||||
|
{ "g3", offsetof(CPUSPARCState, gregs[3]) },
|
||||||
|
{ "g4", offsetof(CPUSPARCState, gregs[4]) },
|
||||||
|
{ "g5", offsetof(CPUSPARCState, gregs[5]) },
|
||||||
|
{ "g6", offsetof(CPUSPARCState, gregs[6]) },
|
||||||
|
{ "g7", offsetof(CPUSPARCState, gregs[7]) },
|
||||||
|
{ "o0", 0, monitor_get_reg },
|
||||||
|
{ "o1", 1, monitor_get_reg },
|
||||||
|
{ "o2", 2, monitor_get_reg },
|
||||||
|
{ "o3", 3, monitor_get_reg },
|
||||||
|
{ "o4", 4, monitor_get_reg },
|
||||||
|
{ "o5", 5, monitor_get_reg },
|
||||||
|
{ "o6", 6, monitor_get_reg },
|
||||||
|
{ "o7", 7, monitor_get_reg },
|
||||||
|
{ "l0", 8, monitor_get_reg },
|
||||||
|
{ "l1", 9, monitor_get_reg },
|
||||||
|
{ "l2", 10, monitor_get_reg },
|
||||||
|
{ "l3", 11, monitor_get_reg },
|
||||||
|
{ "l4", 12, monitor_get_reg },
|
||||||
|
{ "l5", 13, monitor_get_reg },
|
||||||
|
{ "l6", 14, monitor_get_reg },
|
||||||
|
{ "l7", 15, monitor_get_reg },
|
||||||
|
{ "i0", 16, monitor_get_reg },
|
||||||
|
{ "i1", 17, monitor_get_reg },
|
||||||
|
{ "i2", 18, monitor_get_reg },
|
||||||
|
{ "i3", 19, monitor_get_reg },
|
||||||
|
{ "i4", 20, monitor_get_reg },
|
||||||
|
{ "i5", 21, monitor_get_reg },
|
||||||
|
{ "i6", 22, monitor_get_reg },
|
||||||
|
{ "i7", 23, monitor_get_reg },
|
||||||
|
{ "pc", offsetof(CPUSPARCState, pc) },
|
||||||
|
{ "npc", offsetof(CPUSPARCState, npc) },
|
||||||
|
{ "y", offsetof(CPUSPARCState, y) },
|
||||||
|
#ifndef TARGET_SPARC64
|
||||||
|
{ "psr", 0, &monitor_get_psr, },
|
||||||
|
{ "wim", offsetof(CPUSPARCState, wim) },
|
||||||
|
#endif
|
||||||
|
{ "tbr", offsetof(CPUSPARCState, tbr) },
|
||||||
|
{ "fsr", offsetof(CPUSPARCState, fsr) },
|
||||||
|
{ "f0", offsetof(CPUSPARCState, fpr[0].l.upper) },
|
||||||
|
{ "f1", offsetof(CPUSPARCState, fpr[0].l.lower) },
|
||||||
|
{ "f2", offsetof(CPUSPARCState, fpr[1].l.upper) },
|
||||||
|
{ "f3", offsetof(CPUSPARCState, fpr[1].l.lower) },
|
||||||
|
{ "f4", offsetof(CPUSPARCState, fpr[2].l.upper) },
|
||||||
|
{ "f5", offsetof(CPUSPARCState, fpr[2].l.lower) },
|
||||||
|
{ "f6", offsetof(CPUSPARCState, fpr[3].l.upper) },
|
||||||
|
{ "f7", offsetof(CPUSPARCState, fpr[3].l.lower) },
|
||||||
|
{ "f8", offsetof(CPUSPARCState, fpr[4].l.upper) },
|
||||||
|
{ "f9", offsetof(CPUSPARCState, fpr[4].l.lower) },
|
||||||
|
{ "f10", offsetof(CPUSPARCState, fpr[5].l.upper) },
|
||||||
|
{ "f11", offsetof(CPUSPARCState, fpr[5].l.lower) },
|
||||||
|
{ "f12", offsetof(CPUSPARCState, fpr[6].l.upper) },
|
||||||
|
{ "f13", offsetof(CPUSPARCState, fpr[6].l.lower) },
|
||||||
|
{ "f14", offsetof(CPUSPARCState, fpr[7].l.upper) },
|
||||||
|
{ "f15", offsetof(CPUSPARCState, fpr[7].l.lower) },
|
||||||
|
{ "f16", offsetof(CPUSPARCState, fpr[8].l.upper) },
|
||||||
|
{ "f17", offsetof(CPUSPARCState, fpr[8].l.lower) },
|
||||||
|
{ "f18", offsetof(CPUSPARCState, fpr[9].l.upper) },
|
||||||
|
{ "f19", offsetof(CPUSPARCState, fpr[9].l.lower) },
|
||||||
|
{ "f20", offsetof(CPUSPARCState, fpr[10].l.upper) },
|
||||||
|
{ "f21", offsetof(CPUSPARCState, fpr[10].l.lower) },
|
||||||
|
{ "f22", offsetof(CPUSPARCState, fpr[11].l.upper) },
|
||||||
|
{ "f23", offsetof(CPUSPARCState, fpr[11].l.lower) },
|
||||||
|
{ "f24", offsetof(CPUSPARCState, fpr[12].l.upper) },
|
||||||
|
{ "f25", offsetof(CPUSPARCState, fpr[12].l.lower) },
|
||||||
|
{ "f26", offsetof(CPUSPARCState, fpr[13].l.upper) },
|
||||||
|
{ "f27", offsetof(CPUSPARCState, fpr[13].l.lower) },
|
||||||
|
{ "f28", offsetof(CPUSPARCState, fpr[14].l.upper) },
|
||||||
|
{ "f29", offsetof(CPUSPARCState, fpr[14].l.lower) },
|
||||||
|
{ "f30", offsetof(CPUSPARCState, fpr[15].l.upper) },
|
||||||
|
{ "f31", offsetof(CPUSPARCState, fpr[15].l.lower) },
|
||||||
|
#ifdef TARGET_SPARC64
|
||||||
|
{ "f32", offsetof(CPUSPARCState, fpr[16]) },
|
||||||
|
{ "f34", offsetof(CPUSPARCState, fpr[17]) },
|
||||||
|
{ "f36", offsetof(CPUSPARCState, fpr[18]) },
|
||||||
|
{ "f38", offsetof(CPUSPARCState, fpr[19]) },
|
||||||
|
{ "f40", offsetof(CPUSPARCState, fpr[20]) },
|
||||||
|
{ "f42", offsetof(CPUSPARCState, fpr[21]) },
|
||||||
|
{ "f44", offsetof(CPUSPARCState, fpr[22]) },
|
||||||
|
{ "f46", offsetof(CPUSPARCState, fpr[23]) },
|
||||||
|
{ "f48", offsetof(CPUSPARCState, fpr[24]) },
|
||||||
|
{ "f50", offsetof(CPUSPARCState, fpr[25]) },
|
||||||
|
{ "f52", offsetof(CPUSPARCState, fpr[26]) },
|
||||||
|
{ "f54", offsetof(CPUSPARCState, fpr[27]) },
|
||||||
|
{ "f56", offsetof(CPUSPARCState, fpr[28]) },
|
||||||
|
{ "f58", offsetof(CPUSPARCState, fpr[29]) },
|
||||||
|
{ "f60", offsetof(CPUSPARCState, fpr[30]) },
|
||||||
|
{ "f62", offsetof(CPUSPARCState, fpr[31]) },
|
||||||
|
{ "asi", offsetof(CPUSPARCState, asi) },
|
||||||
|
{ "pstate", offsetof(CPUSPARCState, pstate) },
|
||||||
|
{ "cansave", offsetof(CPUSPARCState, cansave) },
|
||||||
|
{ "canrestore", offsetof(CPUSPARCState, canrestore) },
|
||||||
|
{ "otherwin", offsetof(CPUSPARCState, otherwin) },
|
||||||
|
{ "wstate", offsetof(CPUSPARCState, wstate) },
|
||||||
|
{ "cleanwin", offsetof(CPUSPARCState, cleanwin) },
|
||||||
|
{ "fprs", offsetof(CPUSPARCState, fprs) },
|
||||||
|
#endif
|
||||||
|
{ NULL },
|
||||||
|
};
|
||||||
|
|
||||||
|
const MonitorDef *target_monitor_defs(void)
|
||||||
|
{
|
||||||
|
return monitor_defs;
|
||||||
|
}
|
||||||
@ -2,5 +2,6 @@ obj-y += xtensa-semi.o
|
|||||||
obj-y += core-dc232b.o
|
obj-y += core-dc232b.o
|
||||||
obj-y += core-dc233c.o
|
obj-y += core-dc233c.o
|
||||||
obj-y += core-fsf.o
|
obj-y += core-fsf.o
|
||||||
|
obj-$(CONFIG_SOFTMMU) += monitor.o
|
||||||
obj-y += translate.o op_helper.o helper.o cpu.o
|
obj-y += translate.o op_helper.o helper.o cpu.o
|
||||||
obj-y += gdbstub.o
|
obj-y += gdbstub.o
|
||||||
|
|||||||
34
target-xtensa/monitor.c
Normal file
34
target-xtensa/monitor.c
Normal file
@ -0,0 +1,34 @@
|
|||||||
|
/*
|
||||||
|
* QEMU monitor
|
||||||
|
*
|
||||||
|
* Copyright (c) 2003-2004 Fabrice Bellard
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||||
|
* of this software and associated documentation files (the "Software"), to deal
|
||||||
|
* in the Software without restriction, including without limitation the rights
|
||||||
|
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||||
|
* copies of the Software, and to permit persons to whom the Software is
|
||||||
|
* furnished to do so, subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in
|
||||||
|
* all copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||||
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||||
|
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||||
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||||
|
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||||
|
* THE SOFTWARE.
|
||||||
|
*/
|
||||||
|
#include "cpu.h"
|
||||||
|
#include "monitor/monitor.h"
|
||||||
|
#include "monitor/hmp-target.h"
|
||||||
|
#include "hmp.h"
|
||||||
|
|
||||||
|
void hmp_info_tlb(Monitor *mon, const QDict *qdict)
|
||||||
|
{
|
||||||
|
CPUArchState *env1 = mon_get_cpu_env();
|
||||||
|
|
||||||
|
dump_mmu((FILE*)mon, (fprintf_function)monitor_printf, env1);
|
||||||
|
}
|
||||||
Loading…
Reference in New Issue
Block a user