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target/arm: Factor out code for setting MTE TCF0 field 

Factor out the code used for setting the MTE TCF0 field from the prctl
code into a convenient function. Other subsystems, like gdbstub, need to
set this field as well, so keep it as a separate function to avoid
duplication and ensure consistency in how this field is set across the
board.

Signed-off-by: Gustavo Romero <gustavo.romero@linaro.org>
Message-Id: <20240628050850.536447-7-gustavo.romero@linaro.org>
[AJB: clean-up includes, move MTE defines]
Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20240705084047.857176-36-alex.bennee@linaro.org>
This commit is contained in:
Gustavo Romero 2024-07-05 09:40:42 +01:00 committed by Alex Bennée
parent 0c9b437c90
commit bef6a77f6d
5 changed files with 71 additions and 29 deletions
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2
linux-user/aarch64/meson.build
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@ -9,3 +9,5 @@ vdso_le_inc = gen_vdso.process('vdso-le.so',
extra_args: ['-r', '__kernel_rt_sigreturn'])
linux_user_ss.add(when: 'TARGET_AARCH64', if_true: [vdso_be_inc, vdso_le_inc])
linux_user_ss.add(when: 'TARGET_AARCH64', if_true: [files('mte_user_helper.c')])

35
linux-user/aarch64/mte_user_helper.c Normal file
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@ -0,0 +1,35 @@
/*
* ARM MemTag convenience functions.
*
* This code is licensed under the GNU GPL v2 or later.
*
* SPDX-License-Identifier: LGPL-2.1-or-later
*/
#include "qemu/osdep.h"
#include "qemu.h"
#include "mte_user_helper.h"
void arm_set_mte_tcf0(CPUArchState *env, abi_long value)
{
/*
* Write PR_MTE_TCF to SCTLR_EL1[TCF0].
*
* The kernel has a per-cpu configuration for the sysadmin,
* /sys/devices/system/cpu/cpu<N>/mte_tcf_preferred,
* which qemu does not implement.
*
* Because there is no performance difference between the modes, and
* because SYNC is most useful for debugging MTE errors, choose SYNC
* as the preferred mode. With this preference, and the way the API
* uses only two bits, there is no way for the program to select
* ASYMM mode.
*/
unsigned tcf = 0;
if (value & PR_MTE_TCF_SYNC) {
tcf = 1;
} else if (value & PR_MTE_TCF_ASYNC) {
tcf = 2;
}
env->cp15.sctlr_el[1] = deposit64(env->cp15.sctlr_el[1], 38, 2, tcf);
}

32
linux-user/aarch64/mte_user_helper.h Normal file
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@ -0,0 +1,32 @@
/*
* ARM MemTag convenience functions.
*
* This code is licensed under the GNU GPL v2 or later.
*
* SPDX-License-Identifier: LGPL-2.1-or-later
*/
#ifndef AARCH64_MTE_USER_HELPER_H
#define AARCH64_MTE USER_HELPER_H
#ifndef PR_MTE_TCF_SHIFT
# define PR_MTE_TCF_SHIFT 1
# define PR_MTE_TCF_NONE (0UL << PR_MTE_TCF_SHIFT)
# define PR_MTE_TCF_SYNC (1UL << PR_MTE_TCF_SHIFT)
# define PR_MTE_TCF_ASYNC (2UL << PR_MTE_TCF_SHIFT)
# define PR_MTE_TCF_MASK (3UL << PR_MTE_TCF_SHIFT)
# define PR_MTE_TAG_SHIFT 3
# define PR_MTE_TAG_MASK (0xffffUL << PR_MTE_TAG_SHIFT)
#endif
/**
* arm_set_mte_tcf0 - Set TCF0 field in SCTLR_EL1 register
* @env: The CPU environment
* @value: The value to be set for the Tag Check Fault in EL0 field.
*
* Only SYNC and ASYNC modes can be selected. If ASYMM mode is given, the SYNC
* mode is selected instead. So, there is no way to set the ASYMM mode.
*/
void arm_set_mte_tcf0(CPUArchState *env, abi_long value);
#endif /* AARCH64_MTE_USER_HELPER_H */

22
linux-user/aarch64/target_prctl.h
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@ -7,6 +7,7 @@
#define AARCH64_TARGET_PRCTL_H
#include "target/arm/cpu-features.h"
#include "mte_user_helper.h"
static abi_long do_prctl_sve_get_vl(CPUArchState *env)
{
@ -173,26 +174,7 @@ static abi_long do_prctl_set_tagged_addr_ctrl(CPUArchState *env, abi_long arg2)
env->tagged_addr_enable = arg2 & PR_TAGGED_ADDR_ENABLE;
if (cpu_isar_feature(aa64_mte, cpu)) {
/*
* Write PR_MTE_TCF to SCTLR_EL1[TCF0].
*
* The kernel has a per-cpu configuration for the sysadmin,
* /sys/devices/system/cpu/cpu<N>/mte_tcf_preferred,
* which qemu does not implement.
*
* Because there is no performance difference between the modes, and
* because SYNC is most useful for debugging MTE errors, choose SYNC
* as the preferred mode. With this preference, and the way the API
* uses only two bits, there is no way for the program to select
* ASYMM mode.
*/
unsigned tcf = 0;
if (arg2 & PR_MTE_TCF_SYNC) {
tcf = 1;
} else if (arg2 & PR_MTE_TCF_ASYNC) {
tcf = 2;
}
env->cp15.sctlr_el[1] = deposit64(env->cp15.sctlr_el[1], 38, 2, tcf);
arm_set_mte_tcf0(env, arg2);
/*
* Write PR_MTE_TAG to GCR_EL1[Exclude].

9
linux-user/syscall.c
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@ -6281,15 +6281,6 @@ abi_long do_arch_prctl(CPUX86State *env, int code, abi_ulong addr)
# define PR_GET_TAGGED_ADDR_CTRL 56
# define PR_TAGGED_ADDR_ENABLE (1UL << 0)
#endif
#ifndef PR_MTE_TCF_SHIFT
# define PR_MTE_TCF_SHIFT 1
# define PR_MTE_TCF_NONE (0UL << PR_MTE_TCF_SHIFT)
# define PR_MTE_TCF_SYNC (1UL << PR_MTE_TCF_SHIFT)
# define PR_MTE_TCF_ASYNC (2UL << PR_MTE_TCF_SHIFT)
# define PR_MTE_TCF_MASK (3UL << PR_MTE_TCF_SHIFT)
# define PR_MTE_TAG_SHIFT 3
# define PR_MTE_TAG_MASK (0xffffUL << PR_MTE_TAG_SHIFT)
#endif
#ifndef PR_SET_IO_FLUSHER
# define PR_SET_IO_FLUSHER 57
# define PR_GET_IO_FLUSHER 58