target-i386: add ABM to Haswell* and Broadwell* CPU models
ABM is only implemented as a single instruction set by AMD; all AMD processors support both instructions or neither. Intel considers POPCNT as part of SSE4.2, and LZCNT as part of BMI1, but Intel also uses AMD's ABM flag to indicate support for both POPCNT and LZCNT. It has to be added to Haswell and Broadwell because Haswell, by adding LZCNT, has completed the ABM. Tested with "qemu-kvm -cpu Haswell-noTSX,enforce" (and also with older machine types) on an Haswell-EP machine. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
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@ -298,7 +298,27 @@ int e820_get_num_entries(void);
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bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *);
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bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *);
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#define PC_COMPAT_2_4 \
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#define PC_COMPAT_2_4 \
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HW_COMPAT_2_4
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HW_COMPAT_2_4 \
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{\
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.driver = "Haswell-" TYPE_X86_CPU,\
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.property = "abm",\
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.value = "off",\
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},\
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{\
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.driver = "Haswell-noTSX-" TYPE_X86_CPU,\
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.property = "abm",\
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.value = "off",\
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},\
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{\
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.driver = "Broadwell-" TYPE_X86_CPU,\
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.property = "abm",\
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.value = "off",\
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},\
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{\
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.driver = "Broadwell-noTSX-" TYPE_X86_CPU,\
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.property = "abm",\
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.value = "off",\
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},
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#define PC_COMPAT_2_3 \
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#define PC_COMPAT_2_3 \
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PC_COMPAT_2_4 \
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PC_COMPAT_2_4 \
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@ -1081,7 +1081,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
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CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
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CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
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CPUID_EXT2_SYSCALL,
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CPUID_EXT2_SYSCALL,
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.features[FEAT_8000_0001_ECX] =
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.features[FEAT_8000_0001_ECX] =
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CPUID_EXT3_LAHF_LM,
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CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
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.features[FEAT_7_0_EBX] =
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.features[FEAT_7_0_EBX] =
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CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
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CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
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CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
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CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
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@ -1116,7 +1116,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
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CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
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CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
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CPUID_EXT2_SYSCALL,
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CPUID_EXT2_SYSCALL,
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.features[FEAT_8000_0001_ECX] =
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.features[FEAT_8000_0001_ECX] =
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CPUID_EXT3_LAHF_LM,
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CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
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.features[FEAT_7_0_EBX] =
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.features[FEAT_7_0_EBX] =
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CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
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CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
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CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
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CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
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@ -1153,7 +1153,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
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CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
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CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
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CPUID_EXT2_SYSCALL,
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CPUID_EXT2_SYSCALL,
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.features[FEAT_8000_0001_ECX] =
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.features[FEAT_8000_0001_ECX] =
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CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
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CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
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.features[FEAT_7_0_EBX] =
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.features[FEAT_7_0_EBX] =
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CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
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CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
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CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
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CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
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@ -1191,7 +1191,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
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CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
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CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
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CPUID_EXT2_SYSCALL,
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CPUID_EXT2_SYSCALL,
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.features[FEAT_8000_0001_ECX] =
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.features[FEAT_8000_0001_ECX] =
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CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
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CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
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.features[FEAT_7_0_EBX] =
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.features[FEAT_7_0_EBX] =
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CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
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CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
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CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
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CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
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