mirrors/qemu
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

acpi,pc,test bug fixes

Browse Source 
More small fixes: the issues annoy developers so
 I thought they are worth fixing quickly.
 
 Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQEcBAABAgAGBQJTHvMwAAoJECgfDbjSjVRp2SIH/Rh5X1U+tUjr0xnvWllXTgdP
 ixot7AxXO2UkmPqhyAPV/oEr/3xBFyp8C8ZysQzaHsUqDyq40DtkKp+UWvG6EjpY
 3Ser+wA9NzsT67ixtEIN2z1qnO7l29ErggS8EfTOh7gyFJzSKN8x3GV2ENB/FBJW
 k0LSO7aJ0rmTdg63u9T3RIctKPbtCBO8wlE6wuS461pBshYNr6aVkMWDY9bVpx/f
 ol/aoJs7xaPkJs1qFzOfOisYi3LeBZR4O9gRRixqzwJtwWl5rMG3y/oBxbYDfyZw
 NbP7zFAWCj/YYgG0U8L9SR4P28n65FoULAvQ9CRY1+fF7Ozwj0SzoU2Ld6fvINw=
 =VRRB
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging

acpi,pc,test bug fixes

More small fixes: the issues annoy developers so
I thought they are worth fixing quickly.

Signed-off-by: Michael S. Tsirkin <mst@redhat.com>

# gpg: Signature made Tue 11 Mar 2014 11:27:44 GMT using RSA key ID D28D5469
# gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>"
# gpg:                 aka "Michael S. Tsirkin <mst@redhat.com>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 0270 606B 6F3C DF3D 0B17  0970 C350 3912 AFBE 8E67
#      Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA  8A0D 281F 0DB8 D28D 5469

* remotes/mst/tags/for_upstream:
  acpi-test: update expected SSDT files
  acpi-build: don't access unaligned addresses
  q35: Correct typo BRDIGE -> BRIDGE
  configure: don't modify .status on error
  pc: avoid duplicate names for ROM MRs
  loader: rename in_ram/has_mr

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2014-03-11 19:52:32 +00:00
commit be813ef02d
11 changed files with 65 additions and 57 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

27
configure vendored
View File

@ -31,19 +31,6 @@ printf " '%s'" "$0" "$@" >> config.log
echo >> config.log
echo "#" >> config.log
# Save the configure command line for later reuse.
cat <<EOD >config.status
#!/bin/sh
# Generated by configure.
# Run this file to recreate the current configuration.
# Compiler output produced by configure, useful for debugging
# configure, is in config.log if it exists.
EOD
printf "exec" >>config.status
printf " '%s'" "$0" "$@" >>config.status
echo >>config.status
chmod +x config.status
error_exit() {
echo
echo "ERROR: $1"
@ -5146,3 +5133,17 @@ done
if test "$docs" = "yes" ; then
mkdir -p QMP
fi
# Save the configure command line for later reuse.
cat <<EOD >config.status
#!/bin/sh
# Generated by configure.
# Run this file to recreate the current configuration.
# Compiler output produced by configure, useful for debugging
# configure, is in config.log if it exists.
EOD
printf "exec" >>config.status
printf " '%s'" "$0" "$@" >>config.status
echo >>config.status
chmod +x config.status

14
hw/core/loader.c
View File

@ -54,7 +54,8 @@
#include <zlib.h>
bool rom_file_in_ram = true;
bool option_rom_has_mr = false;
bool rom_file_has_mr = true;
static int roms_loaded;
@ -642,7 +643,8 @@ static void *rom_set_mr(Rom *rom, Object *owner, const char *name)
}
int rom_add_file(const char *file, const char *fw_dir,
hwaddr addr, int32_t bootindex)
hwaddr addr, int32_t bootindex,
bool option_rom)
{
Rom *rom;
int rc, fd = -1;
@ -694,7 +696,7 @@ int rom_add_file(const char *file, const char *fw_dir,
basename);
snprintf(devpath, sizeof(devpath), "/rom@%s", fw_file_name);
if (rom_file_in_ram) {
if ((!option_rom || option_rom_has_mr) && rom_file_has_mr) {
data = rom_set_mr(rom, OBJECT(fw_cfg), devpath);
} else {
data = rom->data;
@ -738,7 +740,7 @@ void *rom_add_blob(const char *name, const void *blob, size_t len,
snprintf(devpath, sizeof(devpath), "/rom@%s", fw_file_name);
if (rom_file_in_ram) {
if (rom_file_has_mr) {
data = rom_set_mr(rom, OBJECT(fw_cfg), devpath);
} else {
data = rom->data;
@ -773,12 +775,12 @@ int rom_add_elf_program(const char *name, void *data, size_t datasize,
int rom_add_vga(const char *file)
{
return rom_add_file(file, "vgaroms", 0, -1);
return rom_add_file(file, "vgaroms", 0, -1, true);
}
int rom_add_option(const char *file, int32_t bootindex)
{
return rom_add_file(file, "genroms", 0, bootindex);
return rom_add_file(file, "genroms", 0, bootindex, true);
}
static void rom_reset(void *unused)

31
hw/i386/acpi-build.c
View File

@ -466,9 +466,15 @@ static void acpi_align_size(GArray *blob, unsigned align)
g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align));
}
/* Get pointer within table in a safe manner */
#define ACPI_BUILD_PTR(table, size, off, type) \
((type *)(acpi_data_get_ptr(table, size, off, sizeof(type))))
/* Set a value within table in a safe manner */
#define ACPI_BUILD_SET_LE(table, size, off, bits, val) \
do { \
uint64_t ACPI_BUILD_SET_LE_val = cpu_to_le64(val); \
memcpy(acpi_data_get_ptr(table, size, off, \
(bits) / BITS_PER_BYTE), \
&ACPI_BUILD_SET_LE_val, \
(bits) / BITS_PER_BYTE); \
} while (0)
static inline void *acpi_data_get_ptr(uint8_t *table_data, unsigned table_size,
unsigned off, unsigned size)
@ -974,22 +980,17 @@ static void build_pci_bus_end(PCIBus *bus, void *bus_state)
static void patch_pci_windows(PcPciInfo *pci, uint8_t *start, unsigned size)
{
*ACPI_BUILD_PTR(start, size, acpi_pci32_start[0], uint32_t) =
cpu_to_le32(pci->w32.begin);
ACPI_BUILD_SET_LE(start, size, acpi_pci32_start[0], 32, pci->w32.begin);
*ACPI_BUILD_PTR(start, size, acpi_pci32_end[0], uint32_t) =
cpu_to_le32(pci->w32.end - 1);
ACPI_BUILD_SET_LE(start, size, acpi_pci32_end[0], 32, pci->w32.end - 1);
if (pci->w64.end || pci->w64.begin) {
*ACPI_BUILD_PTR(start, size, acpi_pci64_valid[0], uint8_t) = 1;
*ACPI_BUILD_PTR(start, size, acpi_pci64_start[0], uint64_t) =
cpu_to_le64(pci->w64.begin);
*ACPI_BUILD_PTR(start, size, acpi_pci64_end[0], uint64_t) =
cpu_to_le64(pci->w64.end - 1);
*ACPI_BUILD_PTR(start, size, acpi_pci64_length[0], uint64_t) =
cpu_to_le64(pci->w64.end - pci->w64.begin);
ACPI_BUILD_SET_LE(start, size, acpi_pci64_valid[0], 8, 1);
ACPI_BUILD_SET_LE(start, size, acpi_pci64_start[0], 64, pci->w64.begin);
ACPI_BUILD_SET_LE(start, size, acpi_pci64_end[0], 64, pci->w64.end - 1);
ACPI_BUILD_SET_LE(start, size, acpi_pci64_length[0], 64, pci->w64.end - pci->w64.begin);
} else {
*ACPI_BUILD_PTR(start, size, acpi_pci64_valid[0], uint8_t) = 0;
ACPI_BUILD_SET_LE(start, size, acpi_pci64_valid[0], 8, 0);
}
}

3
hw/i386/pc_piix.c
View File

@ -266,13 +266,14 @@ static void pc_compat_1_7(QEMUMachineInitArgs *args)
{
smbios_type1_defaults = false;
gigabyte_align = false;
option_rom_has_mr = true;
}
static void pc_compat_1_6(QEMUMachineInitArgs *args)
{
pc_compat_1_7(args);
has_pci_info = false;
rom_file_in_ram = false;
rom_file_has_mr = false;
has_acpi_build = false;
}

3
hw/i386/pc_q35.c
View File

@ -244,13 +244,14 @@ static void pc_compat_1_7(QEMUMachineInitArgs *args)
{
smbios_type1_defaults = false;
gigabyte_align = false;
option_rom_has_mr = true;
}
static void pc_compat_1_6(QEMUMachineInitArgs *args)
{
pc_compat_1_7(args);
has_pci_info = false;
rom_file_in_ram = false;
rom_file_has_mr = false;
has_acpi_build = false;
}

10
hw/pci-host/q35.c
View File

@ -272,7 +272,7 @@ static void mch_update_smram(MCHPCIState *mch)
PCIDevice *pd = PCI_DEVICE(mch);
memory_region_transaction_begin();
smram_update(&mch->smram_region, pd->config[MCH_HOST_BRDIGE_SMRAM],
smram_update(&mch->smram_region, pd->config[MCH_HOST_BRIDGE_SMRAM],
mch->smm_enabled);
memory_region_transaction_commit();
}
@ -283,7 +283,7 @@ static void mch_set_smm(int smm, void *arg)
PCIDevice *pd = PCI_DEVICE(mch);
memory_region_transaction_begin();
smram_set_smm(&mch->smm_enabled, smm, pd->config[MCH_HOST_BRDIGE_SMRAM],
smram_set_smm(&mch->smm_enabled, smm, pd->config[MCH_HOST_BRIDGE_SMRAM],
&mch->smram_region);
memory_region_transaction_commit();
}
@ -306,8 +306,8 @@ static void mch_write_config(PCIDevice *d,
mch_update_pciexbar(mch);
}
if (ranges_overlap(address, len, MCH_HOST_BRDIGE_SMRAM,
MCH_HOST_BRDIGE_SMRAM_SIZE)) {
if (ranges_overlap(address, len, MCH_HOST_BRIDGE_SMRAM,
MCH_HOST_BRIDGE_SMRAM_SIZE)) {
mch_update_smram(mch);
}
}
@ -347,7 +347,7 @@ static void mch_reset(DeviceState *qdev)
pci_set_quad(d->config + MCH_HOST_BRIDGE_PCIEXBAR,
MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT);
d->config[MCH_HOST_BRDIGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT;
d->config[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT;
mch_update(mch);
}

2
include/hw/i386/ich9.h
View File

@ -102,7 +102,7 @@ Object *ich9_lpc_find(void);
#define ICH9_USB_UHCI1_DEV 29
#define ICH9_USB_UHCI1_FUNC 0
/* D30:F0 DMI-to-PCI brdige */
/* D30:F0 DMI-to-PCI bridge */
#define ICH9_D2P_BRIDGE "ICH9 D2P BRIDGE"
#define ICH9_D2P_BRIDGE_SAVEVM_VERSION 0

8
include/hw/loader.h
View File

@ -49,10 +49,12 @@ void pstrcpy_targphys(const char *name,
hwaddr dest, int buf_size,
const char *source);
extern bool rom_file_in_ram;
extern bool option_rom_has_mr;
extern bool rom_file_has_mr;
int rom_add_file(const char *file, const char *fw_dir,
hwaddr addr, int32_t bootindex);
hwaddr addr, int32_t bootindex,
bool option_rom);
void *rom_add_blob(const char *name, const void *blob, size_t len,
hwaddr addr, const char *fw_file_name,
FWCfgReadCallback fw_callback, void *callback_opaque);
@ -66,7 +68,7 @@ void *rom_ptr(hwaddr addr);
void do_info_roms(Monitor *mon, const QDict *qdict);
#define rom_add_file_fixed(_f, _a, _i) \
rom_add_file(_f, NULL, _a, _i)
rom_add_file(_f, NULL, _a, _i, false)
#define rom_add_blob_fixed(_f, _b, _l, _a) \
rom_add_blob(_f, _b, _l, _a, NULL, NULL, NULL)

24
include/hw/pci-host/q35.h
View File

@ -125,8 +125,8 @@ typedef struct Q35PCIHost {
#define MCH_HOST_BRIDGE_PAM_RE ((uint8_t)0x1)
#define MCH_HOST_BRIDGE_PAM_MASK ((uint8_t)0x3)
#define MCH_HOST_BRDIGE_SMRAM 0x9d
#define MCH_HOST_BRDIGE_SMRAM_SIZE 1
#define MCH_HOST_BRIDGE_SMRAM 0x9d
#define MCH_HOST_BRIDGE_SMRAM_SIZE 1
#define MCH_HOST_BRIDGE_SMRAM_DEFAULT ((uint8_t)0x2)
#define MCH_HOST_BRIDGE_SMRAM_D_OPEN ((uint8_t)(1 << 6))
#define MCH_HOST_BRIDGE_SMRAM_D_CLS ((uint8_t)(1 << 5))
@ -140,16 +140,16 @@ typedef struct Q35PCIHost {
#define MCH_HOST_BRIDGE_UPPER_SYSTEM_BIOS_END 0x100000
#define MCH_HOST_BRIDGE_ESMRAMC 0x9e
#define MCH_HOST_BRDIGE_ESMRAMC_H_SMRAME ((uint8_t)(1 << 6))
#define MCH_HOST_BRDIGE_ESMRAMC_E_SMERR ((uint8_t)(1 << 5))
#define MCH_HOST_BRDIGE_ESMRAMC_SM_CACHE ((uint8_t)(1 << 4))
#define MCH_HOST_BRDIGE_ESMRAMC_SM_L1 ((uint8_t)(1 << 3))
#define MCH_HOST_BRDIGE_ESMRAMC_SM_L2 ((uint8_t)(1 << 2))
#define MCH_HOST_BRDIGE_ESMRAMC_TSEG_SZ_MASK ((uint8_t)(0x3 << 1))
#define MCH_HOST_BRDIGE_ESMRAMC_TSEG_SZ_1MB ((uint8_t)(0x0 << 1))
#define MCH_HOST_BRDIGE_ESMRAMC_TSEG_SZ_2MB ((uint8_t)(0x1 << 1))
#define MCH_HOST_BRDIGE_ESMRAMC_TSEG_SZ_8MB ((uint8_t)(0x2 << 1))
#define MCH_HOST_BRDIGE_ESMRAMC_T_EN ((uint8_t)1)
#define MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME ((uint8_t)(1 << 6))
#define MCH_HOST_BRIDGE_ESMRAMC_E_SMERR ((uint8_t)(1 << 5))
#define MCH_HOST_BRIDGE_ESMRAMC_SM_CACHE ((uint8_t)(1 << 4))
#define MCH_HOST_BRIDGE_ESMRAMC_SM_L1 ((uint8_t)(1 << 3))
#define MCH_HOST_BRIDGE_ESMRAMC_SM_L2 ((uint8_t)(1 << 2))
#define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK ((uint8_t)(0x3 << 1))
#define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_1MB ((uint8_t)(0x0 << 1))
#define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_2MB ((uint8_t)(0x1 << 1))
#define MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_8MB ((uint8_t)(0x2 << 1))
#define MCH_HOST_BRIDGE_ESMRAMC_T_EN ((uint8_t)1)
/* D1:F0 PCIE* port*/
#define MCH_PCIE_DEV 1

BIN
tests/acpi-test-data/pc/SSDT
View File

Binary file not shown.

BIN
tests/acpi-test-data/q35/SSDT
View File

Binary file not shown.