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target/sh4: Let get_physical_address() use MMUAccessType access_type

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superh_cpu_tlb_fill() already provides a access_type variable of
type MMUAccessType, and it is passed along, but casted as integer
and renamed 'rw'.
Simply replace 'int rw' by 'MMUAccessType access_type'.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210127232151.3523581-5-f4bug@amsat.org>
This commit is contained in:
Philippe Mathieu-Daudé 2021-01-28 00:09:23 +01:00
parent 31ffda7133
commit be617b44fe
1 changed files with 10 additions and 10 deletions
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20
target/sh4/helper.c
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@ -331,14 +331,14 @@ static int find_utlb_entry(CPUSH4State * env, target_ulong address, int use_asid
*/
static int get_mmu_address(CPUSH4State * env, target_ulong * physical,
int *prot, target_ulong address,
int rw)
MMUAccessType access_type)
{
int use_asid, n;
tlb_t *matching = NULL;
use_asid = !(env->mmucr & MMUCR_SV) || !(env->sr & (1u << SR_MD));
if (rw == MMU_INST_FETCH) {
if (access_type == MMU_INST_FETCH) {
n = find_itlb_entry(env, address, use_asid);
if (n >= 0) {
matching = &env->itlb[n];
@ -371,11 +371,11 @@ static int get_mmu_address(CPUSH4State * env, target_ulong * physical,
if (n >= 0) {
matching = &env->utlb[n];
if (!(env->sr & (1u << SR_MD)) && !(matching->pr & 2)) {
n = (rw == MMU_DATA_STORE)
n = (access_type == MMU_DATA_STORE)
? MMU_DTLB_VIOLATION_WRITE : MMU_DTLB_VIOLATION_READ;
} else if ((rw == MMU_DATA_STORE) && !(matching->pr & 1)) {
} else if ((access_type == MMU_DATA_STORE) && !(matching->pr & 1)) {
n = MMU_DTLB_VIOLATION_WRITE;
} else if ((rw == MMU_DATA_STORE) && !matching->d) {
} else if ((access_type == MMU_DATA_STORE) && !matching->d) {
n = MMU_DTLB_INITIAL_WRITE;
} else {
*prot = PAGE_READ;
@ -384,7 +384,7 @@ static int get_mmu_address(CPUSH4State * env, target_ulong * physical,
}
}
} else if (n == MMU_DTLB_MISS) {
n = (rw == MMU_DATA_STORE)
n = (access_type == MMU_DATA_STORE)
? MMU_DTLB_MISS_WRITE : MMU_DTLB_MISS_READ;
}
}
@ -398,7 +398,7 @@ static int get_mmu_address(CPUSH4State * env, target_ulong * physical,
static int get_physical_address(CPUSH4State * env, target_ulong * physical,
int *prot, target_ulong address,
int rw)
MMUAccessType access_type)
{
/* P1, P2 and P4 areas do not use translation */
if ((address >= 0x80000000 && address < 0xc0000000) || address >= 0xe0000000) {
@ -406,9 +406,9 @@ static int get_physical_address(CPUSH4State * env, target_ulong * physical,
&& (address < 0xe0000000 || address >= 0xe4000000)) {
/* Unauthorized access in user mode (only store queues are available) */
qemu_log_mask(LOG_GUEST_ERROR, "Unauthorized access\n");
if (rw == MMU_DATA_LOAD) {
if (access_type == MMU_DATA_LOAD) {
return MMU_DADDR_ERROR_READ;
} else if (rw == MMU_DATA_STORE) {
} else if (access_type == MMU_DATA_STORE) {
return MMU_DADDR_ERROR_WRITE;
} else {
return MMU_IADDR_ERROR;
@ -432,7 +432,7 @@ static int get_physical_address(CPUSH4State * env, target_ulong * physical,
}
/* We need to resort to the MMU */
return get_mmu_address(env, physical, prot, address, rw);
return get_mmu_address(env, physical, prot, address, access_type);
}
hwaddr superh_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)