From be24bb4f3007c3e07cbf1934f7e781493d876ab7 Mon Sep 17 00:00:00 2001
From: ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162>
Date: Mon, 23 Jun 2008 12:57:09 +0000
Subject: [PATCH] Pass T0/T1 explicitly to helper functions, and clean up a few
 dyngen leftovers.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4780 c046a42c-6fe2-441c-8c8c-71466251a162
---
 target-mips/exec.h      |    1 -
 target-mips/helper.h    |  300 +++++------
 target-mips/op_helper.c | 1063 +++++++++++++++++++--------------------
 target-mips/translate.c |  867 ++++++++++++++++---------------
 4 files changed, 1128 insertions(+), 1103 deletions(-)

diff --git a/target-mips/exec.h b/target-mips/exec.h
index ec1b0f4dac..2653d34c7d 100644
--- a/target-mips/exec.h
+++ b/target-mips/exec.h
@@ -54,7 +54,6 @@ void dump_fpu(CPUState *env);
 void fpu_dump_state(CPUState *env, FILE *f,
                     int (*fpu_fprintf)(FILE *f, const char *fmt, ...),
                     int flags);
-void dump_sc (void);
 
 int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
                                int mmu_idx, int is_softmmu);
diff --git a/target-mips/helper.h b/target-mips/helper.h
index 1638d29b33..15ef064936 100644
--- a/target-mips/helper.h
+++ b/target-mips/helper.h
@@ -7,157 +7,157 @@ DEF_HELPER(void, do_raise_exception, (int excp))
 DEF_HELPER(void, do_interrupt_restart, (void))
 
 #ifdef TARGET_MIPS64
-DEF_HELPER(void, do_ldl, (int mem_idx))
-DEF_HELPER(void, do_ldr, (int mem_idx))
-DEF_HELPER(void, do_sdl, (int mem_idx))
-DEF_HELPER(void, do_sdr, (int mem_idx))
+DEF_HELPER(target_ulong, do_ldl, (target_ulong t0, target_ulong t1, int mem_idx))
+DEF_HELPER(target_ulong, do_ldr, (target_ulong t0, target_ulong t1, int mem_idx))
+DEF_HELPER(void, do_sdl, (target_ulong t0, target_ulong t1, int mem_idx))
+DEF_HELPER(void, do_sdr, (target_ulong t0, target_ulong t1, int mem_idx))
 #endif
-DEF_HELPER(void, do_lwl, (int mem_idx))
-DEF_HELPER(void, do_lwr, (int mem_idx))
-DEF_HELPER(void, do_swl, (int mem_idx))
-DEF_HELPER(void, do_swr, (int mem_idx))
+DEF_HELPER(target_ulong, do_lwl, (target_ulong t0, target_ulong t1, int mem_idx))
+DEF_HELPER(target_ulong, do_lwr, (target_ulong t0, target_ulong t1, int mem_idx))
+DEF_HELPER(void, do_swl, (target_ulong t0, target_ulong t1, int mem_idx))
+DEF_HELPER(void, do_swr, (target_ulong t0, target_ulong t1, int mem_idx))
 
-DEF_HELPER(void, do_clo, (void))
-DEF_HELPER(void, do_clz, (void))
+DEF_HELPER(target_ulong, do_clo, (target_ulong t0))
+DEF_HELPER(target_ulong, do_clz, (target_ulong t0))
 #ifdef TARGET_MIPS64
-DEF_HELPER(void, do_dclo, (void))
-DEF_HELPER(void, do_dclz, (void))
-DEF_HELPER(void, do_dmult, (void))
-DEF_HELPER(void, do_dmultu, (void))
+DEF_HELPER(target_ulong, do_dclo, (target_ulong t0))
+DEF_HELPER(target_ulong, do_dclz, (target_ulong t0))
+DEF_HELPER(void, do_dmult, (target_ulong t0, target_ulong t1))
+DEF_HELPER(void, do_dmultu, (target_ulong t0, target_ulong t1))
 #endif
 
-DEF_HELPER(void, do_muls, (void))
-DEF_HELPER(void, do_mulsu, (void))
-DEF_HELPER(void, do_macc, (void))
-DEF_HELPER(void, do_maccu, (void))
-DEF_HELPER(void, do_msac, (void))
-DEF_HELPER(void, do_msacu, (void))
-DEF_HELPER(void, do_mulhi, (void))
-DEF_HELPER(void, do_mulhiu, (void))
-DEF_HELPER(void, do_mulshi, (void))
-DEF_HELPER(void, do_mulshiu, (void))
-DEF_HELPER(void, do_macchi, (void))
-DEF_HELPER(void, do_macchiu, (void))
-DEF_HELPER(void, do_msachi, (void))
-DEF_HELPER(void, do_msachiu, (void))
+DEF_HELPER(target_ulong, do_muls, (target_ulong t0, target_ulong t1))
+DEF_HELPER(target_ulong, do_mulsu, (target_ulong t0, target_ulong t1))
+DEF_HELPER(target_ulong, do_macc, (target_ulong t0, target_ulong t1))
+DEF_HELPER(target_ulong, do_maccu, (target_ulong t0, target_ulong t1))
+DEF_HELPER(target_ulong, do_msac, (target_ulong t0, target_ulong t1))
+DEF_HELPER(target_ulong, do_msacu, (target_ulong t0, target_ulong t1))
+DEF_HELPER(target_ulong, do_mulhi, (target_ulong t0, target_ulong t1))
+DEF_HELPER(target_ulong, do_mulhiu, (target_ulong t0, target_ulong t1))
+DEF_HELPER(target_ulong, do_mulshi, (target_ulong t0, target_ulong t1))
+DEF_HELPER(target_ulong, do_mulshiu, (target_ulong t0, target_ulong t1))
+DEF_HELPER(target_ulong, do_macchi, (target_ulong t0, target_ulong t1))
+DEF_HELPER(target_ulong, do_macchiu, (target_ulong t0, target_ulong t1))
+DEF_HELPER(target_ulong, do_msachi, (target_ulong t0, target_ulong t1))
+DEF_HELPER(target_ulong, do_msachiu, (target_ulong t0, target_ulong t1))
 
 /* CP0 helpers */
 #ifndef CONFIG_USER_ONLY
-DEF_HELPER(void, do_mfc0_mvpcontrol, (void))
-DEF_HELPER(void, do_mfc0_mvpconf0, (void))
-DEF_HELPER(void, do_mfc0_mvpconf1, (void))
-DEF_HELPER(void, do_mfc0_random, (void))
-DEF_HELPER(void, do_mfc0_tcstatus, (void))
-DEF_HELPER(void, do_mftc0_tcstatus, (void))
-DEF_HELPER(void, do_mfc0_tcbind, (void))
-DEF_HELPER(void, do_mftc0_tcbind, (void))
-DEF_HELPER(void, do_mfc0_tcrestart, (void))
-DEF_HELPER(void, do_mftc0_tcrestart, (void))
-DEF_HELPER(void, do_mfc0_tchalt, (void))
-DEF_HELPER(void, do_mftc0_tchalt, (void))
-DEF_HELPER(void, do_mfc0_tccontext, (void))
-DEF_HELPER(void, do_mftc0_tccontext, (void))
-DEF_HELPER(void, do_mfc0_tcschedule, (void))
-DEF_HELPER(void, do_mftc0_tcschedule, (void))
-DEF_HELPER(void, do_mfc0_tcschefback, (void))
-DEF_HELPER(void, do_mftc0_tcschefback, (void))
-DEF_HELPER(void, do_mfc0_count, (void))
-DEF_HELPER(void, do_mftc0_entryhi, (void))
-DEF_HELPER(void, do_mftc0_status, (void))
-DEF_HELPER(void, do_mfc0_lladdr, (void))
-DEF_HELPER(void, do_mfc0_watchlo, (uint32_t sel))
-DEF_HELPER(void, do_mfc0_watchhi, (uint32_t sel))
-DEF_HELPER(void, do_mfc0_debug, (void))
-DEF_HELPER(void, do_mftc0_debug, (void))
+DEF_HELPER(target_ulong, do_mfc0_mvpcontrol, (target_ulong t0))
+DEF_HELPER(target_ulong, do_mfc0_mvpconf0, (target_ulong t0))
+DEF_HELPER(target_ulong, do_mfc0_mvpconf1, (target_ulong t0))
+DEF_HELPER(target_ulong, do_mfc0_random, (target_ulong t0))
+DEF_HELPER(target_ulong, do_mfc0_tcstatus, (target_ulong t0))
+DEF_HELPER(target_ulong, do_mftc0_tcstatus, (target_ulong t0))
+DEF_HELPER(target_ulong, do_mfc0_tcbind, (target_ulong t0))
+DEF_HELPER(target_ulong, do_mftc0_tcbind, (target_ulong t0))
+DEF_HELPER(target_ulong, do_mfc0_tcrestart, (target_ulong t0))
+DEF_HELPER(target_ulong, do_mftc0_tcrestart, (target_ulong t0))
+DEF_HELPER(target_ulong, do_mfc0_tchalt, (target_ulong t0))
+DEF_HELPER(target_ulong, do_mftc0_tchalt, (target_ulong t0))
+DEF_HELPER(target_ulong, do_mfc0_tccontext, (target_ulong t0))
+DEF_HELPER(target_ulong, do_mftc0_tccontext, (target_ulong t0))
+DEF_HELPER(target_ulong, do_mfc0_tcschedule, (target_ulong t0))
+DEF_HELPER(target_ulong, do_mftc0_tcschedule, (target_ulong t0))
+DEF_HELPER(target_ulong, do_mfc0_tcschefback, (target_ulong t0))
+DEF_HELPER(target_ulong, do_mftc0_tcschefback, (target_ulong t0))
+DEF_HELPER(target_ulong, do_mfc0_count, (target_ulong t0))
+DEF_HELPER(target_ulong, do_mftc0_entryhi, (target_ulong t0))
+DEF_HELPER(target_ulong, do_mftc0_status, (target_ulong t0))
+DEF_HELPER(target_ulong, do_mfc0_lladdr, (target_ulong t0))
+DEF_HELPER(target_ulong, do_mfc0_watchlo, (target_ulong t0, uint32_t sel))
+DEF_HELPER(target_ulong, do_mfc0_watchhi, (target_ulong t0, uint32_t sel))
+DEF_HELPER(target_ulong, do_mfc0_debug, (target_ulong t0))
+DEF_HELPER(target_ulong, do_mftc0_debug, (target_ulong t0))
 #ifdef TARGET_MIPS64
-DEF_HELPER(void, do_dmfc0_tcrestart, (void))
-DEF_HELPER(void, do_dmfc0_tchalt, (void))
-DEF_HELPER(void, do_dmfc0_tccontext, (void))
-DEF_HELPER(void, do_dmfc0_tcschedule, (void))
-DEF_HELPER(void, do_dmfc0_tcschefback, (void))
-DEF_HELPER(void, do_dmfc0_lladdr, (void))
-DEF_HELPER(void, do_dmfc0_watchlo, (uint32_t sel))
+DEF_HELPER(target_ulong, do_dmfc0_tcrestart, (target_ulong t0))
+DEF_HELPER(target_ulong, do_dmfc0_tchalt, (target_ulong t0))
+DEF_HELPER(target_ulong, do_dmfc0_tccontext, (target_ulong t0))
+DEF_HELPER(target_ulong, do_dmfc0_tcschedule, (target_ulong t0))
+DEF_HELPER(target_ulong, do_dmfc0_tcschefback, (target_ulong t0))
+DEF_HELPER(target_ulong, do_dmfc0_lladdr, (target_ulong t0))
+DEF_HELPER(target_ulong, do_dmfc0_watchlo, (target_ulong t0, uint32_t sel))
 #endif /* TARGET_MIPS64 */
 
-DEF_HELPER(void, do_mtc0_index, (void))
-DEF_HELPER(void, do_mtc0_mvpcontrol, (void))
-DEF_HELPER(void, do_mtc0_vpecontrol, (void))
-DEF_HELPER(void, do_mtc0_vpeconf0, (void))
-DEF_HELPER(void, do_mtc0_vpeconf1, (void))
-DEF_HELPER(void, do_mtc0_yqmask, (void))
-DEF_HELPER(void, do_mtc0_vpeopt, (void))
-DEF_HELPER(void, do_mtc0_entrylo0, (void))
-DEF_HELPER(void, do_mtc0_tcstatus, (void))
-DEF_HELPER(void, do_mttc0_tcstatus, (void))
-DEF_HELPER(void, do_mtc0_tcbind, (void))
-DEF_HELPER(void, do_mttc0_tcbind, (void))
-DEF_HELPER(void, do_mtc0_tcrestart, (void))
-DEF_HELPER(void, do_mttc0_tcrestart, (void))
-DEF_HELPER(void, do_mtc0_tchalt, (void))
-DEF_HELPER(void, do_mttc0_tchalt, (void))
-DEF_HELPER(void, do_mtc0_tccontext, (void))
-DEF_HELPER(void, do_mttc0_tccontext, (void))
-DEF_HELPER(void, do_mtc0_tcschedule, (void))
-DEF_HELPER(void, do_mttc0_tcschedule, (void))
-DEF_HELPER(void, do_mtc0_tcschefback, (void))
-DEF_HELPER(void, do_mttc0_tcschefback, (void))
-DEF_HELPER(void, do_mtc0_entrylo1, (void))
-DEF_HELPER(void, do_mtc0_context, (void))
-DEF_HELPER(void, do_mtc0_pagemask, (void))
-DEF_HELPER(void, do_mtc0_pagegrain, (void))
-DEF_HELPER(void, do_mtc0_wired, (void))
-DEF_HELPER(void, do_mtc0_srsconf0, (void))
-DEF_HELPER(void, do_mtc0_srsconf1, (void))
-DEF_HELPER(void, do_mtc0_srsconf2, (void))
-DEF_HELPER(void, do_mtc0_srsconf3, (void))
-DEF_HELPER(void, do_mtc0_srsconf4, (void))
-DEF_HELPER(void, do_mtc0_hwrena, (void))
-DEF_HELPER(void, do_mtc0_count, (void))
-DEF_HELPER(void, do_mtc0_entryhi, (void))
-DEF_HELPER(void, do_mttc0_entryhi, (void))
-DEF_HELPER(void, do_mtc0_compare, (void))
-DEF_HELPER(void, do_mtc0_status, (void))
-DEF_HELPER(void, do_mttc0_status, (void))
-DEF_HELPER(void, do_mtc0_intctl, (void))
-DEF_HELPER(void, do_mtc0_srsctl, (void))
-DEF_HELPER(void, do_mtc0_cause, (void))
-DEF_HELPER(void, do_mtc0_ebase, (void))
-DEF_HELPER(void, do_mtc0_config0, (void))
-DEF_HELPER(void, do_mtc0_config2, (void))
-DEF_HELPER(void, do_mtc0_watchlo, (uint32_t sel))
-DEF_HELPER(void, do_mtc0_watchhi, (uint32_t sel))
-DEF_HELPER(void, do_mtc0_xcontext, (void))
-DEF_HELPER(void, do_mtc0_framemask, (void))
-DEF_HELPER(void, do_mtc0_debug, (void))
-DEF_HELPER(void, do_mttc0_debug, (void))
-DEF_HELPER(void, do_mtc0_performance0, (void))
-DEF_HELPER(void, do_mtc0_taglo, (void))
-DEF_HELPER(void, do_mtc0_datalo, (void))
-DEF_HELPER(void, do_mtc0_taghi, (void))
-DEF_HELPER(void, do_mtc0_datahi, (void))
+DEF_HELPER(void, do_mtc0_index, (target_ulong t0))
+DEF_HELPER(void, do_mtc0_mvpcontrol, (target_ulong t0))
+DEF_HELPER(void, do_mtc0_vpecontrol, (target_ulong t0))
+DEF_HELPER(void, do_mtc0_vpeconf0, (target_ulong t0))
+DEF_HELPER(void, do_mtc0_vpeconf1, (target_ulong t0))
+DEF_HELPER(void, do_mtc0_yqmask, (target_ulong t0))
+DEF_HELPER(void, do_mtc0_vpeopt, (target_ulong t0))
+DEF_HELPER(void, do_mtc0_entrylo0, (target_ulong t0))
+DEF_HELPER(void, do_mtc0_tcstatus, (target_ulong t0))
+DEF_HELPER(void, do_mttc0_tcstatus, (target_ulong t0))
+DEF_HELPER(void, do_mtc0_tcbind, (target_ulong t0))
+DEF_HELPER(void, do_mttc0_tcbind, (target_ulong t0))
+DEF_HELPER(void, do_mtc0_tcrestart, (target_ulong t0))
+DEF_HELPER(void, do_mttc0_tcrestart, (target_ulong t0))
+DEF_HELPER(void, do_mtc0_tchalt, (target_ulong t0))
+DEF_HELPER(void, do_mttc0_tchalt, (target_ulong t0))
+DEF_HELPER(void, do_mtc0_tccontext, (target_ulong t0))
+DEF_HELPER(void, do_mttc0_tccontext, (target_ulong t0))
+DEF_HELPER(void, do_mtc0_tcschedule, (target_ulong t0))
+DEF_HELPER(void, do_mttc0_tcschedule, (target_ulong t0))
+DEF_HELPER(void, do_mtc0_tcschefback, (target_ulong t0))
+DEF_HELPER(void, do_mttc0_tcschefback, (target_ulong t0))
+DEF_HELPER(void, do_mtc0_entrylo1, (target_ulong t0))
+DEF_HELPER(void, do_mtc0_context, (target_ulong t0))
+DEF_HELPER(void, do_mtc0_pagemask, (target_ulong t0))
+DEF_HELPER(void, do_mtc0_pagegrain, (target_ulong t0))
+DEF_HELPER(void, do_mtc0_wired, (target_ulong t0))
+DEF_HELPER(void, do_mtc0_srsconf0, (target_ulong t0))
+DEF_HELPER(void, do_mtc0_srsconf1, (target_ulong t0))
+DEF_HELPER(void, do_mtc0_srsconf2, (target_ulong t0))
+DEF_HELPER(void, do_mtc0_srsconf3, (target_ulong t0))
+DEF_HELPER(void, do_mtc0_srsconf4, (target_ulong t0))
+DEF_HELPER(void, do_mtc0_hwrena, (target_ulong t0))
+DEF_HELPER(void, do_mtc0_count, (target_ulong t0))
+DEF_HELPER(void, do_mtc0_entryhi, (target_ulong t0))
+DEF_HELPER(void, do_mttc0_entryhi, (target_ulong t0))
+DEF_HELPER(void, do_mtc0_compare, (target_ulong t0))
+DEF_HELPER(void, do_mtc0_status, (target_ulong t0))
+DEF_HELPER(void, do_mttc0_status, (target_ulong t0))
+DEF_HELPER(void, do_mtc0_intctl, (target_ulong t0))
+DEF_HELPER(void, do_mtc0_srsctl, (target_ulong t0))
+DEF_HELPER(void, do_mtc0_cause, (target_ulong t0))
+DEF_HELPER(void, do_mtc0_ebase, (target_ulong t0))
+DEF_HELPER(void, do_mtc0_config0, (target_ulong t0))
+DEF_HELPER(void, do_mtc0_config2, (target_ulong t0))
+DEF_HELPER(void, do_mtc0_watchlo, (target_ulong t0, uint32_t sel))
+DEF_HELPER(void, do_mtc0_watchhi, (target_ulong t0, uint32_t sel))
+DEF_HELPER(void, do_mtc0_xcontext, (target_ulong t0))
+DEF_HELPER(void, do_mtc0_framemask, (target_ulong t0))
+DEF_HELPER(void, do_mtc0_debug, (target_ulong t0))
+DEF_HELPER(void, do_mttc0_debug, (target_ulong t0))
+DEF_HELPER(void, do_mtc0_performance0, (target_ulong t0))
+DEF_HELPER(void, do_mtc0_taglo, (target_ulong t0))
+DEF_HELPER(void, do_mtc0_datalo, (target_ulong t0))
+DEF_HELPER(void, do_mtc0_taghi, (target_ulong t0))
+DEF_HELPER(void, do_mtc0_datahi, (target_ulong t0))
 #endif /* !CONFIG_USER_ONLY */
 
 /* MIPS MT functions */
-DEF_HELPER(void, do_mftgpr, (uint32_t sel))
-DEF_HELPER(void, do_mftlo, (uint32_t sel))
-DEF_HELPER(void, do_mfthi, (uint32_t sel))
-DEF_HELPER(void, do_mftacx, (uint32_t sel))
-DEF_HELPER(void, do_mftdsp, (void))
-DEF_HELPER(void, do_mttgpr, (uint32_t sel))
-DEF_HELPER(void, do_mttlo, (uint32_t sel))
-DEF_HELPER(void, do_mtthi, (uint32_t sel))
-DEF_HELPER(void, do_mttacx, (uint32_t sel))
-DEF_HELPER(void, do_mttdsp, (void))
-DEF_HELPER(void, do_dmt, (void))
-DEF_HELPER(void, do_emt, (void))
-DEF_HELPER(void, do_dvpe, (void))
-DEF_HELPER(void, do_evpe, (void))
-DEF_HELPER(void, do_fork, (void))
-DEF_HELPER(void, do_yield, (void))
+DEF_HELPER(target_ulong, do_mftgpr, (target_ulong t0, uint32_t sel))
+DEF_HELPER(target_ulong, do_mftlo, (target_ulong t0, uint32_t sel))
+DEF_HELPER(target_ulong, do_mfthi, (target_ulong t0, uint32_t sel))
+DEF_HELPER(target_ulong, do_mftacx, (target_ulong t0, uint32_t sel))
+DEF_HELPER(target_ulong, do_mftdsp, (target_ulong t0))
+DEF_HELPER(void, do_mttgpr, (target_ulong t0, uint32_t sel))
+DEF_HELPER(void, do_mttlo, (target_ulong t0, uint32_t sel))
+DEF_HELPER(void, do_mtthi, (target_ulong t0, uint32_t sel))
+DEF_HELPER(void, do_mttacx, (target_ulong t0, uint32_t sel))
+DEF_HELPER(void, do_mttdsp, (target_ulong t0))
+DEF_HELPER(target_ulong, do_dmt, (target_ulong t0))
+DEF_HELPER(target_ulong, do_emt, (target_ulong t0))
+DEF_HELPER(target_ulong, do_dvpe, (target_ulong t0))
+DEF_HELPER(target_ulong, do_evpe, (target_ulong t0))
+DEF_HELPER(target_ulong, do_fork, (target_ulong t0, target_ulong t1))
+DEF_HELPER(target_ulong, do_yield, (target_ulong t0))
 
 /* CP1 functions */
-DEF_HELPER(void, do_cfc1, (uint32_t reg))
-DEF_HELPER(void, do_ctc1, (uint32_t reg))
+DEF_HELPER(target_ulong, do_cfc1, (target_ulong t0, uint32_t reg))
+DEF_HELPER(void, do_ctc1, (target_ulong t0, uint32_t reg))
 
 DEF_HELPER(void, do_float_cvtd_s, (void))
 DEF_HELPER(void, do_float_cvtd_w, (void))
@@ -239,24 +239,24 @@ FOP_PROTO(ngt)
 #undef FOP_PROTO
 
 /* Special functions */
-DEF_HELPER(void, do_di, (void))
-DEF_HELPER(void, do_ei, (void))
-DEF_HELPER(void, do_eret, (void))
-DEF_HELPER(void, do_deret, (void))
-DEF_HELPER(void, do_rdhwr_cpunum, (void))
-DEF_HELPER(void, do_rdhwr_synci_step, (void))
-DEF_HELPER(void, do_rdhwr_cc, (void))
-DEF_HELPER(void, do_rdhwr_ccres, (void))
+DEF_HELPER(target_ulong, do_di, (target_ulong t0))
+DEF_HELPER(target_ulong, do_ei, (target_ulong t0))
+DEF_HELPER(void, do_eret, (target_ulong t0))
+DEF_HELPER(void, do_deret, (target_ulong t0))
+DEF_HELPER(target_ulong, do_rdhwr_cpunum, (target_ulong t0))
+DEF_HELPER(target_ulong, do_rdhwr_synci_step, (target_ulong t0))
+DEF_HELPER(target_ulong, do_rdhwr_cc, (target_ulong t0))
+DEF_HELPER(target_ulong, do_rdhwr_ccres, (target_ulong t0))
 DEF_HELPER(void, do_pmon, (int function))
 DEF_HELPER(void, do_wait, (void))
 
 /* Bitfield operations. */
-DEF_HELPER(void, do_ext, (uint32_t pos, uint32_t size))
-DEF_HELPER(void, do_ins, (uint32_t pos, uint32_t size))
-DEF_HELPER(void, do_wsbh, (void))
+DEF_HELPER(target_ulong, do_ext, (target_ulong t0, target_ulong t1, uint32_t pos, uint32_t size))
+DEF_HELPER(target_ulong, do_ins, (target_ulong t0, target_ulong t1, uint32_t pos, uint32_t size))
+DEF_HELPER(target_ulong, do_wsbh, (target_ulong t0, target_ulong t1))
 #ifdef TARGET_MIPS64
-DEF_HELPER(void, do_dext, (uint32_t pos, uint32_t size))
-DEF_HELPER(void, do_dins, (uint32_t pos, uint32_t size))
-DEF_HELPER(void, do_dsbh, (void))
-DEF_HELPER(void, do_dshd, (void))
+DEF_HELPER(target_ulong, do_dext, (target_ulong t0, target_ulong t1, uint32_t pos, uint32_t size))
+DEF_HELPER(target_ulong, do_dins, (target_ulong t0, target_ulong t1, uint32_t pos, uint32_t size))
+DEF_HELPER(target_ulong, do_dsbh, (target_ulong t0, target_ulong t1))
+DEF_HELPER(target_ulong, do_dshd, (target_ulong t0, target_ulong t1))
 #endif
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index 602116a8b3..86a720d5ac 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -33,7 +33,6 @@ void do_raise_exception_err (uint32_t exception, int error_code)
 #endif
     env->exception_index = exception;
     env->error_code = error_code;
-    T0 = 0;
     cpu_loop_exit();
 }
 
@@ -65,106 +64,26 @@ void do_restore_state (void *pc_ptr)
     }
 }
 
-void do_clo (void)
+target_ulong do_clo (target_ulong t0)
 {
-    T0 = clo32(T0);
+    return clo32(t0);
 }
 
-void do_clz (void)
+target_ulong do_clz (target_ulong t0)
 {
-    T0 = clz32(T0);
+    return clz32(t0);
 }
 
 #if defined(TARGET_MIPS64)
-#if TARGET_LONG_BITS > HOST_LONG_BITS
-/* Those might call libgcc functions.  */
-void do_dsll (void)
+target_ulong do_dclo (target_ulong t0)
 {
-    T0 = T0 << T1;
+    return clo64(t0);
 }
 
-void do_dsll32 (void)
+target_ulong do_dclz (target_ulong t0)
 {
-    T0 = T0 << (T1 + 32);
+    return clz64(t0);
 }
-
-void do_dsra (void)
-{
-    T0 = (int64_t)T0 >> T1;
-}
-
-void do_dsra32 (void)
-{
-    T0 = (int64_t)T0 >> (T1 + 32);
-}
-
-void do_dsrl (void)
-{
-    T0 = T0 >> T1;
-}
-
-void do_dsrl32 (void)
-{
-    T0 = T0 >> (T1 + 32);
-}
-
-void do_drotr (void)
-{
-    target_ulong tmp;
-
-    if (T1) {
-        tmp = T0 << (0x40 - T1);
-        T0 = (T0 >> T1) | tmp;
-    }
-}
-
-void do_drotr32 (void)
-{
-    target_ulong tmp;
-
-    tmp = T0 << (0x40 - (32 + T1));
-    T0 = (T0 >> (32 + T1)) | tmp;
-}
-
-void do_dsllv (void)
-{
-    T0 = T1 << (T0 & 0x3F);
-}
-
-void do_dsrav (void)
-{
-    T0 = (int64_t)T1 >> (T0 & 0x3F);
-}
-
-void do_dsrlv (void)
-{
-    T0 = T1 >> (T0 & 0x3F);
-}
-
-void do_drotrv (void)
-{
-    target_ulong tmp;
-
-    T0 &= 0x3F;
-    if (T0) {
-        tmp = T1 << (0x40 - T0);
-        T0 = (T1 >> T0) | tmp;
-    } else
-        T0 = T1;
-}
-
-#endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
-
-void do_dclo (void)
-{
-    T0 = clo64(T0);
-}
-
-void do_dclz (void)
-{
-    T0 = clz64(T0);
-}
-
 #endif /* TARGET_MIPS64 */
 
 /* 64 bits arithmetic for 32 bits hosts */
@@ -179,132 +98,160 @@ static always_inline void set_HILO (uint64_t HILO)
     env->HI[env->current_tc][0] = (int32_t)(HILO >> 32);
 }
 
-static always_inline void set_HIT0_LO (uint64_t HILO)
+static always_inline void set_HIT0_LO (target_ulong t0, uint64_t HILO)
 {
     env->LO[env->current_tc][0] = (int32_t)(HILO & 0xFFFFFFFF);
-    T0 = env->HI[env->current_tc][0] = (int32_t)(HILO >> 32);
+    t0 = env->HI[env->current_tc][0] = (int32_t)(HILO >> 32);
 }
 
-static always_inline void set_HI_LOT0 (uint64_t HILO)
+static always_inline void set_HI_LOT0 (target_ulong t0, uint64_t HILO)
 {
-    T0 = env->LO[env->current_tc][0] = (int32_t)(HILO & 0xFFFFFFFF);
+    t0 = env->LO[env->current_tc][0] = (int32_t)(HILO & 0xFFFFFFFF);
     env->HI[env->current_tc][0] = (int32_t)(HILO >> 32);
 }
 
 #if TARGET_LONG_BITS > HOST_LONG_BITS
-void do_madd (void)
+void do_madd (target_ulong t0, target_ulong t1)
 {
     int64_t tmp;
 
-    tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
+    tmp = ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1);
     set_HILO((int64_t)get_HILO() + tmp);
 }
 
-void do_maddu (void)
+void do_maddu (target_ulong t0, target_ulong t1)
 {
     uint64_t tmp;
 
-    tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
+    tmp = ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1);
     set_HILO(get_HILO() + tmp);
 }
 
-void do_msub (void)
+void do_msub (target_ulong t0, target_ulong t1)
 {
     int64_t tmp;
 
-    tmp = ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
+    tmp = ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1);
     set_HILO((int64_t)get_HILO() - tmp);
 }
 
-void do_msubu (void)
+void do_msubu (target_ulong t0, target_ulong t1)
 {
     uint64_t tmp;
 
-    tmp = ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
+    tmp = ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1);
     set_HILO(get_HILO() - tmp);
 }
 #endif /* TARGET_LONG_BITS > HOST_LONG_BITS */
 
 /* Multiplication variants of the vr54xx. */
-void do_muls (void)
+target_ulong do_muls (target_ulong t0, target_ulong t1)
 {
-    set_HI_LOT0(0 - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));
+    set_HI_LOT0(t0, 0 - ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
+
+    return t0;
 }
 
-void do_mulsu (void)
+target_ulong do_mulsu (target_ulong t0, target_ulong t1)
 {
-    set_HI_LOT0(0 - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));
+    set_HI_LOT0(t0, 0 - ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
+
+    return t0;
 }
 
-void do_macc (void)
+target_ulong do_macc (target_ulong t0, target_ulong t1)
 {
-    set_HI_LOT0(((int64_t)get_HILO()) + ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));
+    set_HI_LOT0(t0, ((int64_t)get_HILO()) + ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
+
+    return t0;
 }
 
-void do_macchi (void)
+target_ulong do_macchi (target_ulong t0, target_ulong t1)
 {
-    set_HIT0_LO(((int64_t)get_HILO()) + ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));
+    set_HIT0_LO(t0, ((int64_t)get_HILO()) + ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
+
+    return t0;
 }
 
-void do_maccu (void)
+target_ulong do_maccu (target_ulong t0, target_ulong t1)
 {
-    set_HI_LOT0(((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));
+    set_HI_LOT0(t0, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
+
+    return t0;
 }
 
-void do_macchiu (void)
+target_ulong do_macchiu (target_ulong t0, target_ulong t1)
 {
-    set_HIT0_LO(((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));
+    set_HIT0_LO(t0, ((uint64_t)get_HILO()) + ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
+
+    return t0;
 }
 
-void do_msac (void)
+target_ulong do_msac (target_ulong t0, target_ulong t1)
 {
-    set_HI_LOT0(((int64_t)get_HILO()) - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));
+    set_HI_LOT0(t0, ((int64_t)get_HILO()) - ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
+
+    return t0;
 }
 
-void do_msachi (void)
+target_ulong do_msachi (target_ulong t0, target_ulong t1)
 {
-    set_HIT0_LO(((int64_t)get_HILO()) - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));
+    set_HIT0_LO(t0, ((int64_t)get_HILO()) - ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
+
+    return t0;
 }
 
-void do_msacu (void)
+target_ulong do_msacu (target_ulong t0, target_ulong t1)
 {
-    set_HI_LOT0(((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));
+    set_HI_LOT0(t0, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
+
+    return t0;
 }
 
-void do_msachiu (void)
+target_ulong do_msachiu (target_ulong t0, target_ulong t1)
 {
-    set_HIT0_LO(((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));
+    set_HIT0_LO(t0, ((uint64_t)get_HILO()) - ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
+
+    return t0;
 }
 
-void do_mulhi (void)
+target_ulong do_mulhi (target_ulong t0, target_ulong t1)
 {
-    set_HIT0_LO((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1);
+    set_HIT0_LO(t0, (int64_t)(int32_t)t0 * (int64_t)(int32_t)t1);
+
+    return t0;
 }
 
-void do_mulhiu (void)
+target_ulong do_mulhiu (target_ulong t0, target_ulong t1)
 {
-    set_HIT0_LO((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1);
+    set_HIT0_LO(t0, (uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1);
+
+    return t0;
 }
 
-void do_mulshi (void)
+target_ulong do_mulshi (target_ulong t0, target_ulong t1)
 {
-    set_HIT0_LO(0 - ((int64_t)(int32_t)T0 * (int64_t)(int32_t)T1));
+    set_HIT0_LO(t0, 0 - ((int64_t)(int32_t)t0 * (int64_t)(int32_t)t1));
+
+    return t0;
 }
 
-void do_mulshiu (void)
+target_ulong do_mulshiu (target_ulong t0, target_ulong t1)
 {
-    set_HIT0_LO(0 - ((uint64_t)(uint32_t)T0 * (uint64_t)(uint32_t)T1));
+    set_HIT0_LO(t0, 0 - ((uint64_t)(uint32_t)t0 * (uint64_t)(uint32_t)t1));
+
+    return t0;
 }
 
 #ifdef TARGET_MIPS64
-void do_dmult (void)
+void do_dmult (target_ulong t0, target_ulong t1)
 {
-    muls64(&(env->LO[env->current_tc][0]), &(env->HI[env->current_tc][0]), T0, T1);
+    muls64(&(env->LO[env->current_tc][0]), &(env->HI[env->current_tc][0]), t0, t1);
 }
 
-void do_dmultu (void)
+void do_dmultu (target_ulong t0, target_ulong t1)
 {
-    mulu64(&(env->LO[env->current_tc][0]), &(env->HI[env->current_tc][0]), T0, T1);
+    mulu64(&(env->LO[env->current_tc][0]), &(env->HI[env->current_tc][0]), t0, t1);
 }
 #endif
 
@@ -316,7 +263,7 @@ void do_dmultu (void)
 #define GET_OFFSET(addr, offset) (addr - (offset))
 #endif
 
-void do_lwl(int mem_idx)
+target_ulong do_lwl(target_ulong t0, target_ulong t1, int mem_idx)
 {
     target_ulong tmp;
 
@@ -333,27 +280,27 @@ void do_lwl(int mem_idx)
     case 2: ldfun = ldub_user; break;
     }
 #endif
-    tmp = ldfun(T0);
-    T1 = (T1 & 0x00FFFFFF) | (tmp << 24);
+    tmp = ldfun(t0);
+    t1 = (t1 & 0x00FFFFFF) | (tmp << 24);
 
-    if (GET_LMASK(T0) <= 2) {
-        tmp = ldfun(GET_OFFSET(T0, 1));
-        T1 = (T1 & 0xFF00FFFF) | (tmp << 16);
+    if (GET_LMASK(t0) <= 2) {
+        tmp = ldfun(GET_OFFSET(t0, 1));
+        t1 = (t1 & 0xFF00FFFF) | (tmp << 16);
     }
 
-    if (GET_LMASK(T0) <= 1) {
-        tmp = ldfun(GET_OFFSET(T0, 2));
-        T1 = (T1 & 0xFFFF00FF) | (tmp << 8);
+    if (GET_LMASK(t0) <= 1) {
+        tmp = ldfun(GET_OFFSET(t0, 2));
+        t1 = (t1 & 0xFFFF00FF) | (tmp << 8);
     }
 
-    if (GET_LMASK(T0) == 0) {
-        tmp = ldfun(GET_OFFSET(T0, 3));
-        T1 = (T1 & 0xFFFFFF00) | tmp;
+    if (GET_LMASK(t0) == 0) {
+        tmp = ldfun(GET_OFFSET(t0, 3));
+        t1 = (t1 & 0xFFFFFF00) | tmp;
     }
-    T1 = (int32_t)T1;
+    return (int32_t)t1;
 }
 
-void do_lwr(int mem_idx)
+target_ulong do_lwr(target_ulong t0, target_ulong t1, int mem_idx)
 {
     target_ulong tmp;
 
@@ -370,27 +317,27 @@ void do_lwr(int mem_idx)
     case 2: ldfun = ldub_user; break;
     }
 #endif
-    tmp = ldfun(T0);
-    T1 = (T1 & 0xFFFFFF00) | tmp;
+    tmp = ldfun(t0);
+    t1 = (t1 & 0xFFFFFF00) | tmp;
 
-    if (GET_LMASK(T0) >= 1) {
-        tmp = ldfun(GET_OFFSET(T0, -1));
-        T1 = (T1 & 0xFFFF00FF) | (tmp << 8);
+    if (GET_LMASK(t0) >= 1) {
+        tmp = ldfun(GET_OFFSET(t0, -1));
+        t1 = (t1 & 0xFFFF00FF) | (tmp << 8);
     }
 
-    if (GET_LMASK(T0) >= 2) {
-        tmp = ldfun(GET_OFFSET(T0, -2));
-        T1 = (T1 & 0xFF00FFFF) | (tmp << 16);
+    if (GET_LMASK(t0) >= 2) {
+        tmp = ldfun(GET_OFFSET(t0, -2));
+        t1 = (t1 & 0xFF00FFFF) | (tmp << 16);
     }
 
-    if (GET_LMASK(T0) == 3) {
-        tmp = ldfun(GET_OFFSET(T0, -3));
-        T1 = (T1 & 0x00FFFFFF) | (tmp << 24);
+    if (GET_LMASK(t0) == 3) {
+        tmp = ldfun(GET_OFFSET(t0, -3));
+        t1 = (t1 & 0x00FFFFFF) | (tmp << 24);
     }
-    T1 = (int32_t)T1;
+    return (int32_t)t1;
 }
 
-void do_swl(int mem_idx)
+void do_swl(target_ulong t0, target_ulong t1, int mem_idx)
 {
 #ifdef CONFIG_USER_ONLY
 #define stfun stb_raw
@@ -405,19 +352,19 @@ void do_swl(int mem_idx)
     case 2: stfun = stb_user; break;
     }
 #endif
-    stfun(T0, (uint8_t)(T1 >> 24));
+    stfun(t0, (uint8_t)(t1 >> 24));
 
-    if (GET_LMASK(T0) <= 2)
-        stfun(GET_OFFSET(T0, 1), (uint8_t)(T1 >> 16));
+    if (GET_LMASK(t0) <= 2)
+        stfun(GET_OFFSET(t0, 1), (uint8_t)(t1 >> 16));
 
-    if (GET_LMASK(T0) <= 1)
-        stfun(GET_OFFSET(T0, 2), (uint8_t)(T1 >> 8));
+    if (GET_LMASK(t0) <= 1)
+        stfun(GET_OFFSET(t0, 2), (uint8_t)(t1 >> 8));
 
-    if (GET_LMASK(T0) == 0)
-        stfun(GET_OFFSET(T0, 3), (uint8_t)T1);
+    if (GET_LMASK(t0) == 0)
+        stfun(GET_OFFSET(t0, 3), (uint8_t)t1);
 }
 
-void do_swr(int mem_idx)
+void do_swr(target_ulong t0, target_ulong t1, int mem_idx)
 {
 #ifdef CONFIG_USER_ONLY
 #define stfun stb_raw
@@ -432,16 +379,16 @@ void do_swr(int mem_idx)
     case 2: stfun = stb_user; break;
     }
 #endif
-    stfun(T0, (uint8_t)T1);
+    stfun(t0, (uint8_t)t1);
 
-    if (GET_LMASK(T0) >= 1)
-        stfun(GET_OFFSET(T0, -1), (uint8_t)(T1 >> 8));
+    if (GET_LMASK(t0) >= 1)
+        stfun(GET_OFFSET(t0, -1), (uint8_t)(t1 >> 8));
 
-    if (GET_LMASK(T0) >= 2)
-        stfun(GET_OFFSET(T0, -2), (uint8_t)(T1 >> 16));
+    if (GET_LMASK(t0) >= 2)
+        stfun(GET_OFFSET(t0, -2), (uint8_t)(t1 >> 16));
 
-    if (GET_LMASK(T0) == 3)
-        stfun(GET_OFFSET(T0, -3), (uint8_t)(T1 >> 24));
+    if (GET_LMASK(t0) == 3)
+        stfun(GET_OFFSET(t0, -3), (uint8_t)(t1 >> 24));
 }
 
 #if defined(TARGET_MIPS64)
@@ -454,14 +401,14 @@ void do_swr(int mem_idx)
 #define GET_LMASK64(v) (((v) & 7) ^ 7)
 #endif
 
-void do_ldl(int mem_idx)
+target_ulong do_ldl(target_ulong t0, target_ulong t1, int mem_idx)
 {
     uint64_t tmp;
 
 #ifdef CONFIG_USER_ONLY
 #define ldfun ldub_raw
 #else
-    target_ulong (*ldfun)(target_ulong);
+    int (*ldfun)(target_ulong);
 
     switch (mem_idx)
     {
@@ -471,53 +418,55 @@ void do_ldl(int mem_idx)
     case 2: ldfun = ldub_user; break;
     }
 #endif
-    tmp = ldfun(T0);
-    T1 = (T1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56);
+    tmp = ldfun(t0);
+    t1 = (t1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56);
 
-    if (GET_LMASK64(T0) <= 6) {
-        tmp = ldfun(GET_OFFSET(T0, 1));
-        T1 = (T1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48);
+    if (GET_LMASK64(t0) <= 6) {
+        tmp = ldfun(GET_OFFSET(t0, 1));
+        t1 = (t1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48);
     }
 
-    if (GET_LMASK64(T0) <= 5) {
-        tmp = ldfun(GET_OFFSET(T0, 2));
-        T1 = (T1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40);
+    if (GET_LMASK64(t0) <= 5) {
+        tmp = ldfun(GET_OFFSET(t0, 2));
+        t1 = (t1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40);
     }
 
-    if (GET_LMASK64(T0) <= 4) {
-        tmp = ldfun(GET_OFFSET(T0, 3));
-        T1 = (T1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32);
+    if (GET_LMASK64(t0) <= 4) {
+        tmp = ldfun(GET_OFFSET(t0, 3));
+        t1 = (t1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32);
     }
 
-    if (GET_LMASK64(T0) <= 3) {
-        tmp = ldfun(GET_OFFSET(T0, 4));
-        T1 = (T1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24);
+    if (GET_LMASK64(t0) <= 3) {
+        tmp = ldfun(GET_OFFSET(t0, 4));
+        t1 = (t1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24);
     }
 
-    if (GET_LMASK64(T0) <= 2) {
-        tmp = ldfun(GET_OFFSET(T0, 5));
-        T1 = (T1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16);
+    if (GET_LMASK64(t0) <= 2) {
+        tmp = ldfun(GET_OFFSET(t0, 5));
+        t1 = (t1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16);
     }
 
-    if (GET_LMASK64(T0) <= 1) {
-        tmp = ldfun(GET_OFFSET(T0, 6));
-        T1 = (T1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8);
+    if (GET_LMASK64(t0) <= 1) {
+        tmp = ldfun(GET_OFFSET(t0, 6));
+        t1 = (t1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8);
     }
 
-    if (GET_LMASK64(T0) == 0) {
-        tmp = ldfun(GET_OFFSET(T0, 7));
-        T1 = (T1 & 0xFFFFFFFFFFFFFF00ULL) | tmp;
+    if (GET_LMASK64(t0) == 0) {
+        tmp = ldfun(GET_OFFSET(t0, 7));
+        t1 = (t1 & 0xFFFFFFFFFFFFFF00ULL) | tmp;
     }
+
+    return t1;
 }
 
-void do_ldr(int mem_idx)
+target_ulong do_ldr(target_ulong t0, target_ulong t1, int mem_idx)
 {
     uint64_t tmp;
 
 #ifdef CONFIG_USER_ONLY
 #define ldfun ldub_raw
 #else
-    target_ulong (*ldfun)(target_ulong);
+    int (*ldfun)(target_ulong);
 
     switch (mem_idx)
     {
@@ -527,46 +476,48 @@ void do_ldr(int mem_idx)
     case 2: ldfun = ldub_user; break;
     }
 #endif
-    tmp = ldfun(T0);
-    T1 = (T1 & 0xFFFFFFFFFFFFFF00ULL) | tmp;
+    tmp = ldfun(t0);
+    t1 = (t1 & 0xFFFFFFFFFFFFFF00ULL) | tmp;
 
-    if (GET_LMASK64(T0) >= 1) {
-        tmp = ldfun(GET_OFFSET(T0, -1));
-        T1 = (T1 & 0xFFFFFFFFFFFF00FFULL) | (tmp  << 8);
+    if (GET_LMASK64(t0) >= 1) {
+        tmp = ldfun(GET_OFFSET(t0, -1));
+        t1 = (t1 & 0xFFFFFFFFFFFF00FFULL) | (tmp  << 8);
     }
 
-    if (GET_LMASK64(T0) >= 2) {
-        tmp = ldfun(GET_OFFSET(T0, -2));
-        T1 = (T1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16);
+    if (GET_LMASK64(t0) >= 2) {
+        tmp = ldfun(GET_OFFSET(t0, -2));
+        t1 = (t1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16);
     }
 
-    if (GET_LMASK64(T0) >= 3) {
-        tmp = ldfun(GET_OFFSET(T0, -3));
-        T1 = (T1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24);
+    if (GET_LMASK64(t0) >= 3) {
+        tmp = ldfun(GET_OFFSET(t0, -3));
+        t1 = (t1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24);
     }
 
-    if (GET_LMASK64(T0) >= 4) {
-        tmp = ldfun(GET_OFFSET(T0, -4));
-        T1 = (T1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32);
+    if (GET_LMASK64(t0) >= 4) {
+        tmp = ldfun(GET_OFFSET(t0, -4));
+        t1 = (t1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32);
     }
 
-    if (GET_LMASK64(T0) >= 5) {
-        tmp = ldfun(GET_OFFSET(T0, -5));
-        T1 = (T1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40);
+    if (GET_LMASK64(t0) >= 5) {
+        tmp = ldfun(GET_OFFSET(t0, -5));
+        t1 = (t1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40);
     }
 
-    if (GET_LMASK64(T0) >= 6) {
-        tmp = ldfun(GET_OFFSET(T0, -6));
-        T1 = (T1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48);
+    if (GET_LMASK64(t0) >= 6) {
+        tmp = ldfun(GET_OFFSET(t0, -6));
+        t1 = (t1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48);
     }
 
-    if (GET_LMASK64(T0) == 7) {
-        tmp = ldfun(GET_OFFSET(T0, -7));
-        T1 = (T1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56);
+    if (GET_LMASK64(t0) == 7) {
+        tmp = ldfun(GET_OFFSET(t0, -7));
+        t1 = (t1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56);
     }
+
+    return t1;
 }
 
-void do_sdl(int mem_idx)
+void do_sdl(target_ulong t0, target_ulong t1, int mem_idx)
 {
 #ifdef CONFIG_USER_ONLY
 #define stfun stb_raw
@@ -581,31 +532,31 @@ void do_sdl(int mem_idx)
     case 2: stfun = stb_user; break;
     }
 #endif
-    stfun(T0, (uint8_t)(T1 >> 56));
+    stfun(t0, (uint8_t)(t1 >> 56));
 
-    if (GET_LMASK64(T0) <= 6)
-        stfun(GET_OFFSET(T0, 1), (uint8_t)(T1 >> 48));
+    if (GET_LMASK64(t0) <= 6)
+        stfun(GET_OFFSET(t0, 1), (uint8_t)(t1 >> 48));
 
-    if (GET_LMASK64(T0) <= 5)
-        stfun(GET_OFFSET(T0, 2), (uint8_t)(T1 >> 40));
+    if (GET_LMASK64(t0) <= 5)
+        stfun(GET_OFFSET(t0, 2), (uint8_t)(t1 >> 40));
 
-    if (GET_LMASK64(T0) <= 4)
-        stfun(GET_OFFSET(T0, 3), (uint8_t)(T1 >> 32));
+    if (GET_LMASK64(t0) <= 4)
+        stfun(GET_OFFSET(t0, 3), (uint8_t)(t1 >> 32));
 
-    if (GET_LMASK64(T0) <= 3)
-        stfun(GET_OFFSET(T0, 4), (uint8_t)(T1 >> 24));
+    if (GET_LMASK64(t0) <= 3)
+        stfun(GET_OFFSET(t0, 4), (uint8_t)(t1 >> 24));
 
-    if (GET_LMASK64(T0) <= 2)
-        stfun(GET_OFFSET(T0, 5), (uint8_t)(T1 >> 16));
+    if (GET_LMASK64(t0) <= 2)
+        stfun(GET_OFFSET(t0, 5), (uint8_t)(t1 >> 16));
 
-    if (GET_LMASK64(T0) <= 1)
-        stfun(GET_OFFSET(T0, 6), (uint8_t)(T1 >> 8));
+    if (GET_LMASK64(t0) <= 1)
+        stfun(GET_OFFSET(t0, 6), (uint8_t)(t1 >> 8));
 
-    if (GET_LMASK64(T0) <= 0)
-        stfun(GET_OFFSET(T0, 7), (uint8_t)T1);
+    if (GET_LMASK64(t0) <= 0)
+        stfun(GET_OFFSET(t0, 7), (uint8_t)t1);
 }
 
-void do_sdr(int mem_idx)
+void do_sdr(target_ulong t0, target_ulong t1, int mem_idx)
 {
 #ifdef CONFIG_USER_ONLY
 #define stfun stb_raw
@@ -620,28 +571,28 @@ void do_sdr(int mem_idx)
     case 2: stfun = stb_user; break;
     }
 #endif
-    stfun(T0, (uint8_t)T1);
+    stfun(t0, (uint8_t)t1);
 
-    if (GET_LMASK64(T0) >= 1)
-        stfun(GET_OFFSET(T0, -1), (uint8_t)(T1 >> 8));
+    if (GET_LMASK64(t0) >= 1)
+        stfun(GET_OFFSET(t0, -1), (uint8_t)(t1 >> 8));
 
-    if (GET_LMASK64(T0) >= 2)
-        stfun(GET_OFFSET(T0, -2), (uint8_t)(T1 >> 16));
+    if (GET_LMASK64(t0) >= 2)
+        stfun(GET_OFFSET(t0, -2), (uint8_t)(t1 >> 16));
 
-    if (GET_LMASK64(T0) >= 3)
-        stfun(GET_OFFSET(T0, -3), (uint8_t)(T1 >> 24));
+    if (GET_LMASK64(t0) >= 3)
+        stfun(GET_OFFSET(t0, -3), (uint8_t)(t1 >> 24));
 
-    if (GET_LMASK64(T0) >= 4)
-        stfun(GET_OFFSET(T0, -4), (uint8_t)(T1 >> 32));
+    if (GET_LMASK64(t0) >= 4)
+        stfun(GET_OFFSET(t0, -4), (uint8_t)(t1 >> 32));
 
-    if (GET_LMASK64(T0) >= 5)
-        stfun(GET_OFFSET(T0, -5), (uint8_t)(T1 >> 40));
+    if (GET_LMASK64(t0) >= 5)
+        stfun(GET_OFFSET(t0, -5), (uint8_t)(t1 >> 40));
 
-    if (GET_LMASK64(T0) >= 6)
-        stfun(GET_OFFSET(T0, -6), (uint8_t)(T1 >> 48));
+    if (GET_LMASK64(t0) >= 6)
+        stfun(GET_OFFSET(t0, -6), (uint8_t)(t1 >> 48));
 
-    if (GET_LMASK64(T0) == 7)
-        stfun(GET_OFFSET(T0, -7), (uint8_t)(T1 >> 56));
+    if (GET_LMASK64(t0) == 7)
+        stfun(GET_OFFSET(t0, -7), (uint8_t)(t1 >> 56));
 }
 #endif /* TARGET_MIPS64 */
 
@@ -699,203 +650,207 @@ void cpu_mips_tlb_flush (CPUState *env, int flush_global)
 #else
 
 /* CP0 helpers */
-void do_mfc0_mvpcontrol (void)
+target_ulong do_mfc0_mvpcontrol (target_ulong t0)
 {
-    T0 = env->mvp->CP0_MVPControl;
+    return env->mvp->CP0_MVPControl;
 }
 
-void do_mfc0_mvpconf0 (void)
+target_ulong do_mfc0_mvpconf0 (target_ulong t0)
 {
-    T0 = env->mvp->CP0_MVPConf0;
+    return env->mvp->CP0_MVPConf0;
 }
 
-void do_mfc0_mvpconf1 (void)
+target_ulong do_mfc0_mvpconf1 (target_ulong t0)
 {
-    T0 = env->mvp->CP0_MVPConf1;
+    return env->mvp->CP0_MVPConf1;
 }
 
-void do_mfc0_random (void)
+target_ulong do_mfc0_random (target_ulong t0)
 {
-    T0 = (int32_t)cpu_mips_get_random(env);
+    return (int32_t)cpu_mips_get_random(env);
 }
 
-void do_mfc0_tcstatus (void)
+target_ulong do_mfc0_tcstatus (target_ulong t0)
 {
-    T0 = env->CP0_TCStatus[env->current_tc];
+    return env->CP0_TCStatus[env->current_tc];
 }
 
-void do_mftc0_tcstatus(void)
+target_ulong do_mftc0_tcstatus(target_ulong t0)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
-    T0 = env->CP0_TCStatus[other_tc];
+    return env->CP0_TCStatus[other_tc];
 }
 
-void do_mfc0_tcbind (void)
+target_ulong do_mfc0_tcbind (target_ulong t0)
 {
-    T0 = env->CP0_TCBind[env->current_tc];
+    return env->CP0_TCBind[env->current_tc];
 }
 
-void do_mftc0_tcbind(void)
+target_ulong do_mftc0_tcbind(target_ulong t0)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
-    T0 = env->CP0_TCBind[other_tc];
+    return env->CP0_TCBind[other_tc];
 }
 
-void do_mfc0_tcrestart (void)
+target_ulong do_mfc0_tcrestart (target_ulong t0)
 {
-    T0 = env->PC[env->current_tc];
+    return env->PC[env->current_tc];
 }
 
-void do_mftc0_tcrestart(void)
+target_ulong do_mftc0_tcrestart(target_ulong t0)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
-    T0 = env->PC[other_tc];
+    return env->PC[other_tc];
 }
 
-void do_mfc0_tchalt (void)
+target_ulong do_mfc0_tchalt (target_ulong t0)
 {
-    T0 = env->CP0_TCHalt[env->current_tc];
+    return env->CP0_TCHalt[env->current_tc];
 }
 
-void do_mftc0_tchalt(void)
+target_ulong do_mftc0_tchalt(target_ulong t0)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
-    T0 = env->CP0_TCHalt[other_tc];
+    return env->CP0_TCHalt[other_tc];
 }
 
-void do_mfc0_tccontext (void)
+target_ulong do_mfc0_tccontext (target_ulong t0)
 {
-    T0 = env->CP0_TCContext[env->current_tc];
+    return env->CP0_TCContext[env->current_tc];
 }
 
-void do_mftc0_tccontext(void)
+target_ulong do_mftc0_tccontext(target_ulong t0)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
-    T0 = env->CP0_TCContext[other_tc];
+    return env->CP0_TCContext[other_tc];
 }
 
-void do_mfc0_tcschedule (void)
+target_ulong do_mfc0_tcschedule (target_ulong t0)
 {
-    T0 = env->CP0_TCSchedule[env->current_tc];
+    return env->CP0_TCSchedule[env->current_tc];
 }
 
-void do_mftc0_tcschedule(void)
+target_ulong do_mftc0_tcschedule(target_ulong t0)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
-    T0 = env->CP0_TCSchedule[other_tc];
+    return env->CP0_TCSchedule[other_tc];
 }
 
-void do_mfc0_tcschefback (void)
+target_ulong do_mfc0_tcschefback (target_ulong t0)
 {
-    T0 = env->CP0_TCScheFBack[env->current_tc];
+    return env->CP0_TCScheFBack[env->current_tc];
 }
 
-void do_mftc0_tcschefback(void)
+target_ulong do_mftc0_tcschefback(target_ulong t0)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
-    T0 = env->CP0_TCScheFBack[other_tc];
+    return env->CP0_TCScheFBack[other_tc];
 }
 
-void do_mfc0_count (void)
+target_ulong do_mfc0_count (target_ulong t0)
 {
-    T0 = (int32_t)cpu_mips_get_count(env);
+    return (int32_t)cpu_mips_get_count(env);
 }
 
-void do_mftc0_entryhi(void)
+target_ulong do_mftc0_entryhi(target_ulong t0)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
-    T0 = (env->CP0_EntryHi & ~0xff) | (env->CP0_TCStatus[other_tc] & 0xff);
+    return (env->CP0_EntryHi & ~0xff) | (env->CP0_TCStatus[other_tc] & 0xff);
 }
 
-void do_mftc0_status(void)
+target_ulong do_mftc0_status(target_ulong t0)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
     uint32_t tcstatus = env->CP0_TCStatus[other_tc];
 
-    T0 = env->CP0_Status & ~0xf1000018;
-    T0 |= tcstatus & (0xf << CP0TCSt_TCU0);
-    T0 |= (tcstatus & (1 << CP0TCSt_TMX)) >> (CP0TCSt_TMX - CP0St_MX);
-    T0 |= (tcstatus & (0x3 << CP0TCSt_TKSU)) >> (CP0TCSt_TKSU - CP0St_KSU);
+    t0 = env->CP0_Status & ~0xf1000018;
+    t0 |= tcstatus & (0xf << CP0TCSt_TCU0);
+    t0 |= (tcstatus & (1 << CP0TCSt_TMX)) >> (CP0TCSt_TMX - CP0St_MX);
+    t0 |= (tcstatus & (0x3 << CP0TCSt_TKSU)) >> (CP0TCSt_TKSU - CP0St_KSU);
+
+    return t0;
 }
 
-void do_mfc0_lladdr (void)
+target_ulong do_mfc0_lladdr (target_ulong t0)
 {
-    T0 = (int32_t)env->CP0_LLAddr >> 4;
+    return (int32_t)env->CP0_LLAddr >> 4;
 }
 
-void do_mfc0_watchlo (uint32_t sel)
+target_ulong do_mfc0_watchlo (target_ulong t0, uint32_t sel)
 {
-    T0 = (int32_t)env->CP0_WatchLo[sel];
+    return (int32_t)env->CP0_WatchLo[sel];
 }
 
-void do_mfc0_watchhi (uint32_t sel)
+target_ulong do_mfc0_watchhi (target_ulong t0, uint32_t sel)
 {
-    T0 = env->CP0_WatchHi[sel];
+    return env->CP0_WatchHi[sel];
 }
 
-void do_mfc0_debug (void)
+target_ulong do_mfc0_debug (target_ulong t0)
 {
-    T0 = env->CP0_Debug;
+    t0 = env->CP0_Debug;
     if (env->hflags & MIPS_HFLAG_DM)
-        T0 |= 1 << CP0DB_DM;
+        t0 |= 1 << CP0DB_DM;
+
+    return t0;
 }
 
-void do_mftc0_debug(void)
+target_ulong do_mftc0_debug(target_ulong t0)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
     /* XXX: Might be wrong, check with EJTAG spec. */
-    T0 = (env->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
-         (env->CP0_Debug_tcstatus[other_tc] &
-          ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
+    return (env->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
+            (env->CP0_Debug_tcstatus[other_tc] &
+             ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
 }
 
 #if defined(TARGET_MIPS64)
-void do_dmfc0_tcrestart (void)
+target_ulong do_dmfc0_tcrestart (target_ulong t0)
 {
-    T0 = env->PC[env->current_tc];
+    return env->PC[env->current_tc];
 }
 
-void do_dmfc0_tchalt (void)
+target_ulong do_dmfc0_tchalt (target_ulong t0)
 {
-    T0 = env->CP0_TCHalt[env->current_tc];
+    return env->CP0_TCHalt[env->current_tc];
 }
 
-void do_dmfc0_tccontext (void)
+target_ulong do_dmfc0_tccontext (target_ulong t0)
 {
-    T0 = env->CP0_TCContext[env->current_tc];
+    return env->CP0_TCContext[env->current_tc];
 }
 
-void do_dmfc0_tcschedule (void)
+target_ulong do_dmfc0_tcschedule (target_ulong t0)
 {
-    T0 = env->CP0_TCSchedule[env->current_tc];
+    return env->CP0_TCSchedule[env->current_tc];
 }
 
-void do_dmfc0_tcschefback (void)
+target_ulong do_dmfc0_tcschefback (target_ulong t0)
 {
-    T0 = env->CP0_TCScheFBack[env->current_tc];
+    return env->CP0_TCScheFBack[env->current_tc];
 }
 
-void do_dmfc0_lladdr (void)
+target_ulong do_dmfc0_lladdr (target_ulong t0)
 {
-    T0 = env->CP0_LLAddr >> 4;
+    return env->CP0_LLAddr >> 4;
 }
 
-void do_dmfc0_watchlo (uint32_t sel)
+target_ulong do_dmfc0_watchlo (target_ulong t0, uint32_t sel)
 {
-    T0 = env->CP0_WatchLo[sel];
+    return env->CP0_WatchLo[sel];
 }
 #endif /* TARGET_MIPS64 */
 
-void do_mtc0_index (void)
+void do_mtc0_index (target_ulong t0)
 {
     int num = 1;
     unsigned int tmp = env->tlb->nb_tlb;
@@ -904,10 +859,10 @@ void do_mtc0_index (void)
         tmp >>= 1;
         num <<= 1;
     } while (tmp);
-    env->CP0_Index = (env->CP0_Index & 0x80000000) | (T0 & (num - 1));
+    env->CP0_Index = (env->CP0_Index & 0x80000000) | (t0 & (num - 1));
 }
 
-void do_mtc0_mvpcontrol (void)
+void do_mtc0_mvpcontrol (target_ulong t0)
 {
     uint32_t mask = 0;
     uint32_t newval;
@@ -917,21 +872,21 @@ void do_mtc0_mvpcontrol (void)
                 (1 << CP0MVPCo_EVP);
     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
         mask |= (1 << CP0MVPCo_STLB);
-    newval = (env->mvp->CP0_MVPControl & ~mask) | (T0 & mask);
+    newval = (env->mvp->CP0_MVPControl & ~mask) | (t0 & mask);
 
     // TODO: Enable/disable shared TLB, enable/disable VPEs.
 
     env->mvp->CP0_MVPControl = newval;
 }
 
-void do_mtc0_vpecontrol (void)
+void do_mtc0_vpecontrol (target_ulong t0)
 {
     uint32_t mask;
     uint32_t newval;
 
     mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
            (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
-    newval = (env->CP0_VPEControl & ~mask) | (T0 & mask);
+    newval = (env->CP0_VPEControl & ~mask) | (t0 & mask);
 
     /* Yield scheduler intercept not implemented. */
     /* Gating storage scheduler intercept not implemented. */
@@ -941,7 +896,7 @@ void do_mtc0_vpecontrol (void)
     env->CP0_VPEControl = newval;
 }
 
-void do_mtc0_vpeconf0 (void)
+void do_mtc0_vpeconf0 (target_ulong t0)
 {
     uint32_t mask = 0;
     uint32_t newval;
@@ -951,14 +906,14 @@ void do_mtc0_vpeconf0 (void)
             mask |= (0xff << CP0VPEC0_XTC);
         mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
     }
-    newval = (env->CP0_VPEConf0 & ~mask) | (T0 & mask);
+    newval = (env->CP0_VPEConf0 & ~mask) | (t0 & mask);
 
     // TODO: TC exclusive handling due to ERL/EXL.
 
     env->CP0_VPEConf0 = newval;
 }
 
-void do_mtc0_vpeconf1 (void)
+void do_mtc0_vpeconf1 (target_ulong t0)
 {
     uint32_t mask = 0;
     uint32_t newval;
@@ -966,7 +921,7 @@ void do_mtc0_vpeconf1 (void)
     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
         mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
                 (0xff << CP0VPEC1_NCP1);
-    newval = (env->CP0_VPEConf1 & ~mask) | (T0 & mask);
+    newval = (env->CP0_VPEConf1 & ~mask) | (t0 & mask);
 
     /* UDI not implemented. */
     /* CP2 not implemented. */
@@ -976,57 +931,57 @@ void do_mtc0_vpeconf1 (void)
     env->CP0_VPEConf1 = newval;
 }
 
-void do_mtc0_yqmask (void)
+void do_mtc0_yqmask (target_ulong t0)
 {
     /* Yield qualifier inputs not implemented. */
     env->CP0_YQMask = 0x00000000;
 }
 
-void do_mtc0_vpeopt (void)
+void do_mtc0_vpeopt (target_ulong t0)
 {
-    env->CP0_VPEOpt = T0 & 0x0000ffff;
+    env->CP0_VPEOpt = t0 & 0x0000ffff;
 }
 
-void do_mtc0_entrylo0 (void)
+void do_mtc0_entrylo0 (target_ulong t0)
 {
     /* Large physaddr (PABITS) not implemented */
     /* 1k pages not implemented */
-    env->CP0_EntryLo0 = T0 & 0x3FFFFFFF;
+    env->CP0_EntryLo0 = t0 & 0x3FFFFFFF;
 }
 
-void do_mtc0_tcstatus (void)
+void do_mtc0_tcstatus (target_ulong t0)
 {
     uint32_t mask = env->CP0_TCStatus_rw_bitmask;
     uint32_t newval;
 
-    newval = (env->CP0_TCStatus[env->current_tc] & ~mask) | (T0 & mask);
+    newval = (env->CP0_TCStatus[env->current_tc] & ~mask) | (t0 & mask);
 
     // TODO: Sync with CP0_Status.
 
     env->CP0_TCStatus[env->current_tc] = newval;
 }
 
-void do_mttc0_tcstatus (void)
+void do_mttc0_tcstatus (target_ulong t0)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
     // TODO: Sync with CP0_Status.
 
-    env->CP0_TCStatus[other_tc] = T0;
+    env->CP0_TCStatus[other_tc] = t0;
 }
 
-void do_mtc0_tcbind (void)
+void do_mtc0_tcbind (target_ulong t0)
 {
     uint32_t mask = (1 << CP0TCBd_TBE);
     uint32_t newval;
 
     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
         mask |= (1 << CP0TCBd_CurVPE);
-    newval = (env->CP0_TCBind[env->current_tc] & ~mask) | (T0 & mask);
+    newval = (env->CP0_TCBind[env->current_tc] & ~mask) | (t0 & mask);
     env->CP0_TCBind[env->current_tc] = newval;
 }
 
-void do_mttc0_tcbind (void)
+void do_mttc0_tcbind (target_ulong t0)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
     uint32_t mask = (1 << CP0TCBd_TBE);
@@ -1034,99 +989,99 @@ void do_mttc0_tcbind (void)
 
     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
         mask |= (1 << CP0TCBd_CurVPE);
-    newval = (env->CP0_TCBind[other_tc] & ~mask) | (T0 & mask);
+    newval = (env->CP0_TCBind[other_tc] & ~mask) | (t0 & mask);
     env->CP0_TCBind[other_tc] = newval;
 }
 
-void do_mtc0_tcrestart (void)
+void do_mtc0_tcrestart (target_ulong t0)
 {
-    env->PC[env->current_tc] = T0;
+    env->PC[env->current_tc] = t0;
     env->CP0_TCStatus[env->current_tc] &= ~(1 << CP0TCSt_TDS);
     env->CP0_LLAddr = 0ULL;
     /* MIPS16 not implemented. */
 }
 
-void do_mttc0_tcrestart (void)
+void do_mttc0_tcrestart (target_ulong t0)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
-    env->PC[other_tc] = T0;
+    env->PC[other_tc] = t0;
     env->CP0_TCStatus[other_tc] &= ~(1 << CP0TCSt_TDS);
     env->CP0_LLAddr = 0ULL;
     /* MIPS16 not implemented. */
 }
 
-void do_mtc0_tchalt (void)
+void do_mtc0_tchalt (target_ulong t0)
 {
-    env->CP0_TCHalt[env->current_tc] = T0 & 0x1;
+    env->CP0_TCHalt[env->current_tc] = t0 & 0x1;
 
     // TODO: Halt TC / Restart (if allocated+active) TC.
 }
 
-void do_mttc0_tchalt (void)
+void do_mttc0_tchalt (target_ulong t0)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
     // TODO: Halt TC / Restart (if allocated+active) TC.
 
-    env->CP0_TCHalt[other_tc] = T0;
+    env->CP0_TCHalt[other_tc] = t0;
 }
 
-void do_mtc0_tccontext (void)
+void do_mtc0_tccontext (target_ulong t0)
 {
-    env->CP0_TCContext[env->current_tc] = T0;
+    env->CP0_TCContext[env->current_tc] = t0;
 }
 
-void do_mttc0_tccontext (void)
+void do_mttc0_tccontext (target_ulong t0)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
-    env->CP0_TCContext[other_tc] = T0;
+    env->CP0_TCContext[other_tc] = t0;
 }
 
-void do_mtc0_tcschedule (void)
+void do_mtc0_tcschedule (target_ulong t0)
 {
-    env->CP0_TCSchedule[env->current_tc] = T0;
+    env->CP0_TCSchedule[env->current_tc] = t0;
 }
 
-void do_mttc0_tcschedule (void)
+void do_mttc0_tcschedule (target_ulong t0)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
-    env->CP0_TCSchedule[other_tc] = T0;
+    env->CP0_TCSchedule[other_tc] = t0;
 }
 
-void do_mtc0_tcschefback (void)
+void do_mtc0_tcschefback (target_ulong t0)
 {
-    env->CP0_TCScheFBack[env->current_tc] = T0;
+    env->CP0_TCScheFBack[env->current_tc] = t0;
 }
 
-void do_mttc0_tcschefback (void)
+void do_mttc0_tcschefback (target_ulong t0)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
-    env->CP0_TCScheFBack[other_tc] = T0;
+    env->CP0_TCScheFBack[other_tc] = t0;
 }
 
-void do_mtc0_entrylo1 (void)
+void do_mtc0_entrylo1 (target_ulong t0)
 {
     /* Large physaddr (PABITS) not implemented */
     /* 1k pages not implemented */
-    env->CP0_EntryLo1 = T0 & 0x3FFFFFFF;
+    env->CP0_EntryLo1 = t0 & 0x3FFFFFFF;
 }
 
-void do_mtc0_context (void)
+void do_mtc0_context (target_ulong t0)
 {
-    env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (T0 & ~0x007FFFFF);
+    env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (t0 & ~0x007FFFFF);
 }
 
-void do_mtc0_pagemask (void)
+void do_mtc0_pagemask (target_ulong t0)
 {
     /* 1k pages not implemented */
-    env->CP0_PageMask = T0 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
+    env->CP0_PageMask = t0 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
 }
 
-void do_mtc0_pagegrain (void)
+void do_mtc0_pagegrain (target_ulong t0)
 {
     /* SmartMIPS not implemented */
     /* Large physaddr (PABITS) not implemented */
@@ -1134,52 +1089,52 @@ void do_mtc0_pagegrain (void)
     env->CP0_PageGrain = 0;
 }
 
-void do_mtc0_wired (void)
+void do_mtc0_wired (target_ulong t0)
 {
-    env->CP0_Wired = T0 % env->tlb->nb_tlb;
+    env->CP0_Wired = t0 % env->tlb->nb_tlb;
 }
 
-void do_mtc0_srsconf0 (void)
+void do_mtc0_srsconf0 (target_ulong t0)
 {
-    env->CP0_SRSConf0 |= T0 & env->CP0_SRSConf0_rw_bitmask;
+    env->CP0_SRSConf0 |= t0 & env->CP0_SRSConf0_rw_bitmask;
 }
 
-void do_mtc0_srsconf1 (void)
+void do_mtc0_srsconf1 (target_ulong t0)
 {
-    env->CP0_SRSConf1 |= T0 & env->CP0_SRSConf1_rw_bitmask;
+    env->CP0_SRSConf1 |= t0 & env->CP0_SRSConf1_rw_bitmask;
 }
 
-void do_mtc0_srsconf2 (void)
+void do_mtc0_srsconf2 (target_ulong t0)
 {
-    env->CP0_SRSConf2 |= T0 & env->CP0_SRSConf2_rw_bitmask;
+    env->CP0_SRSConf2 |= t0 & env->CP0_SRSConf2_rw_bitmask;
 }
 
-void do_mtc0_srsconf3 (void)
+void do_mtc0_srsconf3 (target_ulong t0)
 {
-    env->CP0_SRSConf3 |= T0 & env->CP0_SRSConf3_rw_bitmask;
+    env->CP0_SRSConf3 |= t0 & env->CP0_SRSConf3_rw_bitmask;
 }
 
-void do_mtc0_srsconf4 (void)
+void do_mtc0_srsconf4 (target_ulong t0)
 {
-    env->CP0_SRSConf4 |= T0 & env->CP0_SRSConf4_rw_bitmask;
+    env->CP0_SRSConf4 |= t0 & env->CP0_SRSConf4_rw_bitmask;
 }
 
-void do_mtc0_hwrena (void)
+void do_mtc0_hwrena (target_ulong t0)
 {
-    env->CP0_HWREna = T0 & 0x0000000F;
+    env->CP0_HWREna = t0 & 0x0000000F;
 }
 
-void do_mtc0_count (void)
+void do_mtc0_count (target_ulong t0)
 {
-    cpu_mips_store_count(env, T0);
+    cpu_mips_store_count(env, t0);
 }
 
-void do_mtc0_entryhi (void)
+void do_mtc0_entryhi (target_ulong t0)
 {
     target_ulong old, val;
 
     /* 1k pages not implemented */
-    val = T0 & ((TARGET_PAGE_MASK << 1) | 0xFF);
+    val = t0 & ((TARGET_PAGE_MASK << 1) | 0xFF);
 #if defined(TARGET_MIPS64)
     val &= env->SEGMask;
 #endif
@@ -1194,25 +1149,25 @@ void do_mtc0_entryhi (void)
         cpu_mips_tlb_flush(env, 1);
 }
 
-void do_mttc0_entryhi(void)
+void do_mttc0_entryhi(target_ulong t0)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
-    env->CP0_EntryHi = (env->CP0_EntryHi & 0xff) | (T0 & ~0xff);
-    env->CP0_TCStatus[other_tc] = (env->CP0_TCStatus[other_tc] & ~0xff) | (T0 & 0xff);
+    env->CP0_EntryHi = (env->CP0_EntryHi & 0xff) | (t0 & ~0xff);
+    env->CP0_TCStatus[other_tc] = (env->CP0_TCStatus[other_tc] & ~0xff) | (t0 & 0xff);
 }
 
-void do_mtc0_compare (void)
+void do_mtc0_compare (target_ulong t0)
 {
-    cpu_mips_store_compare(env, T0);
+    cpu_mips_store_compare(env, t0);
 }
 
-void do_mtc0_status (void)
+void do_mtc0_status (target_ulong t0)
 {
     uint32_t val, old;
     uint32_t mask = env->CP0_Status_rw_bitmask;
 
-    val = T0 & mask;
+    val = t0 & mask;
     old = env->CP0_Status;
     env->CP0_Status = (env->CP0_Status & ~mask) | val;
     compute_hflags(env);
@@ -1221,31 +1176,31 @@ void do_mtc0_status (void)
     cpu_mips_update_irq(env);
 }
 
-void do_mttc0_status(void)
+void do_mttc0_status(target_ulong t0)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
     uint32_t tcstatus = env->CP0_TCStatus[other_tc];
 
-    env->CP0_Status = T0 & ~0xf1000018;
-    tcstatus = (tcstatus & ~(0xf << CP0TCSt_TCU0)) | (T0 & (0xf << CP0St_CU0));
-    tcstatus = (tcstatus & ~(1 << CP0TCSt_TMX)) | ((T0 & (1 << CP0St_MX)) << (CP0TCSt_TMX - CP0St_MX));
-    tcstatus = (tcstatus & ~(0x3 << CP0TCSt_TKSU)) | ((T0 & (0x3 << CP0St_KSU)) << (CP0TCSt_TKSU - CP0St_KSU));
+    env->CP0_Status = t0 & ~0xf1000018;
+    tcstatus = (tcstatus & ~(0xf << CP0TCSt_TCU0)) | (t0 & (0xf << CP0St_CU0));
+    tcstatus = (tcstatus & ~(1 << CP0TCSt_TMX)) | ((t0 & (1 << CP0St_MX)) << (CP0TCSt_TMX - CP0St_MX));
+    tcstatus = (tcstatus & ~(0x3 << CP0TCSt_TKSU)) | ((t0 & (0x3 << CP0St_KSU)) << (CP0TCSt_TKSU - CP0St_KSU));
     env->CP0_TCStatus[other_tc] = tcstatus;
 }
 
-void do_mtc0_intctl (void)
+void do_mtc0_intctl (target_ulong t0)
 {
     /* vectored interrupts not implemented, no performance counters. */
-    env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000002e0) | (T0 & 0x000002e0);
+    env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000002e0) | (t0 & 0x000002e0);
 }
 
-void do_mtc0_srsctl (void)
+void do_mtc0_srsctl (target_ulong t0)
 {
     uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
-    env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (T0 & mask);
+    env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (t0 & mask);
 }
 
-void do_mtc0_cause (void)
+void do_mtc0_cause (target_ulong t0)
 {
     uint32_t mask = 0x00C00300;
     uint32_t old = env->CP0_Cause;
@@ -1253,7 +1208,7 @@ void do_mtc0_cause (void)
     if (env->insn_flags & ISA_MIPS32R2)
         mask |= 1 << CP0Ca_DC;
 
-    env->CP0_Cause = (env->CP0_Cause & ~mask) | (T0 & mask);
+    env->CP0_Cause = (env->CP0_Cause & ~mask) | (t0 & mask);
 
     if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) {
         if (env->CP0_Cause & (1 << CP0Ca_DC))
@@ -1264,95 +1219,95 @@ void do_mtc0_cause (void)
 
     /* Handle the software interrupt as an hardware one, as they
        are very similar */
-    if (T0 & CP0Ca_IP_mask) {
+    if (t0 & CP0Ca_IP_mask) {
         cpu_mips_update_irq(env);
     }
 }
 
-void do_mtc0_ebase (void)
+void do_mtc0_ebase (target_ulong t0)
 {
     /* vectored interrupts not implemented */
     /* Multi-CPU not implemented */
-    env->CP0_EBase = 0x80000000 | (T0 & 0x3FFFF000);
+    env->CP0_EBase = 0x80000000 | (t0 & 0x3FFFF000);
 }
 
-void do_mtc0_config0 (void)
+void do_mtc0_config0 (target_ulong t0)
 {
-    env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (T0 & 0x00000007);
+    env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (t0 & 0x00000007);
 }
 
-void do_mtc0_config2 (void)
+void do_mtc0_config2 (target_ulong t0)
 {
     /* tertiary/secondary caches not implemented */
     env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
 }
 
-void do_mtc0_watchlo (uint32_t sel)
+void do_mtc0_watchlo (target_ulong t0, uint32_t sel)
 {
     /* Watch exceptions for instructions, data loads, data stores
        not implemented. */
-    env->CP0_WatchLo[sel] = (T0 & ~0x7);
+    env->CP0_WatchLo[sel] = (t0 & ~0x7);
 }
 
-void do_mtc0_watchhi (uint32_t sel)
+void do_mtc0_watchhi (target_ulong t0, uint32_t sel)
 {
-    env->CP0_WatchHi[sel] = (T0 & 0x40FF0FF8);
-    env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & T0 & 0x7);
+    env->CP0_WatchHi[sel] = (t0 & 0x40FF0FF8);
+    env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & t0 & 0x7);
 }
 
-void do_mtc0_xcontext (void)
+void do_mtc0_xcontext (target_ulong t0)
 {
     target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
-    env->CP0_XContext = (env->CP0_XContext & mask) | (T0 & ~mask);
+    env->CP0_XContext = (env->CP0_XContext & mask) | (t0 & ~mask);
 }
 
-void do_mtc0_framemask (void)
+void do_mtc0_framemask (target_ulong t0)
 {
-    env->CP0_Framemask = T0; /* XXX */
+    env->CP0_Framemask = t0; /* XXX */
 }
 
-void do_mtc0_debug (void)
+void do_mtc0_debug (target_ulong t0)
 {
-    env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (T0 & 0x13300120);
-    if (T0 & (1 << CP0DB_DM))
+    env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (t0 & 0x13300120);
+    if (t0 & (1 << CP0DB_DM))
         env->hflags |= MIPS_HFLAG_DM;
     else
         env->hflags &= ~MIPS_HFLAG_DM;
 }
 
-void do_mttc0_debug(void)
+void do_mttc0_debug(target_ulong t0)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
     /* XXX: Might be wrong, check with EJTAG spec. */
-    env->CP0_Debug_tcstatus[other_tc] = T0 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
+    env->CP0_Debug_tcstatus[other_tc] = t0 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
     env->CP0_Debug = (env->CP0_Debug & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
-                     (T0 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
+                     (t0 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
 }
 
-void do_mtc0_performance0 (void)
+void do_mtc0_performance0 (target_ulong t0)
 {
-    env->CP0_Performance0 = T0 & 0x000007ff;
+    env->CP0_Performance0 = t0 & 0x000007ff;
 }
 
-void do_mtc0_taglo (void)
+void do_mtc0_taglo (target_ulong t0)
 {
-    env->CP0_TagLo = T0 & 0xFFFFFCF6;
+    env->CP0_TagLo = t0 & 0xFFFFFCF6;
 }
 
-void do_mtc0_datalo (void)
+void do_mtc0_datalo (target_ulong t0)
 {
-    env->CP0_DataLo = T0; /* XXX */
+    env->CP0_DataLo = t0; /* XXX */
 }
 
-void do_mtc0_taghi (void)
+void do_mtc0_taghi (target_ulong t0)
 {
-    env->CP0_TagHi = T0; /* XXX */
+    env->CP0_TagHi = t0; /* XXX */
 }
 
-void do_mtc0_datahi (void)
+void do_mtc0_datahi (target_ulong t0)
 {
-    env->CP0_DataHi = T0; /* XXX */
+    env->CP0_DataHi = t0; /* XXX */
 }
 
 void do_mtc0_status_debug(uint32_t old, uint32_t val)
@@ -1376,117 +1331,127 @@ void do_mtc0_status_irqraise_debug(void)
 #endif /* !CONFIG_USER_ONLY */
 
 /* MIPS MT functions */
-void do_mftgpr(uint32_t sel)
+target_ulong do_mftgpr(target_ulong t0, uint32_t sel)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
-    T0 = env->gpr[other_tc][sel];
+    return env->gpr[other_tc][sel];
 }
 
-void do_mftlo(uint32_t sel)
+target_ulong do_mftlo(target_ulong t0, uint32_t sel)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
-    T0 = env->LO[other_tc][sel];
+    return env->LO[other_tc][sel];
 }
 
-void do_mfthi(uint32_t sel)
+target_ulong do_mfthi(target_ulong t0, uint32_t sel)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
-    T0 = env->HI[other_tc][sel];
+    return env->HI[other_tc][sel];
 }
 
-void do_mftacx(uint32_t sel)
+target_ulong do_mftacx(target_ulong t0, uint32_t sel)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
-    T0 = env->ACX[other_tc][sel];
+    return env->ACX[other_tc][sel];
 }
 
-void do_mftdsp(void)
+target_ulong do_mftdsp(target_ulong t0)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
-    T0 = env->DSPControl[other_tc];
+    return env->DSPControl[other_tc];
 }
 
-void do_mttgpr(uint32_t sel)
+void do_mttgpr(target_ulong t0, uint32_t sel)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
-    T0 = env->gpr[other_tc][sel];
+    env->gpr[other_tc][sel] = t0;
 }
 
-void do_mttlo(uint32_t sel)
+void do_mttlo(target_ulong t0, uint32_t sel)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
-    T0 = env->LO[other_tc][sel];
+    env->LO[other_tc][sel] = t0;
 }
 
-void do_mtthi(uint32_t sel)
+void do_mtthi(target_ulong t0, uint32_t sel)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
-    T0 = env->HI[other_tc][sel];
+    env->HI[other_tc][sel] = t0;
 }
 
-void do_mttacx(uint32_t sel)
+void do_mttacx(target_ulong t0, uint32_t sel)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
-    T0 = env->ACX[other_tc][sel];
+    env->ACX[other_tc][sel] = t0;
 }
 
-void do_mttdsp(void)
+void do_mttdsp(target_ulong t0)
 {
     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 
-    T0 = env->DSPControl[other_tc];
+    env->DSPControl[other_tc] = t0;
 }
 
 /* MIPS MT functions */
-void do_dmt(void)
+target_ulong do_dmt(target_ulong t0)
 {
     // TODO
-    T0 = 0;
-    // rt = T0
+    t0 = 0;
+    // rt = t0
+
+    return t0;
 }
 
-void do_emt(void)
+target_ulong do_emt(target_ulong t0)
 {
     // TODO
-    T0 = 0;
-    // rt = T0
+    t0 = 0;
+    // rt = t0
+
+    return t0;
 }
 
-void do_dvpe(void)
+target_ulong do_dvpe(target_ulong t0)
 {
     // TODO
-    T0 = 0;
-    // rt = T0
+    t0 = 0;
+    // rt = t0
+
+    return t0;
 }
 
-void do_evpe(void)
+target_ulong do_evpe(target_ulong t0)
 {
     // TODO
-    T0 = 0;
-    // rt = T0
+    t0 = 0;
+    // rt = t0
+
+    return t0;
 }
 
-void do_fork(void)
+target_ulong do_fork(target_ulong t0, target_ulong t1)
 {
-    // T0 = rt, T1 = rs
-    T0 = 0;
+    // t0 = rt, t1 = rs
+    t0 = 0;
     // TODO: store to TC register
+
+    return t0;
 }
 
-void do_yield(void)
+target_ulong do_yield(target_ulong t0)
 {
-    if (T0 < 0) {
+    if (t0 < 0) {
         /* No scheduling policy implemented. */
-        if (T0 != -2) {
+        if (t0 != -2) {
             if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
                 env->CP0_TCStatus[env->current_tc] & (1 << CP0TCSt_DT)) {
                 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
@@ -1494,20 +1459,20 @@ void do_yield(void)
                 do_raise_exception(EXCP_THREAD);
             }
         }
-    } else if (T0 == 0) {
+    } else if (t0 == 0) {
 	if (0 /* TODO: TC underflow */) {
             env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
             do_raise_exception(EXCP_THREAD);
         } else {
             // TODO: Deallocate TC
         }
-    } else if (T0 > 0) {
+    } else if (t0 > 0) {
         /* Yield qualifier inputs not implemented. */
         env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
         env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
         do_raise_exception(EXCP_THREAD);
     }
-    T0 = env->CP0_YQMask;
+    return env->CP0_YQMask;
 }
 
 /* CP1 functions */
@@ -1673,33 +1638,23 @@ void r4k_do_tlbr (void)
 
 #endif /* !CONFIG_USER_ONLY */
 
-void dump_ldst (const unsigned char *func)
-{
-    if (loglevel)
-        fprintf(logfile, "%s => " TARGET_FMT_lx " " TARGET_FMT_lx "\n", __func__, T0, T1);
-}
-
-void dump_sc (void)
-{
-    if (loglevel) {
-        fprintf(logfile, "%s " TARGET_FMT_lx " at " TARGET_FMT_lx " (" TARGET_FMT_lx ")\n", __func__,
-                T1, T0, env->CP0_LLAddr);
-    }
-}
-
 /* Specials */
-void do_di (void)
+target_ulong do_di (target_ulong t0)
 {
-    T0 = env->CP0_Status;
-    env->CP0_Status = T0 & ~(1 << CP0St_IE);
+    t0 = env->CP0_Status;
+    env->CP0_Status = t0 & ~(1 << CP0St_IE);
     cpu_mips_update_irq(env);
+
+    return t0;
 }
 
-void do_ei (void)
+target_ulong do_ei (target_ulong t0)
 {
-    T0 = env->CP0_Status;
-    env->CP0_Status = T0 | (1 << CP0St_IE);
+    t0 = env->CP0_Status;
+    env->CP0_Status = t0 | (1 << CP0St_IE);
     cpu_mips_update_irq(env);
+
+    return t0;
 }
 
 void debug_pre_eret (void)
@@ -1729,7 +1684,7 @@ void debug_post_eret (void)
     }
 }
 
-void do_eret (void)
+void do_eret (target_ulong t0)
 {
     if (loglevel & CPU_LOG_EXEC)
         debug_pre_eret();
@@ -1746,7 +1701,7 @@ void do_eret (void)
     env->CP0_LLAddr = 1;
 }
 
-void do_deret (void)
+void do_deret (target_ulong t0)
 {
     if (loglevel & CPU_LOG_EXEC)
         debug_pre_eret();
@@ -1758,82 +1713,90 @@ void do_deret (void)
     env->CP0_LLAddr = 1;
 }
 
-void do_rdhwr_cpunum(void)
+target_ulong do_rdhwr_cpunum(target_ulong t0)
 {
     if ((env->hflags & MIPS_HFLAG_CP0) ||
         (env->CP0_HWREna & (1 << 0)))
-        T0 = env->CP0_EBase & 0x3ff;
+        t0 = env->CP0_EBase & 0x3ff;
     else
         do_raise_exception(EXCP_RI);
+
+    return t0;
 }
 
-void do_rdhwr_synci_step(void)
+target_ulong do_rdhwr_synci_step(target_ulong t0)
 {
     if ((env->hflags & MIPS_HFLAG_CP0) ||
         (env->CP0_HWREna & (1 << 1)))
-        T0 = env->SYNCI_Step;
+        t0 = env->SYNCI_Step;
     else
         do_raise_exception(EXCP_RI);
+
+    return t0;
 }
 
-void do_rdhwr_cc(void)
+target_ulong do_rdhwr_cc(target_ulong t0)
 {
     if ((env->hflags & MIPS_HFLAG_CP0) ||
         (env->CP0_HWREna & (1 << 2)))
-        T0 = env->CP0_Count;
+        t0 = env->CP0_Count;
     else
         do_raise_exception(EXCP_RI);
+
+    return t0;
 }
 
-void do_rdhwr_ccres(void)
+target_ulong do_rdhwr_ccres(target_ulong t0)
 {
     if ((env->hflags & MIPS_HFLAG_CP0) ||
         (env->CP0_HWREna & (1 << 3)))
-        T0 = env->CCRes;
+        t0 = env->CCRes;
     else
         do_raise_exception(EXCP_RI);
+
+    return t0;
 }
 
 /* Bitfield operations. */
-void do_ext(uint32_t pos, uint32_t size)
+target_ulong do_ext(target_ulong t0, target_ulong t1, uint32_t pos, uint32_t size)
 {
-    T0 = (int32_t)((T1 >> pos) & ((size < 32) ? ((1 << size) - 1) : ~0));
+    return (int32_t)((t1 >> pos) & ((size < 32) ? ((1 << size) - 1) : ~0));
 }
 
-void do_ins(uint32_t pos, uint32_t size)
+target_ulong do_ins(target_ulong t0, target_ulong t1, uint32_t pos, uint32_t size)
 {
     target_ulong mask = ((size < 32) ? ((1 << size) - 1) : ~0) << pos;
 
-    T0 = (int32_t)((T0 & ~mask) | ((T1 << pos) & mask));
+    return (int32_t)((t0 & ~mask) | ((t1 << pos) & mask));
 }
 
-void do_wsbh(void)
+target_ulong do_wsbh(target_ulong t0, target_ulong t1)
 {
-    T0 = (int32_t)(((T1 << 8) & ~0x00FF00FF) | ((T1 >> 8) & 0x00FF00FF));
+    return (int32_t)(((t1 << 8) & ~0x00FF00FF) | ((t1 >> 8) & 0x00FF00FF));
 }
 
 #if defined(TARGET_MIPS64)
-void do_dext(uint32_t pos, uint32_t size)
+target_ulong do_dext(target_ulong t0, target_ulong t1, uint32_t pos, uint32_t size)
 {
-    T0 = (T1 >> pos) & ((size < 64) ? ((1ULL << size) - 1) : ~0ULL);
+    return (t1 >> pos) & ((size < 64) ? ((1ULL << size) - 1) : ~0ULL);
 }
 
-void do_dins(uint32_t pos, uint32_t size)
+target_ulong do_dins(target_ulong t0, target_ulong t1, uint32_t pos, uint32_t size)
 {
     target_ulong mask = ((size < 64) ? ((1ULL << size) - 1) : ~0ULL) << pos;
 
-    T0 = (T0 & ~mask) | ((T1 << pos) & mask);
+    return (t0 & ~mask) | ((t1 << pos) & mask);
 }
 
-void do_dsbh(void)
+target_ulong do_dsbh(target_ulong t0, target_ulong t1)
 {
-    T0 = ((T1 << 8) & ~0x00FF00FF00FF00FFULL) | ((T1 >> 8) & 0x00FF00FF00FF00FFULL);
+    return ((t1 << 8) & ~0x00FF00FF00FF00FFULL) | ((t1 >> 8) & 0x00FF00FF00FF00FFULL);
 }
 
-void do_dshd(void)
+target_ulong do_dshd(target_ulong t0, target_ulong t1)
 {
-    T1 = ((T1 << 16) & ~0x0000FFFF0000FFFFULL) | ((T1 >> 16) & 0x0000FFFF0000FFFFULL);
-    T0 = (T1 << 32) | (T1 >> 32);
+    t1 = ((t1 << 16) & ~0x0000FFFF0000FFFFULL) | ((t1 >> 16) & 0x0000FFFF0000FFFFULL);
+    return (t1 << 32) | (t1 >> 32);
 }
 #endif
 
@@ -1955,51 +1918,53 @@ unsigned int ieee_rm[] = {
 #define RESTORE_ROUNDING_MODE \
     set_float_rounding_mode(ieee_rm[env->fpu->fcr31 & 3], &env->fpu->fp_status)
 
-void do_cfc1 (uint32_t reg)
+target_ulong do_cfc1 (target_ulong t0, uint32_t reg)
 {
     switch (reg) {
     case 0:
-        T0 = (int32_t)env->fpu->fcr0;
+        t0 = (int32_t)env->fpu->fcr0;
         break;
     case 25:
-        T0 = ((env->fpu->fcr31 >> 24) & 0xfe) | ((env->fpu->fcr31 >> 23) & 0x1);
+        t0 = ((env->fpu->fcr31 >> 24) & 0xfe) | ((env->fpu->fcr31 >> 23) & 0x1);
         break;
     case 26:
-        T0 = env->fpu->fcr31 & 0x0003f07c;
+        t0 = env->fpu->fcr31 & 0x0003f07c;
         break;
     case 28:
-        T0 = (env->fpu->fcr31 & 0x00000f83) | ((env->fpu->fcr31 >> 22) & 0x4);
+        t0 = (env->fpu->fcr31 & 0x00000f83) | ((env->fpu->fcr31 >> 22) & 0x4);
         break;
     default:
-        T0 = (int32_t)env->fpu->fcr31;
+        t0 = (int32_t)env->fpu->fcr31;
         break;
     }
+
+    return t0;
 }
 
-void do_ctc1 (uint32_t reg)
+void do_ctc1 (target_ulong t0, uint32_t reg)
 {
     switch(reg) {
     case 25:
-        if (T0 & 0xffffff00)
+        if (t0 & 0xffffff00)
             return;
-        env->fpu->fcr31 = (env->fpu->fcr31 & 0x017fffff) | ((T0 & 0xfe) << 24) |
-                     ((T0 & 0x1) << 23);
+        env->fpu->fcr31 = (env->fpu->fcr31 & 0x017fffff) | ((t0 & 0xfe) << 24) |
+                     ((t0 & 0x1) << 23);
         break;
     case 26:
-        if (T0 & 0x007c0000)
+        if (t0 & 0x007c0000)
             return;
-        env->fpu->fcr31 = (env->fpu->fcr31 & 0xfffc0f83) | (T0 & 0x0003f07c);
+        env->fpu->fcr31 = (env->fpu->fcr31 & 0xfffc0f83) | (t0 & 0x0003f07c);
         break;
     case 28:
-        if (T0 & 0x007c0000)
+        if (t0 & 0x007c0000)
             return;
-        env->fpu->fcr31 = (env->fpu->fcr31 & 0xfefff07c) | (T0 & 0x00000f83) |
-                     ((T0 & 0x4) << 22);
+        env->fpu->fcr31 = (env->fpu->fcr31 & 0xfefff07c) | (t0 & 0x00000f83) |
+                     ((t0 & 0x4) << 22);
         break;
     case 31:
-        if (T0 & 0x007c0000)
+        if (t0 & 0x007c0000)
             return;
-        env->fpu->fcr31 = T0;
+        env->fpu->fcr31 = t0;
         break;
     default:
         return;
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 9fdf836a09..3d135cc604 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -428,22 +428,74 @@ static TCGv cpu_env, current_tc_gprs, current_tc_hi, current_fpu, cpu_T[2];
 /* FPU TNs, global for now. */
 static TCGv fpu32_T[3], fpu64_T[3], fpu32h_T[3];
 
-static inline void tcg_gen_helper_0_1i(void *func, TCGv arg)
+static inline void tcg_gen_helper_0_i(void *func, TCGv arg)
 {
-    TCGv t = tcg_const_i32(arg);
+    TCGv tmp = tcg_const_i32(arg);
 
-    tcg_gen_helper_0_1(func, t);
-    tcg_temp_free(t);
+    tcg_gen_helper_0_1(func, tmp);
+    tcg_temp_free(tmp);
 }
 
-static inline void tcg_gen_helper_0_2ii(void *func, TCGv arg1, TCGv arg2)
+static inline void tcg_gen_helper_0_ii(void *func, TCGv arg1, TCGv arg2)
 {
-    TCGv t1 = tcg_const_i32(arg1);
-    TCGv t2 = tcg_const_i32(arg2);
+    TCGv tmp1 = tcg_const_i32(arg1);
+    TCGv tmp2 = tcg_const_i32(arg2);
 
-    tcg_gen_helper_0_2(func, t1, t2);
-    tcg_temp_free(t1);
-    tcg_temp_free(t2);
+    tcg_gen_helper_0_2(func, tmp1, tmp2);
+    tcg_temp_free(tmp1);
+    tcg_temp_free(tmp2);
+}
+
+static inline void tcg_gen_helper_0_1i(void *func, TCGv arg1, TCGv arg2)
+{
+    TCGv tmp = tcg_const_i32(arg2);
+
+    tcg_gen_helper_0_2(func, arg1, tmp);
+    tcg_temp_free(tmp);
+}
+
+static inline void tcg_gen_helper_0_2i(void *func, TCGv arg1, TCGv arg2, TCGv arg3)
+{
+    TCGv tmp = tcg_const_i32(arg3);
+
+    tcg_gen_helper_0_3(func, arg1, arg2, tmp);
+    tcg_temp_free(tmp);
+}
+
+static inline void tcg_gen_helper_0_2ii(void *func, TCGv arg1, TCGv arg2, TCGv arg3, TCGv arg4)
+{
+    TCGv tmp1 = tcg_const_i32(arg3);
+    TCGv tmp2 = tcg_const_i32(arg3);
+
+    tcg_gen_helper_0_4(func, arg1, arg2, tmp1, tmp2);
+    tcg_temp_free(tmp1);
+    tcg_temp_free(tmp2);
+}
+
+static inline void tcg_gen_helper_1_1i(void *func, TCGv ret, TCGv arg1, TCGv arg2)
+{
+    TCGv tmp = tcg_const_i32(arg2);
+
+    tcg_gen_helper_1_2(func, ret, arg1, tmp);
+    tcg_temp_free(tmp);
+}
+
+static inline void tcg_gen_helper_1_2i(void *func, TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3)
+{
+    TCGv tmp = tcg_const_i32(arg3);
+
+    tcg_gen_helper_1_3(func, ret, arg1, arg2, tmp);
+    tcg_temp_free(tmp);
+}
+
+static inline void tcg_gen_helper_1_2ii(void *func, TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, TCGv arg4)
+{
+    TCGv tmp1 = tcg_const_i32(arg3);
+    TCGv tmp2 = tcg_const_i32(arg3);
+
+    tcg_gen_helper_1_4(func, ret, arg1, arg2, tmp1, tmp2);
+    tcg_temp_free(tmp1);
+    tcg_temp_free(tmp2);
 }
 
 typedef struct DisasContext {
@@ -540,37 +592,44 @@ static inline void gen_store_HI (TCGv t, int reg)
 }
 
 /* Moves to/from shadow registers. */
-static inline void gen_load_srsgpr (TCGv t, int reg)
+static inline void gen_load_srsgpr (int from, int to)
 {
-    if (reg == 0)
-        tcg_gen_movi_tl(t, 0);
+    TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_TL);
+
+    if (from == 0)
+        tcg_gen_movi_tl(r_tmp1, 0);
     else {
-        TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32);
+        TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I32);
 
-        tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSCtl));
-        tcg_gen_shri_i32(r_tmp, r_tmp, CP0SRSCtl_PSS);
-        tcg_gen_andi_i32(r_tmp, r_tmp, 0xf);
-        tcg_gen_muli_i32(r_tmp, r_tmp, sizeof(target_ulong) * 32);
-        tcg_gen_add_i32(r_tmp, cpu_env, r_tmp);
+        tcg_gen_ld_i32(r_tmp2, cpu_env, offsetof(CPUState, CP0_SRSCtl));
+        tcg_gen_shri_i32(r_tmp2, r_tmp2, CP0SRSCtl_PSS);
+        tcg_gen_andi_i32(r_tmp2, r_tmp2, 0xf);
+        tcg_gen_muli_i32(r_tmp2, r_tmp2, sizeof(target_ulong) * 32);
+        tcg_gen_add_i32(r_tmp2, cpu_env, r_tmp2);
 
-        tcg_gen_ld_tl(t, r_tmp, sizeof(target_ulong) * reg);
-        tcg_temp_free(r_tmp);
+        tcg_gen_ld_tl(r_tmp1, r_tmp2, sizeof(target_ulong) * from);
+        tcg_temp_free(r_tmp2);
     }
+    gen_store_gpr(r_tmp1, to);
+    tcg_temp_free(r_tmp1);
 }
 
-static inline void gen_store_srsgpr (TCGv t, int reg)
+static inline void gen_store_srsgpr (int from, int to)
 {
-    if (reg != 0) {
-        TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32);
+    if (to != 0) {
+        TCGv r_tmp1 = tcg_temp_new(TCG_TYPE_TL);
+        TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I32);
 
-        tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_SRSCtl));
-        tcg_gen_shri_i32(r_tmp, r_tmp, CP0SRSCtl_PSS);
-        tcg_gen_andi_i32(r_tmp, r_tmp, 0xf);
-        tcg_gen_muli_i32(r_tmp, r_tmp, sizeof(target_ulong) * 32);
-        tcg_gen_add_i32(r_tmp, cpu_env, r_tmp);
+        gen_load_gpr(r_tmp1, from);
+        tcg_gen_ld_i32(r_tmp2, cpu_env, offsetof(CPUState, CP0_SRSCtl));
+        tcg_gen_shri_i32(r_tmp2, r_tmp2, CP0SRSCtl_PSS);
+        tcg_gen_andi_i32(r_tmp2, r_tmp2, 0xf);
+        tcg_gen_muli_i32(r_tmp2, r_tmp2, sizeof(target_ulong) * 32);
+        tcg_gen_add_i32(r_tmp2, cpu_env, r_tmp2);
 
-        tcg_gen_st_tl(t, r_tmp, sizeof(target_ulong) * reg);
-        tcg_temp_free(r_tmp);
+        tcg_gen_st_tl(r_tmp1, r_tmp2, sizeof(target_ulong) * to);
+        tcg_temp_free(r_tmp1);
+        tcg_temp_free(r_tmp2);
     }
 }
 
@@ -666,7 +725,7 @@ static GenOpFunc1 * fcmp ## type ## _ ## fmt ## _table[16] = {            \
 };                                                                        \
 static inline void gen_cmp ## type ## _ ## fmt(int n, long cc)            \
 {                                                                         \
-    tcg_gen_helper_0_1i(fcmp ## type ## _ ## fmt ## _table[n], cc);       \
+    tcg_gen_helper_0_i(fcmp ## type ## _ ## fmt ## _table[n], cc);        \
 }
 
 FOP_CONDS(, d)
@@ -679,16 +738,16 @@ FOP_CONDS(abs, ps)
 
 /* Tests */
 #define OP_COND(name, cond)                                   \
-void glue(gen_op_, name) (void)                               \
+void glue(gen_op_, name) (TCGv t0, TCGv t1)                   \
 {                                                             \
     int l1 = gen_new_label();                                 \
     int l2 = gen_new_label();                                 \
                                                               \
-    tcg_gen_brcond_tl(cond, cpu_T[0], cpu_T[1], l1);          \
-    tcg_gen_movi_tl(cpu_T[0], 0);                             \
+    tcg_gen_brcond_tl(cond, t0, t1, l1);                      \
+    tcg_gen_movi_tl(t0, 0);                                   \
     tcg_gen_br(l2);                                           \
     gen_set_label(l1);                                        \
-    tcg_gen_movi_tl(cpu_T[0], 1);                             \
+    tcg_gen_movi_tl(t0, 1);                                   \
     gen_set_label(l2);                                        \
 }
 OP_COND(eq, TCG_COND_EQ);
@@ -700,16 +759,16 @@ OP_COND(ltu, TCG_COND_LTU);
 #undef OP_COND
 
 #define OP_CONDI(name, cond)                                  \
-void glue(gen_op_, name) (target_ulong val)                   \
+void glue(gen_op_, name) (TCGv t, target_ulong val)           \
 {                                                             \
     int l1 = gen_new_label();                                 \
     int l2 = gen_new_label();                                 \
                                                               \
-    tcg_gen_brcondi_tl(cond, cpu_T[0], val, l1);              \
-    tcg_gen_movi_tl(cpu_T[0], 0);                             \
+    tcg_gen_brcondi_tl(cond, t, val, l1);                     \
+    tcg_gen_movi_tl(t, 0);                                    \
     tcg_gen_br(l2);                                           \
     gen_set_label(l1);                                        \
-    tcg_gen_movi_tl(cpu_T[0], 1);                             \
+    tcg_gen_movi_tl(t, 1);                                    \
     gen_set_label(l2);                                        \
 }
 OP_CONDI(lti, TCG_COND_LT);
@@ -717,16 +776,16 @@ OP_CONDI(ltiu, TCG_COND_LTU);
 #undef OP_CONDI
 
 #define OP_CONDZ(name, cond)                                  \
-void glue(gen_op_, name) (void)                               \
+void glue(gen_op_, name) (TCGv t)                             \
 {                                                             \
     int l1 = gen_new_label();                                 \
     int l2 = gen_new_label();                                 \
                                                               \
-    tcg_gen_brcondi_tl(cond, cpu_T[0], 0, l1);                \
-    tcg_gen_movi_tl(cpu_T[0], 0);                             \
+    tcg_gen_brcondi_tl(cond, t, 0, l1);                       \
+    tcg_gen_movi_tl(t, 0);                                    \
     tcg_gen_br(l2);                                           \
     gen_set_label(l1);                                        \
-    tcg_gen_movi_tl(cpu_T[0], 1);                             \
+    tcg_gen_movi_tl(t, 1);                                    \
     gen_set_label(l2);                                        \
 }
 OP_CONDZ(gez, TCG_COND_GE);
@@ -840,7 +899,7 @@ static always_inline void
 generate_exception_err (DisasContext *ctx, int excp, int err)
 {
     save_cpu_state(ctx, 1);
-    tcg_gen_helper_0_2ii(do_raise_exception_err, excp, err);
+    tcg_gen_helper_0_ii(do_raise_exception_err, excp, err);
     tcg_gen_helper_0_0(do_interrupt_restart);
     tcg_gen_exit_tb(0);
 }
@@ -849,15 +908,15 @@ static always_inline void
 generate_exception (DisasContext *ctx, int excp)
 {
     save_cpu_state(ctx, 1);
-    tcg_gen_helper_0_1i(do_raise_exception, excp);
+    tcg_gen_helper_0_i(do_raise_exception, excp);
     tcg_gen_helper_0_0(do_interrupt_restart);
     tcg_gen_exit_tb(0);
 }
 
 /* Addresses computation */
-static inline void gen_op_addr_add (void)
+static inline void gen_op_addr_add (TCGv t0, TCGv t1)
 {
-    tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
+    tcg_gen_add_tl(t0, t0, t1);
 
 #if defined(TARGET_MIPS64)
     /* For compatibility with 32-bit code, data reference in user mode
@@ -874,7 +933,7 @@ static inline void gen_op_addr_add (void)
         tcg_gen_andi_i32(r_tmp, r_tmp, (1 << CP0St_UX));
         tcg_gen_brcondi_i32(TCG_COND_NE, r_tmp, 0, l1);
         tcg_temp_free(r_tmp);
-        tcg_gen_ext32s_i64(cpu_T[0], cpu_T[0]);
+        tcg_gen_ext32s_i64(t0, t0);
         gen_set_label(l1);
     }
 #endif
@@ -946,9 +1005,9 @@ static always_inline void check_mips_64(DisasContext *ctx)
 
 /* load/store instructions. */
 #define OP_LD(insn,fname)                                        \
-void inline op_ldst_##insn(DisasContext *ctx)                    \
+void inline op_ldst_##insn(TCGv t0, DisasContext *ctx)           \
 {                                                                \
-    tcg_gen_qemu_##fname(cpu_T[0], cpu_T[0], ctx->mem_idx);      \
+    tcg_gen_qemu_##fname(t0, t0, ctx->mem_idx);                  \
 }
 OP_LD(lb,ld8s);
 OP_LD(lbu,ld8u);
@@ -962,9 +1021,9 @@ OP_LD(ld,ld64);
 #undef OP_LD
 
 #define OP_ST(insn,fname)                                        \
-void inline op_ldst_##insn(DisasContext *ctx)                    \
+void inline op_ldst_##insn(TCGv t0, TCGv t1, DisasContext *ctx)  \
 {                                                                \
-    tcg_gen_qemu_##fname(cpu_T[1], cpu_T[0], ctx->mem_idx);      \
+    tcg_gen_qemu_##fname(t1, t0, ctx->mem_idx);                  \
 }
 OP_ST(sb,st8);
 OP_ST(sh,st16);
@@ -975,11 +1034,11 @@ OP_ST(sd,st64);
 #undef OP_ST
 
 #define OP_LD_ATOMIC(insn,fname)                                        \
-void inline op_ldst_##insn(DisasContext *ctx)                           \
+void inline op_ldst_##insn(TCGv t0, TCGv t1, DisasContext *ctx)         \
 {                                                                       \
-    tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);                                 \
-    tcg_gen_qemu_##fname(cpu_T[0], cpu_T[0], ctx->mem_idx);             \
-    tcg_gen_st_tl(cpu_T[1], cpu_env, offsetof(CPUState, CP0_LLAddr));   \
+    tcg_gen_mov_tl(t1, t0);                                             \
+    tcg_gen_qemu_##fname(t0, t0, ctx->mem_idx);                         \
+    tcg_gen_st_tl(t1, cpu_env, offsetof(CPUState, CP0_LLAddr));         \
 }
 OP_LD_ATOMIC(ll,ld32s);
 #if defined(TARGET_MIPS64)
@@ -988,26 +1047,26 @@ OP_LD_ATOMIC(lld,ld64);
 #undef OP_LD_ATOMIC
 
 #define OP_ST_ATOMIC(insn,fname,almask)                                 \
-void inline op_ldst_##insn(DisasContext *ctx)                           \
+void inline op_ldst_##insn(TCGv t0, TCGv t1, DisasContext *ctx)         \
 {                                                                       \
     TCGv r_tmp = tcg_temp_local_new(TCG_TYPE_TL);                       \
     int l1 = gen_new_label();                                           \
     int l2 = gen_new_label();                                           \
     int l3 = gen_new_label();                                           \
                                                                         \
-    tcg_gen_andi_tl(r_tmp, cpu_T[0], almask);                           \
+    tcg_gen_andi_tl(r_tmp, t0, almask);                                 \
     tcg_gen_brcondi_tl(TCG_COND_EQ, r_tmp, 0, l1);                      \
-    tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, CP0_BadVAddr)); \
+    tcg_gen_st_tl(t0, cpu_env, offsetof(CPUState, CP0_BadVAddr));       \
     generate_exception(ctx, EXCP_AdES);                                 \
     gen_set_label(l1);                                                  \
     tcg_gen_ld_tl(r_tmp, cpu_env, offsetof(CPUState, CP0_LLAddr));      \
-    tcg_gen_brcond_tl(TCG_COND_NE, cpu_T[0], r_tmp, l2);                \
+    tcg_gen_brcond_tl(TCG_COND_NE, t0, r_tmp, l2);                      \
     tcg_temp_free(r_tmp);                                               \
-    tcg_gen_qemu_##fname(cpu_T[1], cpu_T[0], ctx->mem_idx);             \
-    tcg_gen_movi_tl(cpu_T[0], 1);                                       \
+    tcg_gen_qemu_##fname(t1, t0, ctx->mem_idx);                         \
+    tcg_gen_movi_tl(t0, 1);                                             \
     tcg_gen_br(l3);                                                     \
     gen_set_label(l2);                                                  \
-    tcg_gen_movi_tl(cpu_T[0], 0);                                       \
+    tcg_gen_movi_tl(t0, 0);                                             \
     gen_set_label(l3);                                                  \
 }
 OP_ST_ATOMIC(sc,st32,0x3);
@@ -1029,141 +1088,141 @@ static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt,
     } else {
         gen_load_gpr(cpu_T[0], base);
         tcg_gen_movi_tl(cpu_T[1], offset);
-        gen_op_addr_add();
+        gen_op_addr_add(cpu_T[0], cpu_T[1]);
     }
     /* Don't do NOP if destination is zero: we must perform the actual
        memory access. */
     switch (opc) {
 #if defined(TARGET_MIPS64)
     case OPC_LWU:
-        op_ldst_lwu(ctx);
+        op_ldst_lwu(cpu_T[0], ctx);
         gen_store_gpr(cpu_T[0], rt);
         opn = "lwu";
         break;
     case OPC_LD:
-        op_ldst_ld(ctx);
+        op_ldst_ld(cpu_T[0], ctx);
         gen_store_gpr(cpu_T[0], rt);
         opn = "ld";
         break;
     case OPC_LLD:
-        op_ldst_lld(ctx);
+        op_ldst_lld(cpu_T[0], cpu_T[1], ctx);
         gen_store_gpr(cpu_T[0], rt);
         opn = "lld";
         break;
     case OPC_SD:
         gen_load_gpr(cpu_T[1], rt);
-        op_ldst_sd(ctx);
+        op_ldst_sd(cpu_T[0], cpu_T[1], ctx);
         opn = "sd";
         break;
     case OPC_SCD:
         save_cpu_state(ctx, 1);
         gen_load_gpr(cpu_T[1], rt);
-        op_ldst_scd(ctx);
+        op_ldst_scd(cpu_T[0], cpu_T[1], ctx);
         gen_store_gpr(cpu_T[0], rt);
         opn = "scd";
         break;
     case OPC_LDL:
         save_cpu_state(ctx, 1);
         gen_load_gpr(cpu_T[1], rt);
-        tcg_gen_helper_0_1i(do_ldl, ctx->mem_idx);
+        tcg_gen_helper_1_2i(do_ldl, cpu_T[1], cpu_T[0], cpu_T[1], ctx->mem_idx);
         gen_store_gpr(cpu_T[1], rt);
         opn = "ldl";
         break;
     case OPC_SDL:
         save_cpu_state(ctx, 1);
         gen_load_gpr(cpu_T[1], rt);
-        tcg_gen_helper_0_1i(do_sdl, ctx->mem_idx);
+        tcg_gen_helper_0_2i(do_sdl, cpu_T[0], cpu_T[1], ctx->mem_idx);
         opn = "sdl";
         break;
     case OPC_LDR:
         save_cpu_state(ctx, 1);
         gen_load_gpr(cpu_T[1], rt);
-        tcg_gen_helper_0_1i(do_ldr, ctx->mem_idx);
+        tcg_gen_helper_1_2i(do_ldr, cpu_T[1], cpu_T[0], cpu_T[1], ctx->mem_idx);
         gen_store_gpr(cpu_T[1], rt);
         opn = "ldr";
         break;
     case OPC_SDR:
         save_cpu_state(ctx, 1);
         gen_load_gpr(cpu_T[1], rt);
-        tcg_gen_helper_0_1i(do_sdr, ctx->mem_idx);
+        tcg_gen_helper_0_2i(do_sdr, cpu_T[0], cpu_T[1], ctx->mem_idx);
         opn = "sdr";
         break;
 #endif
     case OPC_LW:
-        op_ldst_lw(ctx);
+        op_ldst_lw(cpu_T[0], ctx);
         gen_store_gpr(cpu_T[0], rt);
         opn = "lw";
         break;
     case OPC_SW:
         gen_load_gpr(cpu_T[1], rt);
-        op_ldst_sw(ctx);
+        op_ldst_sw(cpu_T[0], cpu_T[1], ctx);
         opn = "sw";
         break;
     case OPC_LH:
-        op_ldst_lh(ctx);
+        op_ldst_lh(cpu_T[0], ctx);
         gen_store_gpr(cpu_T[0], rt);
         opn = "lh";
         break;
     case OPC_SH:
         gen_load_gpr(cpu_T[1], rt);
-        op_ldst_sh(ctx);
+        op_ldst_sh(cpu_T[0], cpu_T[1], ctx);
         opn = "sh";
         break;
     case OPC_LHU:
-        op_ldst_lhu(ctx);
+        op_ldst_lhu(cpu_T[0], ctx);
         gen_store_gpr(cpu_T[0], rt);
         opn = "lhu";
         break;
     case OPC_LB:
-        op_ldst_lb(ctx);
+        op_ldst_lb(cpu_T[0], ctx);
         gen_store_gpr(cpu_T[0], rt);
         opn = "lb";
         break;
     case OPC_SB:
         gen_load_gpr(cpu_T[1], rt);
-        op_ldst_sb(ctx);
+        op_ldst_sb(cpu_T[0], cpu_T[1], ctx);
         opn = "sb";
         break;
     case OPC_LBU:
-        op_ldst_lbu(ctx);
+        op_ldst_lbu(cpu_T[0], ctx);
         gen_store_gpr(cpu_T[0], rt);
         opn = "lbu";
         break;
     case OPC_LWL:
         save_cpu_state(ctx, 1);
 	gen_load_gpr(cpu_T[1], rt);
-        tcg_gen_helper_0_1i(do_lwl, ctx->mem_idx);
+        tcg_gen_helper_1_2i(do_lwl, cpu_T[1], cpu_T[0], cpu_T[1], ctx->mem_idx);
         gen_store_gpr(cpu_T[1], rt);
         opn = "lwl";
         break;
     case OPC_SWL:
         save_cpu_state(ctx, 1);
         gen_load_gpr(cpu_T[1], rt);
-        tcg_gen_helper_0_1i(do_swl, ctx->mem_idx);
+        tcg_gen_helper_0_2i(do_swl, cpu_T[0], cpu_T[1], ctx->mem_idx);
         opn = "swr";
         break;
     case OPC_LWR:
         save_cpu_state(ctx, 1);
 	gen_load_gpr(cpu_T[1], rt);
-        tcg_gen_helper_0_1i(do_lwr, ctx->mem_idx);
+        tcg_gen_helper_1_2i(do_lwr, cpu_T[1], cpu_T[0], cpu_T[1], ctx->mem_idx);
         gen_store_gpr(cpu_T[1], rt);
         opn = "lwr";
         break;
     case OPC_SWR:
         save_cpu_state(ctx, 1);
         gen_load_gpr(cpu_T[1], rt);
-        tcg_gen_helper_0_1i(do_swr, ctx->mem_idx);
+        tcg_gen_helper_0_2i(do_swr, cpu_T[0], cpu_T[1], ctx->mem_idx);
         opn = "swr";
         break;
     case OPC_LL:
-        op_ldst_ll(ctx);
+        op_ldst_ll(cpu_T[0], cpu_T[1], ctx);
         gen_store_gpr(cpu_T[0], rt);
         opn = "ll";
         break;
     case OPC_SC:
         save_cpu_state(ctx, 1);
         gen_load_gpr(cpu_T[1], rt);
-        op_ldst_sc(ctx);
+        op_ldst_sc(cpu_T[0], cpu_T[1], ctx);
         gen_store_gpr(cpu_T[0], rt);
         opn = "sc";
         break;
@@ -1188,7 +1247,7 @@ static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft,
     } else {
         gen_load_gpr(cpu_T[0], base);
         tcg_gen_movi_tl(cpu_T[1], offset);
-        gen_op_addr_add();
+        gen_op_addr_add(cpu_T[0], cpu_T[1]);
     }
     /* Don't do NOP if destination is zero: we must perform the actual
        memory access. */
@@ -1245,7 +1304,6 @@ static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc,
     case OPC_SLTI:
     case OPC_SLTIU:
         uimm = (target_long)imm; /* Sign extend to 32/64 bits */
-        tcg_gen_movi_tl(cpu_T[1], uimm);
         /* Fall through. */
     case OPC_ANDI:
     case OPC_ORI:
@@ -1334,11 +1392,11 @@ static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc,
         break;
 #endif
     case OPC_SLTI:
-        gen_op_lti(uimm);
+        gen_op_lti(cpu_T[0], uimm);
         opn = "slti";
         break;
     case OPC_SLTIU:
-        gen_op_ltiu(uimm);
+        gen_op_ltiu(cpu_T[0], uimm);
         opn = "sltiu";
         break;
     case OPC_ANDI:
@@ -1645,11 +1703,11 @@ static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc,
         break;
 #endif
     case OPC_SLT:
-        gen_op_lt();
+        gen_op_lt(cpu_T[0], cpu_T[1]);
         opn = "slt";
         break;
     case OPC_SLTU:
-        gen_op_ltu();
+        gen_op_ltu(cpu_T[0], cpu_T[1]);
         opn = "sltu";
         break;
     case OPC_AND:
@@ -2031,11 +2089,11 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
         opn = "ddivu";
         break;
     case OPC_DMULT:
-        tcg_gen_helper_0_0(do_dmult);
+        tcg_gen_helper_0_2(do_dmult, cpu_T[0], cpu_T[1]);
         opn = "dmult";
         break;
     case OPC_DMULTU:
-        tcg_gen_helper_0_0(do_dmultu);
+        tcg_gen_helper_0_2(do_dmultu, cpu_T[0], cpu_T[1]);
         opn = "dmultu";
         break;
 #endif
@@ -2181,59 +2239,59 @@ static void gen_mul_vr54xx (DisasContext *ctx, uint32_t opc,
 
     switch (opc) {
     case OPC_VR54XX_MULS:
-        tcg_gen_helper_0_0(do_muls);
+        tcg_gen_helper_1_2(do_muls, cpu_T[0], cpu_T[0], cpu_T[1]);
         opn = "muls";
 	break;
     case OPC_VR54XX_MULSU:
-        tcg_gen_helper_0_0(do_mulsu);
+        tcg_gen_helper_1_2(do_mulsu, cpu_T[0], cpu_T[0], cpu_T[1]);
         opn = "mulsu";
 	break;
     case OPC_VR54XX_MACC:
-        tcg_gen_helper_0_0(do_macc);
+        tcg_gen_helper_1_2(do_macc, cpu_T[0], cpu_T[0], cpu_T[1]);
         opn = "macc";
 	break;
     case OPC_VR54XX_MACCU:
-        tcg_gen_helper_0_0(do_maccu);
+        tcg_gen_helper_1_2(do_maccu, cpu_T[0], cpu_T[0], cpu_T[1]);
         opn = "maccu";
 	break;
     case OPC_VR54XX_MSAC:
-        tcg_gen_helper_0_0(do_msac);
+        tcg_gen_helper_1_2(do_msac, cpu_T[0], cpu_T[0], cpu_T[1]);
         opn = "msac";
 	break;
     case OPC_VR54XX_MSACU:
-        tcg_gen_helper_0_0(do_msacu);
+        tcg_gen_helper_1_2(do_msacu, cpu_T[0], cpu_T[0], cpu_T[1]);
         opn = "msacu";
 	break;
     case OPC_VR54XX_MULHI:
-        tcg_gen_helper_0_0(do_mulhi);
+        tcg_gen_helper_1_2(do_mulhi, cpu_T[0], cpu_T[0], cpu_T[1]);
         opn = "mulhi";
 	break;
     case OPC_VR54XX_MULHIU:
-        tcg_gen_helper_0_0(do_mulhiu);
+        tcg_gen_helper_1_2(do_mulhiu, cpu_T[0], cpu_T[0], cpu_T[1]);
         opn = "mulhiu";
 	break;
     case OPC_VR54XX_MULSHI:
-        tcg_gen_helper_0_0(do_mulshi);
+        tcg_gen_helper_1_2(do_mulshi, cpu_T[0], cpu_T[0], cpu_T[1]);
         opn = "mulshi";
 	break;
     case OPC_VR54XX_MULSHIU:
-        tcg_gen_helper_0_0(do_mulshiu);
+        tcg_gen_helper_1_2(do_mulshiu, cpu_T[0], cpu_T[0], cpu_T[1]);
         opn = "mulshiu";
 	break;
     case OPC_VR54XX_MACCHI:
-        tcg_gen_helper_0_0(do_macchi);
+        tcg_gen_helper_1_2(do_macchi, cpu_T[0], cpu_T[0], cpu_T[1]);
         opn = "macchi";
 	break;
     case OPC_VR54XX_MACCHIU:
-        tcg_gen_helper_0_0(do_macchiu);
+        tcg_gen_helper_1_2(do_macchiu, cpu_T[0], cpu_T[0], cpu_T[1]);
         opn = "macchiu";
 	break;
     case OPC_VR54XX_MSACHI:
-        tcg_gen_helper_0_0(do_msachi);
+        tcg_gen_helper_1_2(do_msachi, cpu_T[0], cpu_T[0], cpu_T[1]);
         opn = "msachi";
 	break;
     case OPC_VR54XX_MSACHIU:
-        tcg_gen_helper_0_0(do_msachiu);
+        tcg_gen_helper_1_2(do_msachiu, cpu_T[0], cpu_T[0], cpu_T[1]);
         opn = "msachiu";
 	break;
     default:
@@ -2257,20 +2315,20 @@ static void gen_cl (DisasContext *ctx, uint32_t opc,
     gen_load_gpr(cpu_T[0], rs);
     switch (opc) {
     case OPC_CLO:
-        tcg_gen_helper_0_0(do_clo);
+        tcg_gen_helper_1_1(do_clo, cpu_T[0], cpu_T[0]);
         opn = "clo";
         break;
     case OPC_CLZ:
-        tcg_gen_helper_0_0(do_clz);
+        tcg_gen_helper_1_1(do_clz, cpu_T[0], cpu_T[0]);
         opn = "clz";
         break;
 #if defined(TARGET_MIPS64)
     case OPC_DCLO:
-        tcg_gen_helper_0_0(do_dclo);
+        tcg_gen_helper_1_1(do_dclo, cpu_T[0], cpu_T[0]);
         opn = "dclo";
         break;
     case OPC_DCLZ:
-        tcg_gen_helper_0_0(do_dclz);
+        tcg_gen_helper_1_1(do_dclz, cpu_T[0], cpu_T[0]);
         opn = "dclz";
         break;
 #endif
@@ -2288,6 +2346,8 @@ static void gen_trap (DisasContext *ctx, uint32_t opc,
                       int rs, int rt, int16_t imm)
 {
     int cond;
+    TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
+    TCGv t1 = tcg_temp_local_new(TCG_TYPE_TL);
 
     cond = 0;
     /* Load needed operands */
@@ -2300,8 +2360,8 @@ static void gen_trap (DisasContext *ctx, uint32_t opc,
     case OPC_TNE:
         /* Compare two registers */
         if (rs != rt) {
-            gen_load_gpr(cpu_T[0], rs);
-            gen_load_gpr(cpu_T[1], rt);
+            gen_load_gpr(t0, rs);
+            gen_load_gpr(t1, rt);
             cond = 1;
         }
         break;
@@ -2313,8 +2373,8 @@ static void gen_trap (DisasContext *ctx, uint32_t opc,
     case OPC_TNEI:
         /* Compare register to immediate */
         if (rs != 0 || imm != 0) {
-            gen_load_gpr(cpu_T[0], rs);
-            tcg_gen_movi_tl(cpu_T[1], (int32_t)imm);
+            gen_load_gpr(t0, rs);
+            tcg_gen_movi_tl(t1, (int32_t)imm);
             cond = 1;
         }
         break;
@@ -2328,7 +2388,7 @@ static void gen_trap (DisasContext *ctx, uint32_t opc,
         case OPC_TGEU:  /* rs >= rs unsigned */
         case OPC_TGEIU: /* r0 >= 0  unsigned */
             /* Always trap */
-            tcg_gen_movi_tl(cpu_T[0], 1);
+            tcg_gen_movi_tl(t0, 1);
             break;
         case OPC_TLT:   /* rs < rs           */
         case OPC_TLTI:  /* r0 < 0            */
@@ -2337,53 +2397,56 @@ static void gen_trap (DisasContext *ctx, uint32_t opc,
         case OPC_TNE:   /* rs != rs          */
         case OPC_TNEI:  /* r0 != 0           */
             /* Never trap: treat as NOP. */
-            return;
+            goto out;
         default:
             MIPS_INVAL("trap");
             generate_exception(ctx, EXCP_RI);
-            return;
+            goto out;
         }
     } else {
         switch (opc) {
         case OPC_TEQ:
         case OPC_TEQI:
-            gen_op_eq();
+            gen_op_eq(t0, t1);
             break;
         case OPC_TGE:
         case OPC_TGEI:
-            gen_op_ge();
+            gen_op_ge(t0, t1);
             break;
         case OPC_TGEU:
         case OPC_TGEIU:
-            gen_op_geu();
+            gen_op_geu(t0, t1);
             break;
         case OPC_TLT:
         case OPC_TLTI:
-            gen_op_lt();
+            gen_op_lt(t0, t1);
             break;
         case OPC_TLTU:
         case OPC_TLTIU:
-            gen_op_ltu();
+            gen_op_ltu(t0, t1);
             break;
         case OPC_TNE:
         case OPC_TNEI:
-            gen_op_ne();
+            gen_op_ne(t0, t1);
             break;
         default:
             MIPS_INVAL("trap");
             generate_exception(ctx, EXCP_RI);
-            return;
+            goto out;
         }
     }
     save_cpu_state(ctx, 1);
     {
         int l1 = gen_new_label();
 
-        tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_T[0], 0, l1);
-        tcg_gen_helper_0_1i(do_raise_exception, EXCP_TRAP);
+        tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
+        tcg_gen_helper_0_i(do_raise_exception, EXCP_TRAP);
         gen_set_label(l1);
     }
     ctx->bstate = BS_STOP;
+ out:
+    tcg_temp_free(t0);
+    tcg_temp_free(t1);
 }
 
 static always_inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
@@ -2546,69 +2609,69 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
     } else {
         switch (opc) {
         case OPC_BEQ:
-            gen_op_eq();
+            gen_op_eq(cpu_T[0], cpu_T[1]);
             MIPS_DEBUG("beq %s, %s, " TARGET_FMT_lx,
                        regnames[rs], regnames[rt], btarget);
             goto not_likely;
         case OPC_BEQL:
-            gen_op_eq();
+            gen_op_eq(cpu_T[0], cpu_T[1]);
             MIPS_DEBUG("beql %s, %s, " TARGET_FMT_lx,
                        regnames[rs], regnames[rt], btarget);
             goto likely;
         case OPC_BNE:
-            gen_op_ne();
+            gen_op_ne(cpu_T[0], cpu_T[1]);
             MIPS_DEBUG("bne %s, %s, " TARGET_FMT_lx,
                        regnames[rs], regnames[rt], btarget);
             goto not_likely;
         case OPC_BNEL:
-            gen_op_ne();
+            gen_op_ne(cpu_T[0], cpu_T[1]);
             MIPS_DEBUG("bnel %s, %s, " TARGET_FMT_lx,
                        regnames[rs], regnames[rt], btarget);
             goto likely;
         case OPC_BGEZ:
-            gen_op_gez();
+            gen_op_gez(cpu_T[0]);
             MIPS_DEBUG("bgez %s, " TARGET_FMT_lx, regnames[rs], btarget);
             goto not_likely;
         case OPC_BGEZL:
-            gen_op_gez();
+            gen_op_gez(cpu_T[0]);
             MIPS_DEBUG("bgezl %s, " TARGET_FMT_lx, regnames[rs], btarget);
             goto likely;
         case OPC_BGEZAL:
-            gen_op_gez();
+            gen_op_gez(cpu_T[0]);
             MIPS_DEBUG("bgezal %s, " TARGET_FMT_lx, regnames[rs], btarget);
             blink = 31;
             goto not_likely;
         case OPC_BGEZALL:
-            gen_op_gez();
+            gen_op_gez(cpu_T[0]);
             blink = 31;
             MIPS_DEBUG("bgezall %s, " TARGET_FMT_lx, regnames[rs], btarget);
             goto likely;
         case OPC_BGTZ:
-            gen_op_gtz();
+            gen_op_gtz(cpu_T[0]);
             MIPS_DEBUG("bgtz %s, " TARGET_FMT_lx, regnames[rs], btarget);
             goto not_likely;
         case OPC_BGTZL:
-            gen_op_gtz();
+            gen_op_gtz(cpu_T[0]);
             MIPS_DEBUG("bgtzl %s, " TARGET_FMT_lx, regnames[rs], btarget);
             goto likely;
         case OPC_BLEZ:
-            gen_op_lez();
+            gen_op_lez(cpu_T[0]);
             MIPS_DEBUG("blez %s, " TARGET_FMT_lx, regnames[rs], btarget);
             goto not_likely;
         case OPC_BLEZL:
-            gen_op_lez();
+            gen_op_lez(cpu_T[0]);
             MIPS_DEBUG("blezl %s, " TARGET_FMT_lx, regnames[rs], btarget);
             goto likely;
         case OPC_BLTZ:
-            gen_op_ltz();
+            gen_op_ltz(cpu_T[0]);
             MIPS_DEBUG("bltz %s, " TARGET_FMT_lx, regnames[rs], btarget);
             goto not_likely;
         case OPC_BLTZL:
-            gen_op_ltz();
+            gen_op_ltz(cpu_T[0]);
             MIPS_DEBUG("bltzl %s, " TARGET_FMT_lx, regnames[rs], btarget);
             goto likely;
         case OPC_BLTZAL:
-            gen_op_ltz();
+            gen_op_ltz(cpu_T[0]);
             blink = 31;
             MIPS_DEBUG("bltzal %s, " TARGET_FMT_lx, regnames[rs], btarget);
         not_likely:
@@ -2616,7 +2679,7 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
             tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUState, bcond));
             break;
         case OPC_BLTZALL:
-            gen_op_ltz();
+            gen_op_ltz(cpu_T[0]);
             blink = 31;
             MIPS_DEBUG("bltzall %s, " TARGET_FMT_lx, regnames[rs], btarget);
         likely:
@@ -2648,49 +2711,49 @@ static void gen_bitops (DisasContext *ctx, uint32_t opc, int rt,
     case OPC_EXT:
         if (lsb + msb > 31)
             goto fail;
-        tcg_gen_helper_0_2ii(do_ext, lsb, msb + 1);
+        tcg_gen_helper_1_2ii(do_ext, cpu_T[0], cpu_T[0], cpu_T[1], lsb, msb + 1);
         break;
 #if defined(TARGET_MIPS64)
     case OPC_DEXTM:
         if (lsb + msb > 63)
             goto fail;
-        tcg_gen_helper_0_2ii(do_dext, lsb, msb + 1 + 32);
+        tcg_gen_helper_1_2ii(do_dext, cpu_T[0], cpu_T[0], cpu_T[1], lsb, msb + 1 + 32);
         break;
     case OPC_DEXTU:
         if (lsb + msb > 63)
             goto fail;
-        tcg_gen_helper_0_2ii(do_dext, lsb + 32, msb + 1);
+        tcg_gen_helper_1_2ii(do_dext, cpu_T[0], cpu_T[0], cpu_T[1], lsb + 32, msb + 1);
         break;
     case OPC_DEXT:
         if (lsb + msb > 63)
             goto fail;
-        tcg_gen_helper_0_2ii(do_dext, lsb, msb + 1);
+        tcg_gen_helper_1_2ii(do_dext, cpu_T[0], cpu_T[0], cpu_T[1], lsb, msb + 1);
         break;
 #endif
     case OPC_INS:
         if (lsb > msb)
             goto fail;
         gen_load_gpr(cpu_T[0], rt);
-        tcg_gen_helper_0_2ii(do_ins, lsb, msb - lsb + 1);
+        tcg_gen_helper_1_2ii(do_ins, cpu_T[0], cpu_T[0], cpu_T[1], lsb, msb - lsb + 1);
         break;
 #if defined(TARGET_MIPS64)
     case OPC_DINSM:
         if (lsb > msb)
             goto fail;
         gen_load_gpr(cpu_T[0], rt);
-        tcg_gen_helper_0_2ii(do_dins, lsb, msb - lsb + 1 + 32);
+        tcg_gen_helper_1_2ii(do_dins, cpu_T[0], cpu_T[0], cpu_T[1], lsb, msb - lsb + 1 + 32);
         break;
     case OPC_DINSU:
         if (lsb > msb)
             goto fail;
         gen_load_gpr(cpu_T[0], rt);
-        tcg_gen_helper_0_2ii(do_dins, lsb + 32, msb - lsb + 1);
+        tcg_gen_helper_1_2ii(do_dins, cpu_T[0], cpu_T[0], cpu_T[1], lsb + 32, msb - lsb + 1);
         break;
     case OPC_DINS:
         if (lsb > msb)
             goto fail;
         gen_load_gpr(cpu_T[0], rt);
-        tcg_gen_helper_0_2ii(do_dins, lsb, msb - lsb + 1);
+        tcg_gen_helper_1_2ii(do_dins, cpu_T[0], cpu_T[0], cpu_T[1], lsb, msb - lsb + 1);
         break;
 #endif
     default:
@@ -2750,17 +2813,17 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
             break;
         case 1:
             check_insn(env, ctx, ASE_MT);
-            tcg_gen_helper_0_0(do_mfc0_mvpcontrol);
+            tcg_gen_helper_1_1(do_mfc0_mvpcontrol, cpu_T[0], cpu_T[0]);
             rn = "MVPControl";
             break;
         case 2:
             check_insn(env, ctx, ASE_MT);
-            tcg_gen_helper_0_0(do_mfc0_mvpconf0);
+            tcg_gen_helper_1_1(do_mfc0_mvpconf0, cpu_T[0], cpu_T[0]);
             rn = "MVPConf0";
             break;
         case 3:
             check_insn(env, ctx, ASE_MT);
-            tcg_gen_helper_0_0(do_mfc0_mvpconf1);
+            tcg_gen_helper_1_1(do_mfc0_mvpconf1, cpu_T[0], cpu_T[0]);
             rn = "MVPConf1";
             break;
         default:
@@ -2770,7 +2833,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
     case 1:
         switch (sel) {
         case 0:
-            tcg_gen_helper_0_0(do_mfc0_random);
+            tcg_gen_helper_1_1(do_mfc0_random, cpu_T[0], cpu_T[0]);
             rn = "Random";
             break;
         case 1:
@@ -2821,37 +2884,37 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
             break;
         case 1:
             check_insn(env, ctx, ASE_MT);
-            tcg_gen_helper_0_0(do_mfc0_tcstatus);
+            tcg_gen_helper_1_1(do_mfc0_tcstatus, cpu_T[0], cpu_T[0]);
             rn = "TCStatus";
             break;
         case 2:
             check_insn(env, ctx, ASE_MT);
-            tcg_gen_helper_0_0(do_mfc0_tcbind);
+            tcg_gen_helper_1_1(do_mfc0_tcbind, cpu_T[0], cpu_T[0]);
             rn = "TCBind";
             break;
         case 3:
             check_insn(env, ctx, ASE_MT);
-            tcg_gen_helper_0_0(do_mfc0_tcrestart);
+            tcg_gen_helper_1_1(do_mfc0_tcrestart, cpu_T[0], cpu_T[0]);
             rn = "TCRestart";
             break;
         case 4:
             check_insn(env, ctx, ASE_MT);
-            tcg_gen_helper_0_0(do_mfc0_tchalt);
+            tcg_gen_helper_1_1(do_mfc0_tchalt, cpu_T[0], cpu_T[0]);
             rn = "TCHalt";
             break;
         case 5:
             check_insn(env, ctx, ASE_MT);
-            tcg_gen_helper_0_0(do_mfc0_tccontext);
+            tcg_gen_helper_1_1(do_mfc0_tccontext, cpu_T[0], cpu_T[0]);
             rn = "TCContext";
             break;
         case 6:
             check_insn(env, ctx, ASE_MT);
-            tcg_gen_helper_0_0(do_mfc0_tcschedule);
+            tcg_gen_helper_1_1(do_mfc0_tcschedule, cpu_T[0], cpu_T[0]);
             rn = "TCSchedule";
             break;
         case 7:
             check_insn(env, ctx, ASE_MT);
-            tcg_gen_helper_0_0(do_mfc0_tcschefback);
+            tcg_gen_helper_1_1(do_mfc0_tcschefback, cpu_T[0], cpu_T[0]);
             rn = "TCScheFBack";
             break;
         default:
@@ -2877,7 +2940,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
             rn = "Context";
             break;
         case 1:
-//            tcg_gen_helper_0_0(do_mfc0_contextconfig); /* SmartMIPS ASE */
+//            tcg_gen_helper_1_1(do_mfc0_contextconfig, cpu_T[0], cpu_T[0]); /* SmartMIPS ASE */
             rn = "ContextConfig";
 //            break;
         default:
@@ -2959,7 +3022,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
     case 9:
         switch (sel) {
         case 0:
-            tcg_gen_helper_0_0(do_mfc0_count);
+            tcg_gen_helper_1_1(do_mfc0_count, cpu_T[0], cpu_T[0]);
             rn = "Count";
             break;
         /* 6,7 are implementation dependent */
@@ -3085,7 +3148,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
     case 17:
         switch (sel) {
         case 0:
-            tcg_gen_helper_0_0(do_mfc0_lladdr);
+            tcg_gen_helper_1_1(do_mfc0_lladdr, cpu_T[0], cpu_T[0]);
             rn = "LLAddr";
             break;
         default:
@@ -3095,7 +3158,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
     case 18:
         switch (sel) {
         case 0 ... 7:
-            tcg_gen_helper_0_1i(do_mfc0_watchlo, sel);
+            tcg_gen_helper_1_1i(do_mfc0_watchlo, cpu_T[0], cpu_T[0], sel);
             rn = "WatchLo";
             break;
         default:
@@ -3105,7 +3168,7 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
     case 19:
         switch (sel) {
         case 0 ...7:
-            tcg_gen_helper_0_1i(do_mfc0_watchhi, sel);
+            tcg_gen_helper_1_1i(do_mfc0_watchhi, cpu_T[0], cpu_T[0], sel);
             rn = "WatchHi";
             break;
         default:
@@ -3144,23 +3207,23 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
     case 23:
         switch (sel) {
         case 0:
-            tcg_gen_helper_0_0(do_mfc0_debug); /* EJTAG support */
+            tcg_gen_helper_1_1(do_mfc0_debug, cpu_T[0], cpu_T[0]); /* EJTAG support */
             rn = "Debug";
             break;
         case 1:
-//            tcg_gen_helper_0_0(do_mfc0_tracecontrol); /* PDtrace support */
+//            tcg_gen_helper_1_1(do_mfc0_tracecontrol, cpu_T[0], cpu_T[0]); /* PDtrace support */
             rn = "TraceControl";
 //            break;
         case 2:
-//            tcg_gen_helper_0_0(do_mfc0_tracecontrol2); /* PDtrace support */
+//            tcg_gen_helper_1_1(do_mfc0_tracecontrol2, cpu_T[0], cpu_T[0]); /* PDtrace support */
             rn = "TraceControl2";
 //            break;
         case 3:
-//            tcg_gen_helper_0_0(do_mfc0_usertracedata); /* PDtrace support */
+//            tcg_gen_helper_1_1(do_mfc0_usertracedata, cpu_T[0], cpu_T[0]); /* PDtrace support */
             rn = "UserTraceData";
 //            break;
         case 4:
-//            tcg_gen_helper_0_0(do_mfc0_debug); /* PDtrace support */
+//            tcg_gen_helper_1_1(do_mfc0_tracebpc, cpu_T[0], cpu_T[0]); /* PDtrace support */
             rn = "TraceBPC";
 //            break;
         default:
@@ -3186,31 +3249,31 @@ static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
             rn = "Performance0";
             break;
         case 1:
-//            tcg_gen_helper_0_0(do_mfc0_performance1);
+//            tcg_gen_helper_1_1(do_mfc0_performance1, cpu_T[0], cpu_T[0]);
             rn = "Performance1";
 //            break;
         case 2:
-//            tcg_gen_helper_0_0(do_mfc0_performance2);
+//            tcg_gen_helper_1_1(do_mfc0_performance2, cpu_T[0], cpu_T[0]);
             rn = "Performance2";
 //            break;
         case 3:
-//            tcg_gen_helper_0_0(do_mfc0_performance3);
+//            tcg_gen_helper_1_1(do_mfc0_performance3, cpu_T[0], cpu_T[0]);
             rn = "Performance3";
 //            break;
         case 4:
-//            tcg_gen_helper_0_0(do_mfc0_performance4);
+//            tcg_gen_helper_1_1(do_mfc0_performance4, cpu_T[0], cpu_T[0]);
             rn = "Performance4";
 //            break;
         case 5:
-//            tcg_gen_helper_0_0(do_mfc0_performance5);
+//            tcg_gen_helper_1_1(do_mfc0_performance5, cpu_T[0], cpu_T[0]);
             rn = "Performance5";
 //            break;
         case 6:
-//            tcg_gen_helper_0_0(do_mfc0_performance6);
+//            tcg_gen_helper_1_1(do_mfc0_performance6, cpu_T[0], cpu_T[0]);
             rn = "Performance6";
 //            break;
         case 7:
-//            tcg_gen_helper_0_0(do_mfc0_performance7);
+//            tcg_gen_helper_1_1(do_mfc0_performance7, cpu_T[0], cpu_T[0]);
             rn = "Performance7";
 //            break;
         default:
@@ -3324,12 +3387,12 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
     case 0:
         switch (sel) {
         case 0:
-            tcg_gen_helper_0_0(do_mtc0_index);
+            tcg_gen_helper_0_1(do_mtc0_index, cpu_T[0]);
             rn = "Index";
             break;
         case 1:
             check_insn(env, ctx, ASE_MT);
-            tcg_gen_helper_0_0(do_mtc0_mvpcontrol);
+            tcg_gen_helper_0_1(do_mtc0_mvpcontrol, cpu_T[0]);
             rn = "MVPControl";
             break;
         case 2:
@@ -3354,22 +3417,22 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
             break;
         case 1:
             check_insn(env, ctx, ASE_MT);
-            tcg_gen_helper_0_0(do_mtc0_vpecontrol);
+            tcg_gen_helper_0_1(do_mtc0_vpecontrol, cpu_T[0]);
             rn = "VPEControl";
             break;
         case 2:
             check_insn(env, ctx, ASE_MT);
-            tcg_gen_helper_0_0(do_mtc0_vpeconf0);
+            tcg_gen_helper_0_1(do_mtc0_vpeconf0, cpu_T[0]);
             rn = "VPEConf0";
             break;
         case 3:
             check_insn(env, ctx, ASE_MT);
-            tcg_gen_helper_0_0(do_mtc0_vpeconf1);
+            tcg_gen_helper_0_1(do_mtc0_vpeconf1, cpu_T[0]);
             rn = "VPEConf1";
             break;
         case 4:
             check_insn(env, ctx, ASE_MT);
-            tcg_gen_helper_0_0(do_mtc0_yqmask);
+            tcg_gen_helper_0_1(do_mtc0_yqmask, cpu_T[0]);
             rn = "YQMask";
             break;
         case 5:
@@ -3384,7 +3447,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
             break;
         case 7:
             check_insn(env, ctx, ASE_MT);
-            tcg_gen_helper_0_0(do_mtc0_vpeopt);
+            tcg_gen_helper_0_1(do_mtc0_vpeopt, cpu_T[0]);
             rn = "VPEOpt";
             break;
         default:
@@ -3394,42 +3457,42 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
     case 2:
         switch (sel) {
         case 0:
-            tcg_gen_helper_0_0(do_mtc0_entrylo0);
+            tcg_gen_helper_0_1(do_mtc0_entrylo0, cpu_T[0]);
             rn = "EntryLo0";
             break;
         case 1:
             check_insn(env, ctx, ASE_MT);
-            tcg_gen_helper_0_0(do_mtc0_tcstatus);
+            tcg_gen_helper_0_1(do_mtc0_tcstatus, cpu_T[0]);
             rn = "TCStatus";
             break;
         case 2:
             check_insn(env, ctx, ASE_MT);
-            tcg_gen_helper_0_0(do_mtc0_tcbind);
+            tcg_gen_helper_0_1(do_mtc0_tcbind, cpu_T[0]);
             rn = "TCBind";
             break;
         case 3:
             check_insn(env, ctx, ASE_MT);
-            tcg_gen_helper_0_0(do_mtc0_tcrestart);
+            tcg_gen_helper_0_1(do_mtc0_tcrestart, cpu_T[0]);
             rn = "TCRestart";
             break;
         case 4:
             check_insn(env, ctx, ASE_MT);
-            tcg_gen_helper_0_0(do_mtc0_tchalt);
+            tcg_gen_helper_0_1(do_mtc0_tchalt, cpu_T[0]);
             rn = "TCHalt";
             break;
         case 5:
             check_insn(env, ctx, ASE_MT);
-            tcg_gen_helper_0_0(do_mtc0_tccontext);
+            tcg_gen_helper_0_1(do_mtc0_tccontext, cpu_T[0]);
             rn = "TCContext";
             break;
         case 6:
             check_insn(env, ctx, ASE_MT);
-            tcg_gen_helper_0_0(do_mtc0_tcschedule);
+            tcg_gen_helper_0_1(do_mtc0_tcschedule, cpu_T[0]);
             rn = "TCSchedule";
             break;
         case 7:
             check_insn(env, ctx, ASE_MT);
-            tcg_gen_helper_0_0(do_mtc0_tcschefback);
+            tcg_gen_helper_0_1(do_mtc0_tcschefback, cpu_T[0]);
             rn = "TCScheFBack";
             break;
         default:
@@ -3439,7 +3502,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
     case 3:
         switch (sel) {
         case 0:
-            tcg_gen_helper_0_0(do_mtc0_entrylo1);
+            tcg_gen_helper_0_1(do_mtc0_entrylo1, cpu_T[0]);
             rn = "EntryLo1";
             break;
         default:
@@ -3449,11 +3512,11 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
     case 4:
         switch (sel) {
         case 0:
-            tcg_gen_helper_0_0(do_mtc0_context);
+            tcg_gen_helper_0_1(do_mtc0_context, cpu_T[0]);
             rn = "Context";
             break;
         case 1:
-//            tcg_gen_helper_0_0(do_mtc0_contextconfig); /* SmartMIPS ASE */
+//            tcg_gen_helper_0_1(do_mtc0_contextconfig, cpu_T[0]); /* SmartMIPS ASE */
             rn = "ContextConfig";
 //            break;
         default:
@@ -3463,12 +3526,12 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
     case 5:
         switch (sel) {
         case 0:
-            tcg_gen_helper_0_0(do_mtc0_pagemask);
+            tcg_gen_helper_0_1(do_mtc0_pagemask, cpu_T[0]);
             rn = "PageMask";
             break;
         case 1:
             check_insn(env, ctx, ISA_MIPS32R2);
-            tcg_gen_helper_0_0(do_mtc0_pagegrain);
+            tcg_gen_helper_0_1(do_mtc0_pagegrain, cpu_T[0]);
             rn = "PageGrain";
             break;
         default:
@@ -3478,32 +3541,32 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
     case 6:
         switch (sel) {
         case 0:
-            tcg_gen_helper_0_0(do_mtc0_wired);
+            tcg_gen_helper_0_1(do_mtc0_wired, cpu_T[0]);
             rn = "Wired";
             break;
         case 1:
             check_insn(env, ctx, ISA_MIPS32R2);
-            tcg_gen_helper_0_0(do_mtc0_srsconf0);
+            tcg_gen_helper_0_1(do_mtc0_srsconf0, cpu_T[0]);
             rn = "SRSConf0";
             break;
         case 2:
             check_insn(env, ctx, ISA_MIPS32R2);
-            tcg_gen_helper_0_0(do_mtc0_srsconf1);
+            tcg_gen_helper_0_1(do_mtc0_srsconf1, cpu_T[0]);
             rn = "SRSConf1";
             break;
         case 3:
             check_insn(env, ctx, ISA_MIPS32R2);
-            tcg_gen_helper_0_0(do_mtc0_srsconf2);
+            tcg_gen_helper_0_1(do_mtc0_srsconf2, cpu_T[0]);
             rn = "SRSConf2";
             break;
         case 4:
             check_insn(env, ctx, ISA_MIPS32R2);
-            tcg_gen_helper_0_0(do_mtc0_srsconf3);
+            tcg_gen_helper_0_1(do_mtc0_srsconf3, cpu_T[0]);
             rn = "SRSConf3";
             break;
         case 5:
             check_insn(env, ctx, ISA_MIPS32R2);
-            tcg_gen_helper_0_0(do_mtc0_srsconf4);
+            tcg_gen_helper_0_1(do_mtc0_srsconf4, cpu_T[0]);
             rn = "SRSConf4";
             break;
         default:
@@ -3514,7 +3577,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
         switch (sel) {
         case 0:
             check_insn(env, ctx, ISA_MIPS32R2);
-            tcg_gen_helper_0_0(do_mtc0_hwrena);
+            tcg_gen_helper_0_1(do_mtc0_hwrena, cpu_T[0]);
             rn = "HWREna";
             break;
         default:
@@ -3528,7 +3591,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
     case 9:
         switch (sel) {
         case 0:
-            tcg_gen_helper_0_0(do_mtc0_count);
+            tcg_gen_helper_0_1(do_mtc0_count, cpu_T[0]);
             rn = "Count";
             break;
         /* 6,7 are implementation dependent */
@@ -3541,7 +3604,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
     case 10:
         switch (sel) {
         case 0:
-            tcg_gen_helper_0_0(do_mtc0_entryhi);
+            tcg_gen_helper_0_1(do_mtc0_entryhi, cpu_T[0]);
             rn = "EntryHi";
             break;
         default:
@@ -3551,7 +3614,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
     case 11:
         switch (sel) {
         case 0:
-            tcg_gen_helper_0_0(do_mtc0_compare);
+            tcg_gen_helper_0_1(do_mtc0_compare, cpu_T[0]);
             rn = "Compare";
             break;
         /* 6,7 are implementation dependent */
@@ -3564,7 +3627,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
     case 12:
         switch (sel) {
         case 0:
-            tcg_gen_helper_0_0(do_mtc0_status);
+            tcg_gen_helper_0_1(do_mtc0_status, cpu_T[0]);
             /* BS_STOP isn't good enough here, hflags may have changed. */
             gen_save_pc(ctx->pc + 4);
             ctx->bstate = BS_EXCP;
@@ -3572,14 +3635,14 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
             break;
         case 1:
             check_insn(env, ctx, ISA_MIPS32R2);
-            tcg_gen_helper_0_0(do_mtc0_intctl);
+            tcg_gen_helper_0_1(do_mtc0_intctl, cpu_T[0]);
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
             rn = "IntCtl";
             break;
         case 2:
             check_insn(env, ctx, ISA_MIPS32R2);
-            tcg_gen_helper_0_0(do_mtc0_srsctl);
+            tcg_gen_helper_0_1(do_mtc0_srsctl, cpu_T[0]);
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
             rn = "SRSCtl";
@@ -3598,7 +3661,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
     case 13:
         switch (sel) {
         case 0:
-            tcg_gen_helper_0_0(do_mtc0_cause);
+            tcg_gen_helper_0_1(do_mtc0_cause, cpu_T[0]);
             rn = "Cause";
             break;
         default:
@@ -3625,7 +3688,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
             break;
         case 1:
             check_insn(env, ctx, ISA_MIPS32R2);
-            tcg_gen_helper_0_0(do_mtc0_ebase);
+            tcg_gen_helper_0_1(do_mtc0_ebase, cpu_T[0]);
             rn = "EBase";
             break;
         default:
@@ -3635,7 +3698,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
     case 16:
         switch (sel) {
         case 0:
-            tcg_gen_helper_0_0(do_mtc0_config0);
+            tcg_gen_helper_0_1(do_mtc0_config0, cpu_T[0]);
             rn = "Config";
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
@@ -3645,7 +3708,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
             rn = "Config1";
             break;
         case 2:
-            tcg_gen_helper_0_0(do_mtc0_config2);
+            tcg_gen_helper_0_1(do_mtc0_config2, cpu_T[0]);
             rn = "Config2";
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
@@ -3682,7 +3745,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
     case 18:
         switch (sel) {
         case 0 ... 7:
-            tcg_gen_helper_0_1i(do_mtc0_watchlo, sel);
+            tcg_gen_helper_0_1i(do_mtc0_watchlo, cpu_T[0], sel);
             rn = "WatchLo";
             break;
         default:
@@ -3692,7 +3755,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
     case 19:
         switch (sel) {
         case 0 ... 7:
-            tcg_gen_helper_0_1i(do_mtc0_watchhi, sel);
+            tcg_gen_helper_0_1i(do_mtc0_watchhi, cpu_T[0], sel);
             rn = "WatchHi";
             break;
         default:
@@ -3704,7 +3767,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
         case 0:
 #if defined(TARGET_MIPS64)
             check_insn(env, ctx, ISA_MIPS3);
-            tcg_gen_helper_0_0(do_mtc0_xcontext);
+            tcg_gen_helper_0_1(do_mtc0_xcontext, cpu_T[0]);
             rn = "XContext";
             break;
 #endif
@@ -3716,7 +3779,7 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
        /* Officially reserved, but sel 0 is used for R1x000 framemask */
         switch (sel) {
         case 0:
-            tcg_gen_helper_0_0(do_mtc0_framemask);
+            tcg_gen_helper_0_1(do_mtc0_framemask, cpu_T[0]);
             rn = "Framemask";
             break;
         default:
@@ -3730,20 +3793,20 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
     case 23:
         switch (sel) {
         case 0:
-            tcg_gen_helper_0_0(do_mtc0_debug); /* EJTAG support */
+            tcg_gen_helper_0_1(do_mtc0_debug, cpu_T[0]); /* EJTAG support */
             /* BS_STOP isn't good enough here, hflags may have changed. */
             gen_save_pc(ctx->pc + 4);
             ctx->bstate = BS_EXCP;
             rn = "Debug";
             break;
         case 1:
-//            tcg_gen_helper_0_0(do_mtc0_tracecontrol); /* PDtrace support */
+//            tcg_gen_helper_0_1(do_mtc0_tracecontrol, cpu_T[0]); /* PDtrace support */
             rn = "TraceControl";
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
 //            break;
         case 2:
-//            tcg_gen_helper_0_0(do_mtc0_tracecontrol2); /* PDtrace support */
+//            tcg_gen_helper_0_1(do_mtc0_tracecontrol2, cpu_T[0]); /* PDtrace support */
             rn = "TraceControl2";
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
@@ -3751,13 +3814,13 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
         case 3:
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
-//            tcg_gen_helper_0_0(do_mtc0_usertracedata); /* PDtrace support */
+//            tcg_gen_helper_0_1(do_mtc0_usertracedata, cpu_T[0]); /* PDtrace support */
             rn = "UserTraceData";
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
 //            break;
         case 4:
-//            tcg_gen_helper_0_0(do_mtc0_debug); /* PDtrace support */
+//            tcg_gen_helper_0_1(do_mtc0_tracebpc, cpu_T[0]); /* PDtrace support */
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
             rn = "TraceBPC";
@@ -3780,35 +3843,35 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
     case 25:
         switch (sel) {
         case 0:
-            tcg_gen_helper_0_0(do_mtc0_performance0);
+            tcg_gen_helper_0_1(do_mtc0_performance0, cpu_T[0]);
             rn = "Performance0";
             break;
         case 1:
-//            tcg_gen_helper_0_0(do_mtc0_performance1);
+//            tcg_gen_helper_0_1(do_mtc0_performance1, cpu_T[0]);
             rn = "Performance1";
 //            break;
         case 2:
-//            tcg_gen_helper_0_0(do_mtc0_performance2);
+//            tcg_gen_helper_0_1(do_mtc0_performance2, cpu_T[0]);
             rn = "Performance2";
 //            break;
         case 3:
-//            tcg_gen_helper_0_0(do_mtc0_performance3);
+//            tcg_gen_helper_0_1(do_mtc0_performance3, cpu_T[0]);
             rn = "Performance3";
 //            break;
         case 4:
-//            tcg_gen_helper_0_0(do_mtc0_performance4);
+//            tcg_gen_helper_0_1(do_mtc0_performance4, cpu_T[0]);
             rn = "Performance4";
 //            break;
         case 5:
-//            tcg_gen_helper_0_0(do_mtc0_performance5);
+//            tcg_gen_helper_0_1(do_mtc0_performance5, cpu_T[0]);
             rn = "Performance5";
 //            break;
         case 6:
-//            tcg_gen_helper_0_0(do_mtc0_performance6);
+//            tcg_gen_helper_0_1(do_mtc0_performance6, cpu_T[0]);
             rn = "Performance6";
 //            break;
         case 7:
-//            tcg_gen_helper_0_0(do_mtc0_performance7);
+//            tcg_gen_helper_0_1(do_mtc0_performance7, cpu_T[0]);
             rn = "Performance7";
 //            break;
         default:
@@ -3835,14 +3898,14 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
         case 2:
         case 4:
         case 6:
-            tcg_gen_helper_0_0(do_mtc0_taglo);
+            tcg_gen_helper_0_1(do_mtc0_taglo, cpu_T[0]);
             rn = "TagLo";
             break;
         case 1:
         case 3:
         case 5:
         case 7:
-            tcg_gen_helper_0_0(do_mtc0_datalo);
+            tcg_gen_helper_0_1(do_mtc0_datalo, cpu_T[0]);
             rn = "DataLo";
             break;
         default:
@@ -3855,14 +3918,14 @@ static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
         case 2:
         case 4:
         case 6:
-            tcg_gen_helper_0_0(do_mtc0_taghi);
+            tcg_gen_helper_0_1(do_mtc0_taghi, cpu_T[0]);
             rn = "TagHi";
             break;
         case 1:
         case 3:
         case 5:
         case 7:
-            tcg_gen_helper_0_0(do_mtc0_datahi);
+            tcg_gen_helper_0_1(do_mtc0_datahi, cpu_T[0]);
             rn = "DataHi";
             break;
         default:
@@ -3931,17 +3994,17 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
             break;
         case 1:
             check_insn(env, ctx, ASE_MT);
-            tcg_gen_helper_0_0(do_mfc0_mvpcontrol);
+            tcg_gen_helper_1_1(do_mfc0_mvpcontrol, cpu_T[0], cpu_T[0]);
             rn = "MVPControl";
             break;
         case 2:
             check_insn(env, ctx, ASE_MT);
-            tcg_gen_helper_0_0(do_mfc0_mvpconf0);
+            tcg_gen_helper_1_1(do_mfc0_mvpconf0, cpu_T[0], cpu_T[0]);
             rn = "MVPConf0";
             break;
         case 3:
             check_insn(env, ctx, ASE_MT);
-            tcg_gen_helper_0_0(do_mfc0_mvpconf1);
+            tcg_gen_helper_1_1(do_mfc0_mvpconf1, cpu_T[0], cpu_T[0]);
             rn = "MVPConf1";
             break;
         default:
@@ -3951,7 +4014,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
     case 1:
         switch (sel) {
         case 0:
-            tcg_gen_helper_0_0(do_mfc0_random);
+            tcg_gen_helper_1_1(do_mfc0_random, cpu_T[0], cpu_T[0]);
             rn = "Random";
             break;
         case 1:
@@ -4001,37 +4064,37 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
             break;
         case 1:
             check_insn(env, ctx, ASE_MT);
-            tcg_gen_helper_0_0(do_mfc0_tcstatus);
+            tcg_gen_helper_1_1(do_mfc0_tcstatus, cpu_T[0], cpu_T[0]);
             rn = "TCStatus";
             break;
         case 2:
             check_insn(env, ctx, ASE_MT);
-            tcg_gen_helper_0_0(do_mfc0_tcbind);
+            tcg_gen_helper_1_1(do_mfc0_tcbind, cpu_T[0], cpu_T[0]);
             rn = "TCBind";
             break;
         case 3:
             check_insn(env, ctx, ASE_MT);
-            tcg_gen_helper_0_0(do_dmfc0_tcrestart);
+            tcg_gen_helper_1_1(do_dmfc0_tcrestart, cpu_T[0], cpu_T[0]);
             rn = "TCRestart";
             break;
         case 4:
             check_insn(env, ctx, ASE_MT);
-            tcg_gen_helper_0_0(do_dmfc0_tchalt);
+            tcg_gen_helper_1_1(do_dmfc0_tchalt, cpu_T[0], cpu_T[0]);
             rn = "TCHalt";
             break;
         case 5:
             check_insn(env, ctx, ASE_MT);
-            tcg_gen_helper_0_0(do_dmfc0_tccontext);
+            tcg_gen_helper_1_1(do_dmfc0_tccontext, cpu_T[0], cpu_T[0]);
             rn = "TCContext";
             break;
         case 6:
             check_insn(env, ctx, ASE_MT);
-            tcg_gen_helper_0_0(do_dmfc0_tcschedule);
+            tcg_gen_helper_1_1(do_dmfc0_tcschedule, cpu_T[0], cpu_T[0]);
             rn = "TCSchedule";
             break;
         case 7:
             check_insn(env, ctx, ASE_MT);
-            tcg_gen_helper_0_0(do_dmfc0_tcschefback);
+            tcg_gen_helper_1_1(do_dmfc0_tcschefback, cpu_T[0], cpu_T[0]);
             rn = "TCScheFBack";
             break;
         default:
@@ -4055,7 +4118,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
             rn = "Context";
             break;
         case 1:
-//            tcg_gen_helper_0_0(do_dmfc0_contextconfig); /* SmartMIPS ASE */
+//            tcg_gen_helper_1_1(do_dmfc0_contextconfig, cpu_T[0], cpu_T[0]); /* SmartMIPS ASE */
             rn = "ContextConfig";
 //            break;
         default:
@@ -4136,7 +4199,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
     case 9:
         switch (sel) {
         case 0:
-            tcg_gen_helper_0_0(do_mfc0_count);
+            tcg_gen_helper_1_1(do_mfc0_count, cpu_T[0], cpu_T[0]);
             rn = "Count";
             break;
         /* 6,7 are implementation dependent */
@@ -4259,7 +4322,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
     case 17:
         switch (sel) {
         case 0:
-            tcg_gen_helper_0_0(do_dmfc0_lladdr);
+            tcg_gen_helper_1_1(do_dmfc0_lladdr, cpu_T[0], cpu_T[0]);
             rn = "LLAddr";
             break;
         default:
@@ -4269,7 +4332,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
     case 18:
         switch (sel) {
         case 0 ... 7:
-            tcg_gen_helper_0_1i(do_dmfc0_watchlo, sel);
+            tcg_gen_helper_1_1i(do_dmfc0_watchlo, cpu_T[0], cpu_T[0], sel);
             rn = "WatchLo";
             break;
         default:
@@ -4279,7 +4342,7 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
     case 19:
         switch (sel) {
         case 0 ... 7:
-            tcg_gen_helper_0_1i(do_mfc0_watchhi, sel);
+            tcg_gen_helper_1_1i(do_mfc0_watchhi, cpu_T[0], cpu_T[0], sel);
             rn = "WatchHi";
             break;
         default:
@@ -4315,23 +4378,23 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
     case 23:
         switch (sel) {
         case 0:
-            tcg_gen_helper_0_0(do_mfc0_debug); /* EJTAG support */
+            tcg_gen_helper_1_1(do_mfc0_debug, cpu_T[0], cpu_T[0]); /* EJTAG support */
             rn = "Debug";
             break;
         case 1:
-//            tcg_gen_helper_0_0(do_dmfc0_tracecontrol); /* PDtrace support */
+//            tcg_gen_helper_1_1(do_dmfc0_tracecontrol, cpu_T[0], cpu_T[0]); /* PDtrace support */
             rn = "TraceControl";
 //            break;
         case 2:
-//            tcg_gen_helper_0_0(do_dmfc0_tracecontrol2); /* PDtrace support */
+//            tcg_gen_helper_1_1(do_dmfc0_tracecontrol2, cpu_T[0], cpu_T[0]); /* PDtrace support */
             rn = "TraceControl2";
 //            break;
         case 3:
-//            tcg_gen_helper_0_0(do_dmfc0_usertracedata); /* PDtrace support */
+//            tcg_gen_helper_1_1(do_dmfc0_usertracedata, cpu_T[0], cpu_T[0]); /* PDtrace support */
             rn = "UserTraceData";
 //            break;
         case 4:
-//            tcg_gen_helper_0_0(do_dmfc0_debug); /* PDtrace support */
+//            tcg_gen_helper_1_1(do_dmfc0_tracebpc, cpu_T[0], cpu_T[0]); /* PDtrace support */
             rn = "TraceBPC";
 //            break;
         default:
@@ -4356,31 +4419,31 @@ static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
             rn = "Performance0";
             break;
         case 1:
-//            tcg_gen_helper_0_0(do_dmfc0_performance1);
+//            tcg_gen_helper_1_1(do_dmfc0_performance1, cpu_T[0], cpu_T[0]);
             rn = "Performance1";
 //            break;
         case 2:
-//            tcg_gen_helper_0_0(do_dmfc0_performance2);
+//            tcg_gen_helper_1_1(do_dmfc0_performance2, cpu_T[0], cpu_T[0]);
             rn = "Performance2";
 //            break;
         case 3:
-//            tcg_gen_helper_0_0(do_dmfc0_performance3);
+//            tcg_gen_helper_1_1(do_dmfc0_performance3, cpu_T[0], cpu_T[0]);
             rn = "Performance3";
 //            break;
         case 4:
-//            tcg_gen_helper_0_0(do_dmfc0_performance4);
+//            tcg_gen_helper_1_1(do_dmfc0_performance4, cpu_T[0], cpu_T[0]);
             rn = "Performance4";
 //            break;
         case 5:
-//            tcg_gen_helper_0_0(do_dmfc0_performance5);
+//            tcg_gen_helper_1_1(do_dmfc0_performance5, cpu_T[0], cpu_T[0]);
             rn = "Performance5";
 //            break;
         case 6:
-//            tcg_gen_helper_0_0(do_dmfc0_performance6);
+//            tcg_gen_helper_1_1(do_dmfc0_performance6, cpu_T[0], cpu_T[0]);
             rn = "Performance6";
 //            break;
         case 7:
-//            tcg_gen_helper_0_0(do_dmfc0_performance7);
+//            tcg_gen_helper_1_1(do_dmfc0_performance7, cpu_T[0], cpu_T[0]);
             rn = "Performance7";
 //            break;
         default:
@@ -4493,12 +4556,12 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
     case 0:
         switch (sel) {
         case 0:
-            tcg_gen_helper_0_0(do_mtc0_index);
+            tcg_gen_helper_0_1(do_mtc0_index, cpu_T[0]);
             rn = "Index";
             break;
         case 1:
             check_insn(env, ctx, ASE_MT);
-            tcg_gen_helper_0_0(do_mtc0_mvpcontrol);
+            tcg_gen_helper_0_1(do_mtc0_mvpcontrol, cpu_T[0]);
             rn = "MVPControl";
             break;
         case 2:
@@ -4523,22 +4586,22 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
             break;
         case 1:
             check_insn(env, ctx, ASE_MT);
-            tcg_gen_helper_0_0(do_mtc0_vpecontrol);
+            tcg_gen_helper_0_1(do_mtc0_vpecontrol, cpu_T[0]);
             rn = "VPEControl";
             break;
         case 2:
             check_insn(env, ctx, ASE_MT);
-            tcg_gen_helper_0_0(do_mtc0_vpeconf0);
+            tcg_gen_helper_0_1(do_mtc0_vpeconf0, cpu_T[0]);
             rn = "VPEConf0";
             break;
         case 3:
             check_insn(env, ctx, ASE_MT);
-            tcg_gen_helper_0_0(do_mtc0_vpeconf1);
+            tcg_gen_helper_0_1(do_mtc0_vpeconf1, cpu_T[0]);
             rn = "VPEConf1";
             break;
         case 4:
             check_insn(env, ctx, ASE_MT);
-            tcg_gen_helper_0_0(do_mtc0_yqmask);
+            tcg_gen_helper_0_1(do_mtc0_yqmask, cpu_T[0]);
             rn = "YQMask";
             break;
         case 5:
@@ -4553,7 +4616,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
             break;
         case 7:
             check_insn(env, ctx, ASE_MT);
-            tcg_gen_helper_0_0(do_mtc0_vpeopt);
+            tcg_gen_helper_0_1(do_mtc0_vpeopt, cpu_T[0]);
             rn = "VPEOpt";
             break;
         default:
@@ -4563,42 +4626,42 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
     case 2:
         switch (sel) {
         case 0:
-            tcg_gen_helper_0_0(do_mtc0_entrylo0);
+            tcg_gen_helper_0_1(do_mtc0_entrylo0, cpu_T[0]);
             rn = "EntryLo0";
             break;
         case 1:
             check_insn(env, ctx, ASE_MT);
-            tcg_gen_helper_0_0(do_mtc0_tcstatus);
+            tcg_gen_helper_0_1(do_mtc0_tcstatus, cpu_T[0]);
             rn = "TCStatus";
             break;
         case 2:
             check_insn(env, ctx, ASE_MT);
-            tcg_gen_helper_0_0(do_mtc0_tcbind);
+            tcg_gen_helper_0_1(do_mtc0_tcbind, cpu_T[0]);
             rn = "TCBind";
             break;
         case 3:
             check_insn(env, ctx, ASE_MT);
-            tcg_gen_helper_0_0(do_mtc0_tcrestart);
+            tcg_gen_helper_0_1(do_mtc0_tcrestart, cpu_T[0]);
             rn = "TCRestart";
             break;
         case 4:
             check_insn(env, ctx, ASE_MT);
-            tcg_gen_helper_0_0(do_mtc0_tchalt);
+            tcg_gen_helper_0_1(do_mtc0_tchalt, cpu_T[0]);
             rn = "TCHalt";
             break;
         case 5:
             check_insn(env, ctx, ASE_MT);
-            tcg_gen_helper_0_0(do_mtc0_tccontext);
+            tcg_gen_helper_0_1(do_mtc0_tccontext, cpu_T[0]);
             rn = "TCContext";
             break;
         case 6:
             check_insn(env, ctx, ASE_MT);
-            tcg_gen_helper_0_0(do_mtc0_tcschedule);
+            tcg_gen_helper_0_1(do_mtc0_tcschedule, cpu_T[0]);
             rn = "TCSchedule";
             break;
         case 7:
             check_insn(env, ctx, ASE_MT);
-            tcg_gen_helper_0_0(do_mtc0_tcschefback);
+            tcg_gen_helper_0_1(do_mtc0_tcschefback, cpu_T[0]);
             rn = "TCScheFBack";
             break;
         default:
@@ -4608,7 +4671,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
     case 3:
         switch (sel) {
         case 0:
-            tcg_gen_helper_0_0(do_mtc0_entrylo1);
+            tcg_gen_helper_0_1(do_mtc0_entrylo1, cpu_T[0]);
             rn = "EntryLo1";
             break;
         default:
@@ -4618,11 +4681,11 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
     case 4:
         switch (sel) {
         case 0:
-            tcg_gen_helper_0_0(do_mtc0_context);
+            tcg_gen_helper_0_1(do_mtc0_context, cpu_T[0]);
             rn = "Context";
             break;
         case 1:
-//           tcg_gen_helper_0_0(do_mtc0_contextconfig); /* SmartMIPS ASE */
+//           tcg_gen_helper_0_1(do_mtc0_contextconfig, cpu_T[0]); /* SmartMIPS ASE */
             rn = "ContextConfig";
 //           break;
         default:
@@ -4632,12 +4695,12 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
     case 5:
         switch (sel) {
         case 0:
-            tcg_gen_helper_0_0(do_mtc0_pagemask);
+            tcg_gen_helper_0_1(do_mtc0_pagemask, cpu_T[0]);
             rn = "PageMask";
             break;
         case 1:
             check_insn(env, ctx, ISA_MIPS32R2);
-            tcg_gen_helper_0_0(do_mtc0_pagegrain);
+            tcg_gen_helper_0_1(do_mtc0_pagegrain, cpu_T[0]);
             rn = "PageGrain";
             break;
         default:
@@ -4647,32 +4710,32 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
     case 6:
         switch (sel) {
         case 0:
-            tcg_gen_helper_0_0(do_mtc0_wired);
+            tcg_gen_helper_0_1(do_mtc0_wired, cpu_T[0]);
             rn = "Wired";
             break;
         case 1:
             check_insn(env, ctx, ISA_MIPS32R2);
-            tcg_gen_helper_0_0(do_mtc0_srsconf0);
+            tcg_gen_helper_0_1(do_mtc0_srsconf0, cpu_T[0]);
             rn = "SRSConf0";
             break;
         case 2:
             check_insn(env, ctx, ISA_MIPS32R2);
-            tcg_gen_helper_0_0(do_mtc0_srsconf1);
+            tcg_gen_helper_0_1(do_mtc0_srsconf1, cpu_T[0]);
             rn = "SRSConf1";
             break;
         case 3:
             check_insn(env, ctx, ISA_MIPS32R2);
-            tcg_gen_helper_0_0(do_mtc0_srsconf2);
+            tcg_gen_helper_0_1(do_mtc0_srsconf2, cpu_T[0]);
             rn = "SRSConf2";
             break;
         case 4:
             check_insn(env, ctx, ISA_MIPS32R2);
-            tcg_gen_helper_0_0(do_mtc0_srsconf3);
+            tcg_gen_helper_0_1(do_mtc0_srsconf3, cpu_T[0]);
             rn = "SRSConf3";
             break;
         case 5:
             check_insn(env, ctx, ISA_MIPS32R2);
-            tcg_gen_helper_0_0(do_mtc0_srsconf4);
+            tcg_gen_helper_0_1(do_mtc0_srsconf4, cpu_T[0]);
             rn = "SRSConf4";
             break;
         default:
@@ -4683,7 +4746,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
         switch (sel) {
         case 0:
             check_insn(env, ctx, ISA_MIPS32R2);
-            tcg_gen_helper_0_0(do_mtc0_hwrena);
+            tcg_gen_helper_0_1(do_mtc0_hwrena, cpu_T[0]);
             rn = "HWREna";
             break;
         default:
@@ -4697,7 +4760,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
     case 9:
         switch (sel) {
         case 0:
-            tcg_gen_helper_0_0(do_mtc0_count);
+            tcg_gen_helper_0_1(do_mtc0_count, cpu_T[0]);
             rn = "Count";
             break;
         /* 6,7 are implementation dependent */
@@ -4710,7 +4773,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
     case 10:
         switch (sel) {
         case 0:
-            tcg_gen_helper_0_0(do_mtc0_entryhi);
+            tcg_gen_helper_0_1(do_mtc0_entryhi, cpu_T[0]);
             rn = "EntryHi";
             break;
         default:
@@ -4720,7 +4783,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
     case 11:
         switch (sel) {
         case 0:
-            tcg_gen_helper_0_0(do_mtc0_compare);
+            tcg_gen_helper_0_1(do_mtc0_compare, cpu_T[0]);
             rn = "Compare";
             break;
         /* 6,7 are implementation dependent */
@@ -4733,7 +4796,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
     case 12:
         switch (sel) {
         case 0:
-            tcg_gen_helper_0_0(do_mtc0_status);
+            tcg_gen_helper_0_1(do_mtc0_status, cpu_T[0]);
             /* BS_STOP isn't good enough here, hflags may have changed. */
             gen_save_pc(ctx->pc + 4);
             ctx->bstate = BS_EXCP;
@@ -4741,14 +4804,14 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
             break;
         case 1:
             check_insn(env, ctx, ISA_MIPS32R2);
-            tcg_gen_helper_0_0(do_mtc0_intctl);
+            tcg_gen_helper_0_1(do_mtc0_intctl, cpu_T[0]);
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
             rn = "IntCtl";
             break;
         case 2:
             check_insn(env, ctx, ISA_MIPS32R2);
-            tcg_gen_helper_0_0(do_mtc0_srsctl);
+            tcg_gen_helper_0_1(do_mtc0_srsctl, cpu_T[0]);
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
             rn = "SRSCtl";
@@ -4767,7 +4830,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
     case 13:
         switch (sel) {
         case 0:
-            tcg_gen_helper_0_0(do_mtc0_cause);
+            tcg_gen_helper_0_1(do_mtc0_cause, cpu_T[0]);
             rn = "Cause";
             break;
         default:
@@ -4794,7 +4857,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
             break;
         case 1:
             check_insn(env, ctx, ISA_MIPS32R2);
-            tcg_gen_helper_0_0(do_mtc0_ebase);
+            tcg_gen_helper_0_1(do_mtc0_ebase, cpu_T[0]);
             rn = "EBase";
             break;
         default:
@@ -4804,7 +4867,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
     case 16:
         switch (sel) {
         case 0:
-            tcg_gen_helper_0_0(do_mtc0_config0);
+            tcg_gen_helper_0_1(do_mtc0_config0, cpu_T[0]);
             rn = "Config";
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
@@ -4814,7 +4877,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
             rn = "Config1";
             break;
         case 2:
-            tcg_gen_helper_0_0(do_mtc0_config2);
+            tcg_gen_helper_0_1(do_mtc0_config2, cpu_T[0]);
             rn = "Config2";
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
@@ -4842,7 +4905,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
     case 18:
         switch (sel) {
         case 0 ... 7:
-            tcg_gen_helper_0_1i(do_mtc0_watchlo, sel);
+            tcg_gen_helper_0_1i(do_mtc0_watchlo, cpu_T[0], sel);
             rn = "WatchLo";
             break;
         default:
@@ -4852,7 +4915,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
     case 19:
         switch (sel) {
         case 0 ... 7:
-            tcg_gen_helper_0_1i(do_mtc0_watchhi, sel);
+            tcg_gen_helper_0_1i(do_mtc0_watchhi, cpu_T[0], sel);
             rn = "WatchHi";
             break;
         default:
@@ -4863,7 +4926,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
         switch (sel) {
         case 0:
             check_insn(env, ctx, ISA_MIPS3);
-            tcg_gen_helper_0_0(do_mtc0_xcontext);
+            tcg_gen_helper_0_1(do_mtc0_xcontext, cpu_T[0]);
             rn = "XContext";
             break;
         default:
@@ -4874,7 +4937,7 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
        /* Officially reserved, but sel 0 is used for R1x000 framemask */
         switch (sel) {
         case 0:
-            tcg_gen_helper_0_0(do_mtc0_framemask);
+            tcg_gen_helper_0_1(do_mtc0_framemask, cpu_T[0]);
             rn = "Framemask";
             break;
         default:
@@ -4888,32 +4951,32 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
     case 23:
         switch (sel) {
         case 0:
-            tcg_gen_helper_0_0(do_mtc0_debug); /* EJTAG support */
+            tcg_gen_helper_0_1(do_mtc0_debug, cpu_T[0]); /* EJTAG support */
             /* BS_STOP isn't good enough here, hflags may have changed. */
             gen_save_pc(ctx->pc + 4);
             ctx->bstate = BS_EXCP;
             rn = "Debug";
             break;
         case 1:
-//            tcg_gen_helper_0_0(do_mtc0_tracecontrol); /* PDtrace support */
+//            tcg_gen_helper_0_1(do_mtc0_tracecontrol, cpu_T[0]); /* PDtrace support */
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
             rn = "TraceControl";
 //            break;
         case 2:
-//            tcg_gen_helper_0_0(do_mtc0_tracecontrol2); /* PDtrace support */
+//            tcg_gen_helper_0_1(do_mtc0_tracecontrol2, cpu_T[0]); /* PDtrace support */
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
             rn = "TraceControl2";
 //            break;
         case 3:
-//            tcg_gen_helper_0_0(do_mtc0_usertracedata); /* PDtrace support */
+//            tcg_gen_helper_0_1(do_mtc0_usertracedata, cpu_T[0]); /* PDtrace support */
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
             rn = "UserTraceData";
 //            break;
         case 4:
-//            tcg_gen_helper_0_0(do_mtc0_debug); /* PDtrace support */
+//            tcg_gen_helper_0_1(do_mtc0_tracebpc, cpu_T[0]); /* PDtrace support */
             /* Stop translation as we may have switched the execution mode */
             ctx->bstate = BS_STOP;
             rn = "TraceBPC";
@@ -4936,35 +4999,35 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
     case 25:
         switch (sel) {
         case 0:
-            tcg_gen_helper_0_0(do_mtc0_performance0);
+            tcg_gen_helper_0_1(do_mtc0_performance0, cpu_T[0]);
             rn = "Performance0";
             break;
         case 1:
-//            tcg_gen_helper_0_0(do_mtc0_performance1);
+//            tcg_gen_helper_0_1(do_mtc0_performance1, cpu_T[0]);
             rn = "Performance1";
 //            break;
         case 2:
-//            tcg_gen_helper_0_0(do_mtc0_performance2);
+//            tcg_gen_helper_0_1(do_mtc0_performance2, cpu_T[0]);
             rn = "Performance2";
 //            break;
         case 3:
-//            tcg_gen_helper_0_0(do_mtc0_performance3);
+//            tcg_gen_helper_0_1(do_mtc0_performance3, cpu_T[0]);
             rn = "Performance3";
 //            break;
         case 4:
-//            tcg_gen_helper_0_0(do_mtc0_performance4);
+//            tcg_gen_helper_0_1(do_mtc0_performance4, cpu_T[0]);
             rn = "Performance4";
 //            break;
         case 5:
-//            tcg_gen_helper_0_0(do_mtc0_performance5);
+//            tcg_gen_helper_0_1(do_mtc0_performance5, cpu_T[0]);
             rn = "Performance5";
 //            break;
         case 6:
-//            tcg_gen_helper_0_0(do_mtc0_performance6);
+//            tcg_gen_helper_0_1(do_mtc0_performance6, cpu_T[0]);
             rn = "Performance6";
 //            break;
         case 7:
-//            tcg_gen_helper_0_0(do_mtc0_performance7);
+//            tcg_gen_helper_0_1(do_mtc0_performance7, cpu_T[0]);
             rn = "Performance7";
 //            break;
         default:
@@ -4991,14 +5054,14 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
         case 2:
         case 4:
         case 6:
-            tcg_gen_helper_0_0(do_mtc0_taglo);
+            tcg_gen_helper_0_1(do_mtc0_taglo, cpu_T[0]);
             rn = "TagLo";
             break;
         case 1:
         case 3:
         case 5:
         case 7:
-            tcg_gen_helper_0_0(do_mtc0_datalo);
+            tcg_gen_helper_0_1(do_mtc0_datalo, cpu_T[0]);
             rn = "DataLo";
             break;
         default:
@@ -5011,14 +5074,14 @@ static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel)
         case 2:
         case 4:
         case 6:
-            tcg_gen_helper_0_0(do_mtc0_taghi);
+            tcg_gen_helper_0_1(do_mtc0_taghi, cpu_T[0]);
             rn = "TagHi";
             break;
         case 1:
         case 3:
         case 5:
         case 7:
-            tcg_gen_helper_0_0(do_mtc0_datahi);
+            tcg_gen_helper_0_1(do_mtc0_datahi, cpu_T[0]);
             rn = "DataHi";
             break;
         default:
@@ -5088,25 +5151,25 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt,
         case 2:
             switch (sel) {
             case 1:
-                tcg_gen_helper_0_0(do_mftc0_tcstatus);
+                tcg_gen_helper_1_1(do_mftc0_tcstatus, cpu_T[0], cpu_T[0]);
                 break;
             case 2:
-                tcg_gen_helper_0_0(do_mftc0_tcbind);
+                tcg_gen_helper_1_1(do_mftc0_tcbind, cpu_T[0], cpu_T[0]);
                 break;
             case 3:
-                tcg_gen_helper_0_0(do_mftc0_tcrestart);
+                tcg_gen_helper_1_1(do_mftc0_tcrestart, cpu_T[0], cpu_T[0]);
                 break;
             case 4:
-                tcg_gen_helper_0_0(do_mftc0_tchalt);
+                tcg_gen_helper_1_1(do_mftc0_tchalt, cpu_T[0], cpu_T[0]);
                 break;
             case 5:
-                tcg_gen_helper_0_0(do_mftc0_tccontext);
+                tcg_gen_helper_1_1(do_mftc0_tccontext, cpu_T[0], cpu_T[0]);
                 break;
             case 6:
-                tcg_gen_helper_0_0(do_mftc0_tcschedule);
+                tcg_gen_helper_1_1(do_mftc0_tcschedule, cpu_T[0], cpu_T[0]);
                 break;
             case 7:
-                tcg_gen_helper_0_0(do_mftc0_tcschefback);
+                tcg_gen_helper_1_1(do_mftc0_tcschefback, cpu_T[0], cpu_T[0]);
                 break;
             default:
                 gen_mfc0(env, ctx, rt, sel);
@@ -5116,7 +5179,7 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt,
         case 10:
             switch (sel) {
             case 0:
-                tcg_gen_helper_0_0(do_mftc0_entryhi);
+                tcg_gen_helper_1_1(do_mftc0_entryhi, cpu_T[0], cpu_T[0]);
                 break;
             default:
                 gen_mfc0(env, ctx, rt, sel);
@@ -5125,7 +5188,7 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt,
         case 12:
             switch (sel) {
             case 0:
-                tcg_gen_helper_0_0(do_mftc0_status);
+                tcg_gen_helper_1_1(do_mftc0_status, cpu_T[0], cpu_T[0]);
                 break;
             default:
                 gen_mfc0(env, ctx, rt, sel);
@@ -5134,7 +5197,7 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt,
         case 23:
             switch (sel) {
             case 0:
-                tcg_gen_helper_0_0(do_mftc0_debug);
+                tcg_gen_helper_1_1(do_mftc0_debug, cpu_T[0], cpu_T[0]);
                 break;
             default:
                 gen_mfc0(env, ctx, rt, sel);
@@ -5147,49 +5210,49 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt,
     } else switch (sel) {
     /* GPR registers. */
     case 0:
-        tcg_gen_helper_0_1i(do_mftgpr, rt);
+        tcg_gen_helper_1_1i(do_mftgpr, cpu_T[0], cpu_T[0], rt);
         break;
     /* Auxiliary CPU registers */
     case 1:
         switch (rt) {
         case 0:
-            tcg_gen_helper_0_1i(do_mftlo, 0);
+            tcg_gen_helper_1_1i(do_mftlo, cpu_T[0], cpu_T[0], 0);
             break;
         case 1:
-            tcg_gen_helper_0_1i(do_mfthi, 0);
+            tcg_gen_helper_1_1i(do_mfthi, cpu_T[0], cpu_T[0], 0);
             break;
         case 2:
-            tcg_gen_helper_0_1i(do_mftacx, 0);
+            tcg_gen_helper_1_1i(do_mftacx, cpu_T[0], cpu_T[0], 0);
             break;
         case 4:
-            tcg_gen_helper_0_1i(do_mftlo, 1);
+            tcg_gen_helper_1_1i(do_mftlo, cpu_T[0], cpu_T[0], 1);
             break;
         case 5:
-            tcg_gen_helper_0_1i(do_mfthi, 1);
+            tcg_gen_helper_1_1i(do_mfthi, cpu_T[0], cpu_T[0], 1);
             break;
         case 6:
-            tcg_gen_helper_0_1i(do_mftacx, 1);
+            tcg_gen_helper_1_1i(do_mftacx, cpu_T[0], cpu_T[0], 1);
             break;
         case 8:
-            tcg_gen_helper_0_1i(do_mftlo, 2);
+            tcg_gen_helper_1_1i(do_mftlo, cpu_T[0], cpu_T[0], 2);
             break;
         case 9:
-            tcg_gen_helper_0_1i(do_mfthi, 2);
+            tcg_gen_helper_1_1i(do_mfthi, cpu_T[0], cpu_T[0], 2);
             break;
         case 10:
-            tcg_gen_helper_0_1i(do_mftacx, 2);
+            tcg_gen_helper_1_1i(do_mftacx, cpu_T[0], cpu_T[0], 2);
             break;
         case 12:
-            tcg_gen_helper_0_1i(do_mftlo, 3);
+            tcg_gen_helper_1_1i(do_mftlo, cpu_T[0], cpu_T[0], 3);
             break;
         case 13:
-            tcg_gen_helper_0_1i(do_mfthi, 3);
+            tcg_gen_helper_1_1i(do_mfthi, cpu_T[0], cpu_T[0], 3);
             break;
         case 14:
-            tcg_gen_helper_0_1i(do_mftacx, 3);
+            tcg_gen_helper_1_1i(do_mftacx, cpu_T[0], cpu_T[0], 3);
             break;
         case 16:
-            tcg_gen_helper_0_0(do_mftdsp);
+            tcg_gen_helper_1_1(do_mftdsp, cpu_T[0], cpu_T[0]);
             break;
         default:
             goto die;
@@ -5208,7 +5271,7 @@ static void gen_mftr(CPUState *env, DisasContext *ctx, int rt,
         break;
     case 3:
         /* XXX: For now we support only a single FPU context. */
-        tcg_gen_helper_0_1i(do_cfc1, rt);
+        tcg_gen_helper_1_1i(do_cfc1, cpu_T[0], cpu_T[0], rt);
         break;
     /* COP2: Not implemented. */
     case 4:
@@ -5252,25 +5315,25 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd,
         case 2:
             switch (sel) {
             case 1:
-                tcg_gen_helper_0_0(do_mttc0_tcstatus);
+                tcg_gen_helper_0_1(do_mttc0_tcstatus, cpu_T[0]);
                 break;
             case 2:
-                tcg_gen_helper_0_0(do_mttc0_tcbind);
+                tcg_gen_helper_0_1(do_mttc0_tcbind, cpu_T[0]);
                 break;
             case 3:
-                tcg_gen_helper_0_0(do_mttc0_tcrestart);
+                tcg_gen_helper_0_1(do_mttc0_tcrestart, cpu_T[0]);
                 break;
             case 4:
-                tcg_gen_helper_0_0(do_mttc0_tchalt);
+                tcg_gen_helper_0_1(do_mttc0_tchalt, cpu_T[0]);
                 break;
             case 5:
-                tcg_gen_helper_0_0(do_mttc0_tccontext);
+                tcg_gen_helper_0_1(do_mttc0_tccontext, cpu_T[0]);
                 break;
             case 6:
-                tcg_gen_helper_0_0(do_mttc0_tcschedule);
+                tcg_gen_helper_0_1(do_mttc0_tcschedule, cpu_T[0]);
                 break;
             case 7:
-                tcg_gen_helper_0_0(do_mttc0_tcschefback);
+                tcg_gen_helper_0_1(do_mttc0_tcschefback, cpu_T[0]);
                 break;
             default:
                 gen_mtc0(env, ctx, rd, sel);
@@ -5280,7 +5343,7 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd,
         case 10:
             switch (sel) {
             case 0:
-                tcg_gen_helper_0_0(do_mttc0_entryhi);
+                tcg_gen_helper_0_1(do_mttc0_entryhi, cpu_T[0]);
                 break;
             default:
                 gen_mtc0(env, ctx, rd, sel);
@@ -5289,7 +5352,7 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd,
         case 12:
             switch (sel) {
             case 0:
-                tcg_gen_helper_0_0(do_mttc0_status);
+                tcg_gen_helper_0_1(do_mttc0_status, cpu_T[0]);
                 break;
             default:
                 gen_mtc0(env, ctx, rd, sel);
@@ -5298,7 +5361,7 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd,
         case 23:
             switch (sel) {
             case 0:
-                tcg_gen_helper_0_0(do_mttc0_debug);
+                tcg_gen_helper_0_1(do_mttc0_debug, cpu_T[0]);
                 break;
             default:
                 gen_mtc0(env, ctx, rd, sel);
@@ -5311,49 +5374,49 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd,
     } else switch (sel) {
     /* GPR registers. */
     case 0:
-        tcg_gen_helper_0_1i(do_mttgpr, rd);
+        tcg_gen_helper_0_1i(do_mttgpr, cpu_T[0], rd);
         break;
     /* Auxiliary CPU registers */
     case 1:
         switch (rd) {
         case 0:
-            tcg_gen_helper_0_1i(do_mttlo, 0);
+            tcg_gen_helper_0_1i(do_mttlo, cpu_T[0], 0);
             break;
         case 1:
-            tcg_gen_helper_0_1i(do_mtthi, 0);
+            tcg_gen_helper_0_1i(do_mtthi, cpu_T[0], 0);
             break;
         case 2:
-            tcg_gen_helper_0_1i(do_mttacx, 0);
+            tcg_gen_helper_0_1i(do_mttacx, cpu_T[0], 0);
             break;
         case 4:
-            tcg_gen_helper_0_1i(do_mttlo, 1);
+            tcg_gen_helper_0_1i(do_mttlo, cpu_T[0], 1);
             break;
         case 5:
-            tcg_gen_helper_0_1i(do_mtthi, 1);
+            tcg_gen_helper_0_1i(do_mtthi, cpu_T[0], 1);
             break;
         case 6:
-            tcg_gen_helper_0_1i(do_mttacx, 1);
+            tcg_gen_helper_0_1i(do_mttacx, cpu_T[0], 1);
             break;
         case 8:
-            tcg_gen_helper_0_1i(do_mttlo, 2);
+            tcg_gen_helper_0_1i(do_mttlo, cpu_T[0], 2);
             break;
         case 9:
-            tcg_gen_helper_0_1i(do_mtthi, 2);
+            tcg_gen_helper_0_1i(do_mtthi, cpu_T[0], 2);
             break;
         case 10:
-            tcg_gen_helper_0_1i(do_mttacx, 2);
+            tcg_gen_helper_0_1i(do_mttacx, cpu_T[0], 2);
             break;
         case 12:
-            tcg_gen_helper_0_1i(do_mttlo, 3);
+            tcg_gen_helper_0_1i(do_mttlo, cpu_T[0], 3);
             break;
         case 13:
-            tcg_gen_helper_0_1i(do_mtthi, 3);
+            tcg_gen_helper_0_1i(do_mtthi, cpu_T[0], 3);
             break;
         case 14:
-            tcg_gen_helper_0_1i(do_mttacx, 3);
+            tcg_gen_helper_0_1i(do_mttacx, cpu_T[0], 3);
             break;
         case 16:
-            tcg_gen_helper_0_0(do_mttdsp);
+            tcg_gen_helper_0_1(do_mttdsp, cpu_T[0]);
             break;
         default:
             goto die;
@@ -5372,7 +5435,7 @@ static void gen_mttr(CPUState *env, DisasContext *ctx, int rd,
         break;
     case 3:
         /* XXX: For now we support only a single FPU context. */
-        tcg_gen_helper_0_1i(do_ctc1, rd);
+        tcg_gen_helper_0_1i(do_ctc1, cpu_T[0], rd);
         break;
     /* COP2: Not implemented. */
     case 4:
@@ -5484,7 +5547,7 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int
         opn = "eret";
         check_insn(env, ctx, ISA_MIPS2);
         save_cpu_state(ctx, 1);
-        tcg_gen_helper_0_0(do_eret);
+        tcg_gen_helper_0_1(do_eret, cpu_T[0]);
         ctx->bstate = BS_EXCP;
         break;
     case OPC_DERET:
@@ -5495,7 +5558,7 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int
             generate_exception(ctx, EXCP_RI);
         } else {
             save_cpu_state(ctx, 1);
-            tcg_gen_helper_0_0(do_deret);
+            tcg_gen_helper_0_1(do_deret, cpu_T[0]);
             ctx->bstate = BS_EXCP;
         }
         break;
@@ -5734,13 +5797,13 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs)
         opn = "mtc1";
         break;
     case OPC_CFC1:
-        tcg_gen_helper_0_1i(do_cfc1, fs);
+        tcg_gen_helper_1_1i(do_cfc1, cpu_T[0], cpu_T[0], fs);
         gen_store_gpr(cpu_T[0], rt);
         opn = "cfc1";
         break;
     case OPC_CTC1:
         gen_load_gpr(cpu_T[0], rt);
-        tcg_gen_helper_0_1i(do_ctc1, fs);
+        tcg_gen_helper_0_1i(do_ctc1, cpu_T[0], fs);
         opn = "ctc1";
         break;
     case OPC_DMFC1:
@@ -6745,7 +6808,7 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc,
     } else {
         gen_load_gpr(cpu_T[0], base);
         gen_load_gpr(cpu_T[1], index);
-        gen_op_addr_add();
+        gen_op_addr_add(cpu_T[0], cpu_T[1]);
     }
     /* Don't do NOP if destination is zero: we must perform the actual
        memory access. */
@@ -7069,7 +7132,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
             MIPS_INVAL("PMON / selsl");
             generate_exception(ctx, EXCP_RI);
 #else
-            tcg_gen_helper_0_1i(do_pmon, sa);
+            tcg_gen_helper_0_i(do_pmon, sa);
 #endif
             break;
         case OPC_SYSCALL:
@@ -7187,7 +7250,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
             switch (op2) {
             case OPC_WSBH:
                 gen_load_gpr(cpu_T[1], rt);
-                tcg_gen_helper_0_0(do_wsbh);
+                tcg_gen_helper_1_2(do_wsbh, cpu_T[0], cpu_T[0], cpu_T[1]);
                 break;
             case OPC_SEB:
                 gen_load_gpr(cpu_T[1], rt);
@@ -7209,19 +7272,19 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
             switch (rd) {
             case 0:
                 save_cpu_state(ctx, 1);
-                tcg_gen_helper_0_0(do_rdhwr_cpunum);
+                tcg_gen_helper_1_1(do_rdhwr_cpunum, cpu_T[0], cpu_T[0]);
                 break;
             case 1:
                 save_cpu_state(ctx, 1);
-                tcg_gen_helper_0_0(do_rdhwr_synci_step);
+                tcg_gen_helper_1_1(do_rdhwr_synci_step, cpu_T[0], cpu_T[0]);
                 break;
             case 2:
                 save_cpu_state(ctx, 1);
-                tcg_gen_helper_0_0(do_rdhwr_cc);
+                tcg_gen_helper_1_1(do_rdhwr_cc, cpu_T[0], cpu_T[0]);
                 break;
             case 3:
                 save_cpu_state(ctx, 1);
-                tcg_gen_helper_0_0(do_rdhwr_ccres);
+                tcg_gen_helper_1_1(do_rdhwr_ccres, cpu_T[0], cpu_T[0]);
                 break;
             case 29:
 #if defined (CONFIG_USER_ONLY)
@@ -7241,12 +7304,12 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
             check_insn(env, ctx, ASE_MT);
             gen_load_gpr(cpu_T[0], rt);
             gen_load_gpr(cpu_T[1], rs);
-            tcg_gen_helper_0_0(do_fork);
+            tcg_gen_helper_1_2(do_fork, cpu_T[0], cpu_T[0], cpu_T[1]);
             break;
         case OPC_YIELD:
             check_insn(env, ctx, ASE_MT);
             gen_load_gpr(cpu_T[0], rs);
-            tcg_gen_helper_0_0(do_yield);
+            tcg_gen_helper_1_1(do_yield, cpu_T[0], cpu_T[0]);
             gen_store_gpr(cpu_T[0], rd);
             break;
 #if defined(TARGET_MIPS64)
@@ -7263,11 +7326,11 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
             switch (op2) {
             case OPC_DSBH:
                 gen_load_gpr(cpu_T[1], rt);
-                tcg_gen_helper_0_0(do_dsbh);
+                tcg_gen_helper_1_2(do_dsbh, cpu_T[0], cpu_T[0], cpu_T[1]);
                 break;
             case OPC_DSHD:
                 gen_load_gpr(cpu_T[1], rt);
-                tcg_gen_helper_0_0(do_dshd);
+                tcg_gen_helper_1_2(do_dshd, cpu_T[0], cpu_T[0], cpu_T[1]);
                 break;
             default:            /* Invalid */
                 MIPS_INVAL("dbshfl");
@@ -7330,31 +7393,31 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
             switch (op2) {
             case OPC_DMT:
                 check_insn(env, ctx, ASE_MT);
-                tcg_gen_helper_0_0(do_dmt);
+                tcg_gen_helper_1_1(do_dmt, cpu_T[0], cpu_T[0]);
                 break;
             case OPC_EMT:
                 check_insn(env, ctx, ASE_MT);
-                tcg_gen_helper_0_0(do_emt);
+                tcg_gen_helper_1_1(do_emt, cpu_T[0], cpu_T[0]);
                 break;
             case OPC_DVPE:
                 check_insn(env, ctx, ASE_MT);
-                tcg_gen_helper_0_0(do_dvpe);
+                tcg_gen_helper_1_1(do_dvpe, cpu_T[0], cpu_T[0]);
                 break;
             case OPC_EVPE:
                 check_insn(env, ctx, ASE_MT);
-                tcg_gen_helper_0_0(do_evpe);
+                tcg_gen_helper_1_1(do_evpe, cpu_T[0], cpu_T[0]);
                 break;
             case OPC_DI:
                 check_insn(env, ctx, ISA_MIPS32R2);
                 save_cpu_state(ctx, 1);
-                tcg_gen_helper_0_0(do_di);
+                tcg_gen_helper_1_1(do_di, cpu_T[0], cpu_T[0]);
                 /* Stop translation as we may have switched the execution mode */
                 ctx->bstate = BS_STOP;
                 break;
             case OPC_EI:
                 check_insn(env, ctx, ISA_MIPS32R2);
                 save_cpu_state(ctx, 1);
-                tcg_gen_helper_0_0(do_ei);
+                tcg_gen_helper_1_1(do_ei, cpu_T[0], cpu_T[0]);
                 /* Stop translation as we may have switched the execution mode */
                 ctx->bstate = BS_STOP;
                 break;
@@ -7367,13 +7430,11 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
             break;
         case OPC_RDPGPR:
             check_insn(env, ctx, ISA_MIPS32R2);
-            gen_load_srsgpr(cpu_T[0], rt);
-            gen_store_gpr(cpu_T[0], rd);
+            gen_load_srsgpr(rt, rd);
             break;
         case OPC_WRPGPR:
             check_insn(env, ctx, ISA_MIPS32R2);
-            gen_load_gpr(cpu_T[0], rt);
-            gen_store_srsgpr(cpu_T[0], rd);
+            gen_store_srsgpr(rt, rd);
             break;
         default:
             MIPS_INVAL("cp0");
@@ -7643,7 +7704,7 @@ gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
                 if (env->breakpoints[j] == ctx.pc) {
                     save_cpu_state(&ctx, 1);
                     ctx.bstate = BS_BRANCH;
-                    tcg_gen_helper_0_1i(do_raise_exception, EXCP_DEBUG);
+                    tcg_gen_helper_0_i(do_raise_exception, EXCP_DEBUG);
                     /* Include the breakpoint location or the tb won't
                      * be flushed when it must be.  */
                     ctx.pc += 4;
@@ -7685,7 +7746,7 @@ gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
     }
     if (env->singlestep_enabled) {
         save_cpu_state(&ctx, ctx.bstate == BS_NONE);
-        tcg_gen_helper_0_1i(do_raise_exception, EXCP_DEBUG);
+        tcg_gen_helper_0_i(do_raise_exception, EXCP_DEBUG);
     } else {
 	switch (ctx.bstate) {
         case BS_STOP: