xhci: fix portsc writes
Check for port reset first and skip everything else then. Add sanity checks for PLS updates. Add PLC notification when entering PLS_U0 state. This gets host-initiated port resume going on win8. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
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@ -2592,6 +2592,7 @@ static void xhci_port_notify(XHCIPort *port, uint32_t bits)
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if ((port->portsc & bits) == bits) {
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if ((port->portsc & bits) == bits) {
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return;
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return;
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}
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}
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trace_usb_xhci_port_notify(port->portnr, bits);
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port->portsc |= bits;
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port->portsc |= bits;
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if (!xhci_running(port->xhci)) {
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if (!xhci_running(port->xhci)) {
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return;
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return;
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@ -2798,29 +2799,56 @@ static void xhci_port_write(void *ptr, hwaddr reg,
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uint64_t val, unsigned size)
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uint64_t val, unsigned size)
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{
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{
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XHCIPort *port = ptr;
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XHCIPort *port = ptr;
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uint32_t portsc;
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uint32_t portsc, notify;
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trace_usb_xhci_port_write(port->portnr, reg, val);
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trace_usb_xhci_port_write(port->portnr, reg, val);
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switch (reg) {
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switch (reg) {
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case 0x00: /* PORTSC */
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case 0x00: /* PORTSC */
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/* write-1-to-start bits */
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if (val & PORTSC_PR) {
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xhci_port_reset(port);
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break;
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}
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portsc = port->portsc;
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portsc = port->portsc;
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notify = 0;
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/* write-1-to-clear bits*/
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/* write-1-to-clear bits*/
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portsc &= ~(val & (PORTSC_CSC|PORTSC_PEC|PORTSC_WRC|PORTSC_OCC|
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portsc &= ~(val & (PORTSC_CSC|PORTSC_PEC|PORTSC_WRC|PORTSC_OCC|
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PORTSC_PRC|PORTSC_PLC|PORTSC_CEC));
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PORTSC_PRC|PORTSC_PLC|PORTSC_CEC));
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if (val & PORTSC_LWS) {
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if (val & PORTSC_LWS) {
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/* overwrite PLS only when LWS=1 */
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/* overwrite PLS only when LWS=1 */
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uint32_t pls = get_field(val, PORTSC_PLS);
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uint32_t old_pls = get_field(port->portsc, PORTSC_PLS);
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set_field(&portsc, pls, PORTSC_PLS);
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uint32_t new_pls = get_field(val, PORTSC_PLS);
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trace_usb_xhci_port_link(port->portnr, pls);
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switch (new_pls) {
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case PLS_U0:
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if (old_pls != PLS_U0) {
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set_field(&portsc, new_pls, PORTSC_PLS);
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trace_usb_xhci_port_link(port->portnr, new_pls);
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notify = PORTSC_PLC;
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}
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break;
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case PLS_U3:
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if (old_pls < PLS_U3) {
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set_field(&portsc, new_pls, PORTSC_PLS);
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trace_usb_xhci_port_link(port->portnr, new_pls);
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}
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break;
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case PLS_RESUME:
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/* windows does this for some reason, don't spam stderr */
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break;
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default:
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fprintf(stderr, "%s: ignore pls write (old %d, new %d)\n",
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__func__, old_pls, new_pls);
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break;
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}
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}
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}
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/* read/write bits */
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/* read/write bits */
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portsc &= ~(PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE);
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portsc &= ~(PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE);
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portsc |= (val & (PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE));
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portsc |= (val & (PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE));
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port->portsc = portsc;
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port->portsc = portsc;
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/* write-1-to-start bits */
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if (notify) {
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if (val & PORTSC_PR) {
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xhci_port_notify(port, notify);
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xhci_port_reset(port);
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}
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}
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break;
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break;
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case 0x04: /* PORTPMSC */
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case 0x04: /* PORTPMSC */
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@ -362,6 +362,7 @@ usb_xhci_queue_event(uint32_t vector, uint32_t idx, const char *trb, const char
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usb_xhci_fetch_trb(uint64_t addr, const char *name, uint64_t param, uint32_t status, uint32_t control) "addr %016" PRIx64 ", %s, p %016" PRIx64 ", s %08x, c 0x%08x"
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usb_xhci_fetch_trb(uint64_t addr, const char *name, uint64_t param, uint32_t status, uint32_t control) "addr %016" PRIx64 ", %s, p %016" PRIx64 ", s %08x, c 0x%08x"
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usb_xhci_port_reset(uint32_t port) "port %d"
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usb_xhci_port_reset(uint32_t port) "port %d"
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usb_xhci_port_link(uint32_t port, uint32_t pls) "port %d, pls %d"
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usb_xhci_port_link(uint32_t port, uint32_t pls) "port %d, pls %d"
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usb_xhci_port_notify(uint32_t port, uint32_t pls) "port %d, bits %x"
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usb_xhci_slot_enable(uint32_t slotid) "slotid %d"
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usb_xhci_slot_enable(uint32_t slotid) "slotid %d"
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usb_xhci_slot_disable(uint32_t slotid) "slotid %d"
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usb_xhci_slot_disable(uint32_t slotid) "slotid %d"
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usb_xhci_slot_address(uint32_t slotid) "slotid %d"
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usb_xhci_slot_address(uint32_t slotid) "slotid %d"
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