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target-ppc: indentation fixes

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Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5656 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
aurel32 2008-11-09 17:27:03 +00:00
parent 539390668a
commit bdc4e053d1
1 changed files with 4 additions and 5 deletions
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9
target-ppc/translate.c
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@ -908,7 +908,7 @@ static always_inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1,
tcg_gen_ext32u_tl(t1, arg2); tcg_gen_ext32u_tl(t1, arg2);
if (sub) { if (sub) {
tcg_gen_brcond_tl(TCG_COND_GTU, t0, t1, l1); tcg_gen_brcond_tl(TCG_COND_GTU, t0, t1, l1);
} else { } else {
tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
} }
} else } else
@ -3488,7 +3488,7 @@ static always_inline void gen_goto_tb (DisasContext *ctx, int n,
tcg_gen_movi_tl(cpu_nip, dest & ~3); tcg_gen_movi_tl(cpu_nip, dest & ~3);
if (unlikely(ctx->singlestep_enabled)) { if (unlikely(ctx->singlestep_enabled)) {
if ((ctx->singlestep_enabled & if ((ctx->singlestep_enabled &
(CPU_BRANCH_STEP | CPU_SINGLE_STEP)) && (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
ctx->exception == POWERPC_EXCP_BRANCH) { ctx->exception == POWERPC_EXCP_BRANCH) {
target_ulong tmp = ctx->nip; target_ulong tmp = ctx->nip;
ctx->nip = dest; ctx->nip = dest;
@ -3592,7 +3592,6 @@ static always_inline void gen_bcond (DisasContext *ctx, int type)
} }
} }
if (type == BCOND_IM) { if (type == BCOND_IM) {
target_ulong li = (target_long)((int16_t)(BD(ctx->opcode))); target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
if (likely(AA(ctx->opcode) == 0)) { if (likely(AA(ctx->opcode) == 0)) {
gen_goto_tb(ctx, 0, ctx->nip + li - 4); gen_goto_tb(ctx, 0, ctx->nip + li - 4);
@ -5291,7 +5290,7 @@ static always_inline void gen_405_mulladd_insn (DisasContext *ctx,
tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1); tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
tcg_gen_xor_tl(t1, cpu_gpr[rt], t0); tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1); tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
if (opc3 & 0x02) { if (opc3 & 0x02) {
/* Saturate */ /* Saturate */
tcg_gen_sari_tl(t0, cpu_gpr[rt], 31); tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
tcg_gen_xori_tl(t0, t0, 0x7fffffff); tcg_gen_xori_tl(t0, t0, 0x7fffffff);
@ -5299,7 +5298,7 @@ static always_inline void gen_405_mulladd_insn (DisasContext *ctx,
} else { } else {
/* Unsigned */ /* Unsigned */
tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1); tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
if (opc3 & 0x02) { if (opc3 & 0x02) {
/* Saturate */ /* Saturate */
tcg_gen_movi_tl(t0, UINT32_MAX); tcg_gen_movi_tl(t0, UINT32_MAX);
} }