Merge remote-tracking branch 'afaerber-or/prep-up' into staging
* afaerber-or/prep-up: pc87312: Avoid define conflict on mingw32 pc87312: Replace register_ioport_*() with MemoryRegion Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
commit
bdb8872cc1
64
hw/pc87312.c
64
hw/pc87312.c
@ -34,10 +34,6 @@
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#define REG_FAR 1
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#define REG_PTR 2
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#define FER regs[REG_FER]
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#define FAR regs[REG_FAR]
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#define PTR regs[REG_PTR]
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#define FER_PARALLEL_EN 0x01
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#define FER_UART1_EN 0x02
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#define FER_UART2_EN 0x04
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@ -66,14 +62,14 @@
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static inline bool is_parallel_enabled(PC87312State *s)
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{
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return s->FER & FER_PARALLEL_EN;
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return s->regs[REG_FER] & FER_PARALLEL_EN;
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}
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static const uint32_t parallel_base[] = { 0x378, 0x3bc, 0x278, 0x00 };
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static inline uint32_t get_parallel_iobase(PC87312State *s)
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{
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return parallel_base[s->FAR & FAR_PARALLEL_ADDR];
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return parallel_base[s->regs[REG_FAR] & FAR_PARALLEL_ADDR];
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}
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static const uint32_t parallel_irq[] = { 5, 7, 5, 0 };
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@ -81,9 +77,9 @@ static const uint32_t parallel_irq[] = { 5, 7, 5, 0 };
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static inline uint32_t get_parallel_irq(PC87312State *s)
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{
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int idx;
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idx = (s->FAR & FAR_PARALLEL_ADDR);
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idx = (s->regs[REG_FAR] & FAR_PARALLEL_ADDR);
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if (idx == 0) {
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return (s->PTR & PTR_IRQ_5_7) ? 7 : 5;
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return (s->regs[REG_PTR] & PTR_IRQ_5_7) ? 7 : 5;
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} else {
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return parallel_irq[idx];
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}
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@ -91,7 +87,7 @@ static inline uint32_t get_parallel_irq(PC87312State *s)
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static inline bool is_parallel_epp(PC87312State *s)
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{
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return s->PTR & PTR_EPP_MODE;
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return s->regs[REG_PTR] & PTR_EPP_MODE;
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}
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@ -105,26 +101,26 @@ static const uint32_t uart_base[2][4] = {
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static inline uint32_t get_uart_iobase(PC87312State *s, int i)
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{
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int idx;
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idx = (s->FAR >> (2 * i + 2)) & 0x3;
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idx = (s->regs[REG_FAR] >> (2 * i + 2)) & 0x3;
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if (idx == 0) {
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return 0x3f8;
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} else if (idx == 1) {
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return 0x2f8;
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} else {
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return uart_base[idx & 1][(s->FAR & FAR_UART_3_4) >> 6];
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return uart_base[idx & 1][(s->regs[REG_FAR] & FAR_UART_3_4) >> 6];
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}
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}
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static inline uint32_t get_uart_irq(PC87312State *s, int i)
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{
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int idx;
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idx = (s->FAR >> (2 * i + 2)) & 0x3;
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idx = (s->regs[REG_FAR] >> (2 * i + 2)) & 0x3;
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return (idx & 1) ? 3 : 4;
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}
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static inline bool is_uart_enabled(PC87312State *s, int i)
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{
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return s->FER & (FER_UART1_EN << i);
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return s->regs[REG_FER] & (FER_UART1_EN << i);
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}
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@ -132,12 +128,12 @@ static inline bool is_uart_enabled(PC87312State *s, int i)
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static inline bool is_fdc_enabled(PC87312State *s)
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{
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return s->FER & FER_FDC_EN;
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return s->regs[REG_FER] & FER_FDC_EN;
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}
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static inline uint32_t get_fdc_iobase(PC87312State *s)
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{
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return (s->FER & FER_FDC_ADDR) ? 0x370 : 0x3f0;
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return (s->regs[REG_FER] & FER_FDC_ADDR) ? 0x370 : 0x3f0;
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}
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@ -145,19 +141,19 @@ static inline uint32_t get_fdc_iobase(PC87312State *s)
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static inline bool is_ide_enabled(PC87312State *s)
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{
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return s->FER & FER_IDE_EN;
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return s->regs[REG_FER] & FER_IDE_EN;
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}
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static inline uint32_t get_ide_iobase(PC87312State *s)
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{
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return (s->FER & FER_IDE_ADDR) ? 0x170 : 0x1f0;
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return (s->regs[REG_FER] & FER_IDE_ADDR) ? 0x170 : 0x1f0;
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}
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static void reconfigure_devices(PC87312State *s)
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{
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error_report("pc87312: unsupported device reconfiguration (%02x %02x %02x)",
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s->FER, s->FAR, s->PTR);
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s->regs[REG_FER], s->regs[REG_FAR], s->regs[REG_PTR]);
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}
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static void pc87312_soft_reset(PC87312State *s)
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@ -184,9 +180,9 @@ static void pc87312_soft_reset(PC87312State *s)
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s->read_id_step = 0;
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s->selected_index = REG_FER;
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s->FER = fer_init[s->config & 0x1f];
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s->FAR = far_init[s->config & 0x1f];
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s->PTR = ptr_init[s->config & 0x1f];
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s->regs[REG_FER] = fer_init[s->config & 0x1f];
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s->regs[REG_FAR] = far_init[s->config & 0x1f];
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s->regs[REG_PTR] = ptr_init[s->config & 0x1f];
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}
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static void pc87312_hard_reset(PC87312State *s)
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@ -194,7 +190,8 @@ static void pc87312_hard_reset(PC87312State *s)
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pc87312_soft_reset(s);
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}
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static void pc87312_ioport_write(void *opaque, uint32_t addr, uint32_t val)
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static void pc87312_io_write(void *opaque, hwaddr addr, uint64_t val,
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unsigned int size)
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{
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PC87312State *s = opaque;
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@ -213,7 +210,7 @@ static void pc87312_ioport_write(void *opaque, uint32_t addr, uint32_t val)
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}
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}
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static uint32_t pc87312_ioport_read(void *opaque, uint32_t addr)
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static uint64_t pc87312_io_read(void *opaque, hwaddr addr, unsigned int size)
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{
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PC87312State *s = opaque;
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uint32_t val;
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@ -241,6 +238,16 @@ static uint32_t pc87312_ioport_read(void *opaque, uint32_t addr)
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return val;
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}
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static const MemoryRegionOps pc87312_io_ops = {
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.read = pc87312_io_read,
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.write = pc87312_io_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 1,
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.max_access_size = 1,
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},
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};
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static int pc87312_post_load(void *opaque, int version_id)
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{
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PC87312State *s = opaque;
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@ -270,6 +277,7 @@ static int pc87312_init(ISADevice *dev)
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s = PC87312(dev);
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bus = isa_bus_from_device(dev);
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pc87312_hard_reset(s);
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isa_register_ioport(dev, &s->io, s->iobase);
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if (is_parallel_enabled(s)) {
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chr = parallel_hds[0];
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@ -337,11 +345,16 @@ static int pc87312_init(ISADevice *dev)
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trace_pc87312_info_ide(get_ide_iobase(s));
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}
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register_ioport_write(s->iobase, 2, 1, pc87312_ioport_write, s);
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register_ioport_read(s->iobase, 2, 1, pc87312_ioport_read, s);
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return 0;
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}
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static void pc87312_initfn(Object *obj)
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{
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PC87312State *s = PC87312(obj);
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memory_region_init_io(&s->io, &pc87312_io_ops, s, "pc87312", 2);
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}
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static const VMStateDescription vmstate_pc87312 = {
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.name = "pc87312",
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.version_id = 1,
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@ -376,6 +389,7 @@ static const TypeInfo pc87312_type_info = {
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.name = TYPE_PC87312,
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.parent = TYPE_ISA_DEVICE,
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.instance_size = sizeof(PC87312State),
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.instance_init = pc87312_initfn,
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.class_init = pc87312_class_init,
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};
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@ -56,6 +56,8 @@ typedef struct PC87312State {
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uint32_t base;
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} ide;
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MemoryRegion io;
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uint8_t read_id_step;
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uint8_t selected_index;
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