TCG MIPS and S390 fixes for 2.4.
-----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJVvyHXAAoJELqceAYd3Yyb0ysP+wY3gvuZJ4FRY2zszQ7/0Z08 I9TIWlE+Ty5KY23BdTqVTIcslbIohN6avYTZXnbVXtHiAlktegAGhc7SsJgzNvoi xfntyiQXqtWbR2s/BrNZvBU8Xjirdfz6uJhONBXpYUkDBkHab0ivSDG8D4jr/Kfv yDQalmwGqoI8hrodkoIbIwhlX4wT6OIKY80fYzwJcQEgVO9a31MuK9o+twNqMO7P D0awzky7xleizfuffEDkoMVLX+3zcb/pVYr4zSJws6yDDcm7fsK8BK66/NvQGEd0 PAc1a8aVtqQW2jwXZRzXmdlhpu6EGuhxOkvZepD1lSAuXFBTSMHNy9A4gZzrXBJI F5f1ZcvHsGovudjvQBxnZOPAWpLFV+wmM8YKOLWmVQoudmwm/q7jMyjRIw6nR/Yf oOBWeUgIRZ9wzH+VKj3AjfYeVp6LtNph8hvu4c2/SmlZgYugIKliAwfMVrGmm5Ke YgkCqyR8gF5+9WI9hr8vZjUCqnCjRbkTYkNdpLOzgGOEbpVLLVePm2lTrcMMkjXn OZYC6mXKRsGYpwwkevoQpBQ0PCMVwFBsdHs4mmgS7SAeEv+KECHw+o8DT76qh/o3 0eb0DJFv1T7IrR87uo0uTHzj5tjg1Z1Kxyocey0WW46dVDOiFgHAydSo59x2l6nY /IQSliSUgF/ULdlG1Lmx =3lEa -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/aurel/tags/pull-tcg-mips-s390-20150803' into staging TCG MIPS and S390 fixes for 2.4. # gpg: Signature made Mon Aug 3 09:09:59 2015 BST using RSA key ID 1DDD8C9B # gpg: Good signature from "Aurelien Jarno <aurelien@aurel32.net>" # gpg: aka "Aurelien Jarno <aurelien@jarno.fr>" # gpg: aka "Aurelien Jarno <aurel32@debian.org>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 7746 2642 A9EF 94FD 0F77 196D BA9C 7806 1DDD 8C9B * remotes/aurel/tags/pull-tcg-mips-s390-20150803: tcg/mips: fix add2 tcg/s390x: Mask TCGMemOp appropriately for indexing tcg/mips: Mask TCGMemOp appropriately for indexing tcg/mips: fix TLB loading for BE host with 32-bit guests Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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bd80b5963f
@ -963,9 +963,11 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg base, TCGReg addrl,
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}
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/* Load the tlb comparator. */
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tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, TCG_REG_A0, cmp_off + LO_OFF);
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if (TARGET_LONG_BITS == 64) {
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tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, TCG_REG_A0, cmp_off + LO_OFF);
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tcg_out_opc_imm(s, OPC_LW, base, TCG_REG_A0, cmp_off + HI_OFF);
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} else {
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tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, TCG_REG_A0, cmp_off);
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}
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/* Mask the page bits, keeping the alignment bits to compare against.
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@ -1103,7 +1105,7 @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
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static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,
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TCGReg base, TCGMemOp opc)
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{
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switch (opc) {
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switch (opc & (MO_SSIZE | MO_BSWAP)) {
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case MO_UB:
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tcg_out_opc_imm(s, OPC_LBU, datalo, base, 0);
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break;
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@ -1193,7 +1195,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64)
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static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi,
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TCGReg base, TCGMemOp opc)
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{
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switch (opc) {
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switch (opc & (MO_SIZE | MO_BSWAP)) {
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case MO_8:
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tcg_out_opc_imm(s, OPC_SB, datalo, base, 0);
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break;
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@ -1269,6 +1271,9 @@ static void tcg_out_addsub2(TCGContext *s, TCGReg rl, TCGReg rh, TCGReg al,
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if (cbl) {
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tcg_out_opc_imm(s, OPC_ADDIU, rl, al, bl);
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tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, rl, bl);
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} else if (rl == al && rl == bl) {
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tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, al, 31);
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tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl);
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} else {
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tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl);
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tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, rl, (rl == bl ? al : bl));
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@ -1390,7 +1390,7 @@ static void tcg_out_call(TCGContext *s, tcg_insn_unit *dest)
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static void tcg_out_qemu_ld_direct(TCGContext *s, TCGMemOp opc, TCGReg data,
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TCGReg base, TCGReg index, int disp)
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{
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switch (opc) {
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switch (opc & (MO_SSIZE | MO_BSWAP)) {
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case MO_UB:
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tcg_out_insn(s, RXY, LLGC, data, base, index, disp);
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break;
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@ -1449,7 +1449,7 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, TCGMemOp opc, TCGReg data,
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static void tcg_out_qemu_st_direct(TCGContext *s, TCGMemOp opc, TCGReg data,
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TCGReg base, TCGReg index, int disp)
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{
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switch (opc) {
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switch (opc & (MO_SIZE | MO_BSWAP)) {
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case MO_UB:
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if (disp >= 0 && disp < 0x1000) {
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tcg_out_insn(s, RX, STC, data, base, index, disp);
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