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use generic GenOpFunc

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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@543 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
bellard 2004-01-05 00:06:41 +00:00
parent 16d17fdb8e
commit bd49793889
3 changed files with 4 additions and 36 deletions
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5
target-arm/translate.c
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@ -51,11 +51,6 @@ enum {
#include "gen-op.h"
typedef void (GenOpFunc)(void);
typedef void (GenOpFunc1)(long);
typedef void (GenOpFunc2)(long, long);
typedef void (GenOpFunc3)(long, long, long);
static GenOpFunc2 *gen_test_cc[14] = {
gen_op_test_eq,
gen_op_test_ne,

5
target-i386/translate.c
View File

@ -128,11 +128,6 @@ enum {
NB_OREGS,
};
typedef void (GenOpFunc)(void);
typedef void (GenOpFunc1)(long);
typedef void (GenOpFunc2)(long, long);
typedef void (GenOpFunc3)(long, long, long);
static GenOpFunc *gen_op_mov_reg_T0[3][8] = {
[OT_BYTE] = {
gen_op_movb_EAX_T0,

30
target-sparc/translate.c
View File

@ -2,6 +2,7 @@
SPARC translation
Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
Copyright (C) 2003 Fabrice Bellard
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
@ -19,33 +20,15 @@
*/
/*
SPARC has two pitfalls: Delay slots and (a)nullification.
This is currently solved as follows:
'call' instructions simply execute the delay slot before the actual
control transfer instructions.
'jmpl' instructions execute calculate the destination, then execute
the delay slot and then do the control transfer.
(conditional) branch instructions are the most difficult ones, as the
delay slot may be nullified (ie. not executed). This happens when a
conditional branch is not executed (thus no control transfer happens)
and the 'anull' bit in the branch instruction opcode is set. This is
currently solved by doing a jump after the delay slot instruction.
TODO-list:
Register window overflow/underflow check
NPC/PC static optimisations (use JUMP_TB when possible)
FPU-Instructions
Coprocessor-Instructions
Check signedness issues
Privileged instructions
Coprocessor-Instructions
Optimize synthetic instructions
Optional alignment and privileged instruction check
-- TMO, 09/03/03
*/
*/
#include <stdarg.h>
#include <stdlib.h>
@ -87,11 +70,6 @@ enum {
static void disas_sparc_insn(DisasContext * dc);
typedef void (GenOpFunc) (void);
typedef void (GenOpFunc1) (long);
typedef void (GenOpFunc2) (long, long);
typedef void (GenOpFunc3) (long, long, long);
static GenOpFunc *gen_op_movl_TN_reg[2][32] = {
{
gen_op_movl_g0_T0,