ppc/translate: Rewrite gen_lxvdsx to use gvec primitives
Make the implementation match the lxvwsx one. The code is now shorter smaller and potentially faster as the translation will use the host SIMD capabilities if available. No functional change. Signed-off-by: Giuseppe Musacchio <thatlemon@gmail.com> Message-Id: <a463dea379da4cb3a22de49c678932f74fb15dd7.1604912739.git.thatlemon@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -75,29 +75,6 @@ static void gen_lxvd2x(DisasContext *ctx)
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tcg_temp_free_i64(t0);
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tcg_temp_free_i64(t0);
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}
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}
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static void gen_lxvdsx(DisasContext *ctx)
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{
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TCGv EA;
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TCGv_i64 t0;
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TCGv_i64 t1;
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if (unlikely(!ctx->vsx_enabled)) {
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gen_exception(ctx, POWERPC_EXCP_VSXU);
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return;
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}
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t0 = tcg_temp_new_i64();
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t1 = tcg_temp_new_i64();
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gen_set_access_type(ctx, ACCESS_INT);
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EA = tcg_temp_new();
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gen_addr_reg_index(ctx, EA);
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gen_qemu_ld64_i64(ctx, t0, EA);
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set_cpu_vsrh(xT(ctx->opcode), t0);
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tcg_gen_mov_i64(t1, t0);
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set_cpu_vsrl(xT(ctx->opcode), t1);
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tcg_temp_free(EA);
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tcg_temp_free_i64(t0);
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tcg_temp_free_i64(t1);
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}
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static void gen_lxvw4x(DisasContext *ctx)
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static void gen_lxvw4x(DisasContext *ctx)
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{
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{
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TCGv EA;
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TCGv EA;
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@ -169,6 +146,29 @@ static void gen_lxvwsx(DisasContext *ctx)
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tcg_temp_free_i32(data);
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tcg_temp_free_i32(data);
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}
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}
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static void gen_lxvdsx(DisasContext *ctx)
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{
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TCGv EA;
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TCGv_i64 data;
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if (unlikely(!ctx->vsx_enabled)) {
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gen_exception(ctx, POWERPC_EXCP_VSXU);
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return;
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}
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gen_set_access_type(ctx, ACCESS_INT);
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EA = tcg_temp_new();
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gen_addr_reg_index(ctx, EA);
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data = tcg_temp_new_i64();
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tcg_gen_qemu_ld_i64(data, EA, ctx->mem_idx, MO_TEQ);
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tcg_gen_gvec_dup_i64(MO_Q, vsr_full_offset(xT(ctx->opcode)), 16, 16, data);
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tcg_temp_free(EA);
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tcg_temp_free_i64(data);
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}
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static void gen_bswap16x8(TCGv_i64 outh, TCGv_i64 outl,
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static void gen_bswap16x8(TCGv_i64 outh, TCGv_i64 outl,
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TCGv_i64 inh, TCGv_i64 inl)
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TCGv_i64 inh, TCGv_i64 inl)
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{
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{
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