Make address_space_translate{, _cached}() take a MemTxAttrs argument
As part of plumbing MemTxAttrs down to the IOMMU translate method, add MemTxAttrs as an argument to address_space_translate() and address_space_translate_cached(). Callers either have an attrs value to hand, or don't care and can use MEMTXATTRS_UNSPECIFIED. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180521140402.23318-4-peter.maydell@linaro.org
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c874dc4f5e
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bc6b1cec84
@ -1676,7 +1676,7 @@ void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
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hwaddr l = 1;
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hwaddr l = 1;
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rcu_read_lock();
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rcu_read_lock();
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mr = address_space_translate(as, addr, &addr, &l, false);
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mr = address_space_translate(as, addr, &addr, &l, false, attrs);
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if (!(memory_region_is_ram(mr)
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if (!(memory_region_is_ram(mr)
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|| memory_region_is_romd(mr))) {
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|| memory_region_is_romd(mr))) {
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rcu_read_unlock();
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rcu_read_unlock();
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14
exec.c
14
exec.c
@ -3322,7 +3322,8 @@ static inline void cpu_physical_memory_write_rom_internal(AddressSpace *as,
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rcu_read_lock();
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rcu_read_lock();
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while (len > 0) {
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while (len > 0) {
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l = len;
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l = len;
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mr = address_space_translate(as, addr, &addr1, &l, true);
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mr = address_space_translate(as, addr, &addr1, &l, true,
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MEMTXATTRS_UNSPECIFIED);
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if (!(memory_region_is_ram(mr) ||
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if (!(memory_region_is_ram(mr) ||
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memory_region_is_romd(mr))) {
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memory_region_is_romd(mr))) {
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@ -3699,7 +3700,7 @@ void address_space_cache_destroy(MemoryRegionCache *cache)
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*/
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*/
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static inline MemoryRegion *address_space_translate_cached(
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static inline MemoryRegion *address_space_translate_cached(
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MemoryRegionCache *cache, hwaddr addr, hwaddr *xlat,
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MemoryRegionCache *cache, hwaddr addr, hwaddr *xlat,
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hwaddr *plen, bool is_write)
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hwaddr *plen, bool is_write, MemTxAttrs attrs)
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{
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{
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MemoryRegionSection section;
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MemoryRegionSection section;
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MemoryRegion *mr;
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MemoryRegion *mr;
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@ -3733,7 +3734,8 @@ address_space_read_cached_slow(MemoryRegionCache *cache, hwaddr addr,
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MemoryRegion *mr;
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MemoryRegion *mr;
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l = len;
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l = len;
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mr = address_space_translate_cached(cache, addr, &addr1, &l, false);
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mr = address_space_translate_cached(cache, addr, &addr1, &l, false,
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MEMTXATTRS_UNSPECIFIED);
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flatview_read_continue(cache->fv,
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flatview_read_continue(cache->fv,
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addr, MEMTXATTRS_UNSPECIFIED, buf, len,
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addr, MEMTXATTRS_UNSPECIFIED, buf, len,
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addr1, l, mr);
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addr1, l, mr);
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@ -3750,7 +3752,8 @@ address_space_write_cached_slow(MemoryRegionCache *cache, hwaddr addr,
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MemoryRegion *mr;
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MemoryRegion *mr;
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l = len;
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l = len;
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mr = address_space_translate_cached(cache, addr, &addr1, &l, true);
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mr = address_space_translate_cached(cache, addr, &addr1, &l, true,
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MEMTXATTRS_UNSPECIFIED);
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flatview_write_continue(cache->fv,
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flatview_write_continue(cache->fv,
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addr, MEMTXATTRS_UNSPECIFIED, buf, len,
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addr, MEMTXATTRS_UNSPECIFIED, buf, len,
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addr1, l, mr);
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addr1, l, mr);
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@ -3848,7 +3851,8 @@ bool cpu_physical_memory_is_io(hwaddr phys_addr)
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rcu_read_lock();
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rcu_read_lock();
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mr = address_space_translate(&address_space_memory,
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mr = address_space_translate(&address_space_memory,
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phys_addr, &phys_addr, &l, false);
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phys_addr, &phys_addr, &l, false,
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MEMTXATTRS_UNSPECIFIED);
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res = !(memory_region_is_ram(mr) || memory_region_is_romd(mr));
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res = !(memory_region_is_ram(mr) || memory_region_is_romd(mr));
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rcu_read_unlock();
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rcu_read_unlock();
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@ -324,7 +324,8 @@ static bool vfio_get_vaddr(IOMMUTLBEntry *iotlb, void **vaddr,
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*/
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*/
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mr = address_space_translate(&address_space_memory,
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mr = address_space_translate(&address_space_memory,
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iotlb->translated_addr,
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iotlb->translated_addr,
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&xlat, &len, writable);
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&xlat, &len, writable,
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MEMTXATTRS_UNSPECIFIED);
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if (!memory_region_is_ram(mr)) {
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if (!memory_region_is_ram(mr)) {
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error_report("iommu map to non memory area %"HWADDR_PRIx"",
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error_report("iommu map to non memory area %"HWADDR_PRIx"",
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xlat);
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xlat);
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@ -1908,6 +1908,7 @@ IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
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* #MemoryRegion.
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* #MemoryRegion.
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* @len: pointer to length
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* @len: pointer to length
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* @is_write: indicates the transfer direction
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* @is_write: indicates the transfer direction
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* @attrs: memory attributes
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*/
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*/
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MemoryRegion *flatview_translate(FlatView *fv,
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MemoryRegion *flatview_translate(FlatView *fv,
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hwaddr addr, hwaddr *xlat,
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hwaddr addr, hwaddr *xlat,
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@ -1915,7 +1916,8 @@ MemoryRegion *flatview_translate(FlatView *fv,
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static inline MemoryRegion *address_space_translate(AddressSpace *as,
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static inline MemoryRegion *address_space_translate(AddressSpace *as,
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hwaddr addr, hwaddr *xlat,
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hwaddr addr, hwaddr *xlat,
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hwaddr *len, bool is_write)
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hwaddr *len, bool is_write,
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MemTxAttrs attrs)
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{
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{
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return flatview_translate(address_space_to_flatview(as),
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return flatview_translate(address_space_to_flatview(as),
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addr, xlat, len, is_write);
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addr, xlat, len, is_write);
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@ -33,7 +33,7 @@ static inline uint32_t glue(address_space_ldl_internal, SUFFIX)(ARG1_DECL,
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bool release_lock = false;
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bool release_lock = false;
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RCU_READ_LOCK();
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RCU_READ_LOCK();
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mr = TRANSLATE(addr, &addr1, &l, false);
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mr = TRANSLATE(addr, &addr1, &l, false, attrs);
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if (l < 4 || !IS_DIRECT(mr, false)) {
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if (l < 4 || !IS_DIRECT(mr, false)) {
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release_lock |= prepare_mmio_access(mr);
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release_lock |= prepare_mmio_access(mr);
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@ -109,7 +109,7 @@ static inline uint64_t glue(address_space_ldq_internal, SUFFIX)(ARG1_DECL,
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bool release_lock = false;
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bool release_lock = false;
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RCU_READ_LOCK();
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RCU_READ_LOCK();
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mr = TRANSLATE(addr, &addr1, &l, false);
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mr = TRANSLATE(addr, &addr1, &l, false, attrs);
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if (l < 8 || !IS_DIRECT(mr, false)) {
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if (l < 8 || !IS_DIRECT(mr, false)) {
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release_lock |= prepare_mmio_access(mr);
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release_lock |= prepare_mmio_access(mr);
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@ -183,7 +183,7 @@ uint32_t glue(address_space_ldub, SUFFIX)(ARG1_DECL,
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bool release_lock = false;
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bool release_lock = false;
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RCU_READ_LOCK();
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RCU_READ_LOCK();
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mr = TRANSLATE(addr, &addr1, &l, false);
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mr = TRANSLATE(addr, &addr1, &l, false, attrs);
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if (!IS_DIRECT(mr, false)) {
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if (!IS_DIRECT(mr, false)) {
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release_lock |= prepare_mmio_access(mr);
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release_lock |= prepare_mmio_access(mr);
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@ -219,7 +219,7 @@ static inline uint32_t glue(address_space_lduw_internal, SUFFIX)(ARG1_DECL,
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bool release_lock = false;
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bool release_lock = false;
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RCU_READ_LOCK();
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RCU_READ_LOCK();
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mr = TRANSLATE(addr, &addr1, &l, false);
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mr = TRANSLATE(addr, &addr1, &l, false, attrs);
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if (l < 2 || !IS_DIRECT(mr, false)) {
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if (l < 2 || !IS_DIRECT(mr, false)) {
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release_lock |= prepare_mmio_access(mr);
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release_lock |= prepare_mmio_access(mr);
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@ -296,7 +296,7 @@ void glue(address_space_stl_notdirty, SUFFIX)(ARG1_DECL,
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bool release_lock = false;
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bool release_lock = false;
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RCU_READ_LOCK();
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RCU_READ_LOCK();
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mr = TRANSLATE(addr, &addr1, &l, true);
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mr = TRANSLATE(addr, &addr1, &l, true, attrs);
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if (l < 4 || !IS_DIRECT(mr, true)) {
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if (l < 4 || !IS_DIRECT(mr, true)) {
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release_lock |= prepare_mmio_access(mr);
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release_lock |= prepare_mmio_access(mr);
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@ -333,7 +333,7 @@ static inline void glue(address_space_stl_internal, SUFFIX)(ARG1_DECL,
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bool release_lock = false;
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bool release_lock = false;
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RCU_READ_LOCK();
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RCU_READ_LOCK();
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mr = TRANSLATE(addr, &addr1, &l, true);
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mr = TRANSLATE(addr, &addr1, &l, true, attrs);
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if (l < 4 || !IS_DIRECT(mr, true)) {
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if (l < 4 || !IS_DIRECT(mr, true)) {
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release_lock |= prepare_mmio_access(mr);
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release_lock |= prepare_mmio_access(mr);
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@ -405,7 +405,7 @@ void glue(address_space_stb, SUFFIX)(ARG1_DECL,
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bool release_lock = false;
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bool release_lock = false;
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RCU_READ_LOCK();
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RCU_READ_LOCK();
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mr = TRANSLATE(addr, &addr1, &l, true);
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mr = TRANSLATE(addr, &addr1, &l, true, attrs);
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if (!IS_DIRECT(mr, true)) {
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if (!IS_DIRECT(mr, true)) {
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release_lock |= prepare_mmio_access(mr);
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release_lock |= prepare_mmio_access(mr);
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r = memory_region_dispatch_write(mr, addr1, val, 1, attrs);
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r = memory_region_dispatch_write(mr, addr1, val, 1, attrs);
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@ -438,7 +438,7 @@ static inline void glue(address_space_stw_internal, SUFFIX)(ARG1_DECL,
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bool release_lock = false;
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bool release_lock = false;
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RCU_READ_LOCK();
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RCU_READ_LOCK();
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mr = TRANSLATE(addr, &addr1, &l, true);
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mr = TRANSLATE(addr, &addr1, &l, true, attrs);
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if (l < 2 || !IS_DIRECT(mr, true)) {
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if (l < 2 || !IS_DIRECT(mr, true)) {
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release_lock |= prepare_mmio_access(mr);
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release_lock |= prepare_mmio_access(mr);
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@ -511,7 +511,7 @@ static void glue(address_space_stq_internal, SUFFIX)(ARG1_DECL,
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bool release_lock = false;
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bool release_lock = false;
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RCU_READ_LOCK();
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RCU_READ_LOCK();
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mr = TRANSLATE(addr, &addr1, &l, true);
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mr = TRANSLATE(addr, &addr1, &l, true, attrs);
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if (l < 8 || !IS_DIRECT(mr, true)) {
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if (l < 8 || !IS_DIRECT(mr, true)) {
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release_lock |= prepare_mmio_access(mr);
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release_lock |= prepare_mmio_access(mr);
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@ -664,7 +664,8 @@ int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route,
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/* MSI doorbell address is translated by an IOMMU */
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/* MSI doorbell address is translated by an IOMMU */
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rcu_read_lock();
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rcu_read_lock();
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mr = address_space_translate(as, address, &xlat, &len, true);
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mr = address_space_translate(as, address, &xlat, &len, true,
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MEMTXATTRS_UNSPECIFIED);
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if (!mr) {
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if (!mr) {
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goto unlock;
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goto unlock;
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}
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}
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@ -210,7 +210,7 @@ restart:
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MemoryRegion *mr;
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MemoryRegion *mr;
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hwaddr l = sizeof(target_ulong), addr1;
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hwaddr l = sizeof(target_ulong), addr1;
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mr = address_space_translate(cs->as, pte_addr,
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mr = address_space_translate(cs->as, pte_addr,
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&addr1, &l, false);
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&addr1, &l, false, MEMTXATTRS_UNSPECIFIED);
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if (memory_access_is_direct(mr, true)) {
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if (memory_access_is_direct(mr, true)) {
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target_ulong *pte_pa =
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target_ulong *pte_pa =
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qemu_map_ram_ptr(mr->ram_block, addr1);
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qemu_map_ram_ptr(mr->ram_block, addr1);
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