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target/sparc: Implement FPADD64, FPSUB64

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Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-11-04 16:39:12 -07:00
parent d6ff1ccb45
commit bc3f14a9ed
2 changed files with 5 additions and 0 deletions
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2
target/sparc/insns.decode
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@ -441,10 +441,12 @@ FCMPEq 10 000 cc:2 110101 ..... 0 0101 0111 ..... \
FPADD16s 10 ..... 110110 ..... 0 0101 0001 ..... @r_r_r
FPADD32 10 ..... 110110 ..... 0 0101 0010 ..... @d_d_d
FPADD32s 10 ..... 110110 ..... 0 0101 0011 ..... @r_r_r
FPADD64 10 ..... 110110 ..... 0 0100 0010 ..... @d_d_d
FPSUB16 10 ..... 110110 ..... 0 0101 0100 ..... @d_d_d
FPSUB16s 10 ..... 110110 ..... 0 0101 0101 ..... @r_r_r
FPSUB32 10 ..... 110110 ..... 0 0101 0110 ..... @d_d_d
FPSUB32s 10 ..... 110110 ..... 0 0101 0111 ..... @r_r_r
FPSUB64 10 ..... 110110 ..... 0 0100 0110 ..... @d_d_d
FNORd 10 ..... 110110 ..... 0 0110 0010 ..... @d_d_d
FNORs 10 ..... 110110 ..... 0 0110 0011 ..... @r_r_r

3
target/sparc/translate.c
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@ -4912,6 +4912,9 @@ TRANS(FHADDd, VIS3, do_ddd, a, gen_op_fhaddd)
TRANS(FHSUBd, VIS3, do_ddd, a, gen_op_fhsubd)
TRANS(FNHADDd, VIS3, do_ddd, a, gen_op_fnhaddd)
TRANS(FPADD64, VIS3B, do_ddd, a, tcg_gen_add_i64)
TRANS(FPSUB64, VIS3B, do_ddd, a, tcg_gen_sub_i64)
static bool do_rdd(DisasContext *dc, arg_r_r_r *a,
void (*func)(TCGv, TCGv_i64, TCGv_i64))
{