From 72bace2d13cb427fde3bb50ae1a71a2abe9acc0f Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Sat, 2 Mar 2024 15:10:00 -1000 Subject: [PATCH 1/9] target/hppa: Fix assemble_16 insns for wide mode Reported-by: Sven Schnelle Reviewed-by: Helge Deller Signed-off-by: Richard Henderson --- target/hppa/insns.decode | 15 +++++++++------ target/hppa/translate.c | 22 ++++++++++++++++++++++ 2 files changed, 31 insertions(+), 6 deletions(-) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index f5a3f02fd1..0d9f8159ec 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -27,13 +27,14 @@ %assemble_11a 0:s1 4:10 !function=expand_shl3 %assemble_12 0:s1 2:1 3:10 !function=expand_shl2 %assemble_12a 0:s1 3:11 !function=expand_shl2 +%assemble_16 0:16 !function=expand_16 %assemble_17 0:s1 16:5 2:1 3:10 !function=expand_shl2 %assemble_22 0:s1 16:10 2:1 3:10 !function=expand_shl2 +%assemble_sp 14:2 !function=sp0_if_wide %assemble_21 0:s1 1:11 14:2 16:5 12:2 !function=expand_shl11 %lowsign_11 0:s1 1:10 -%lowsign_14 0:s1 1:13 %sm_imm 16:10 !function=expand_sm_imm @@ -221,7 +222,7 @@ sub_b_tsv 000010 ..... ..... .... 110100 . ..... @rrr_cf_d ldil 001000 t:5 ..................... i=%assemble_21 addil 001010 r:5 ..................... i=%assemble_21 -ldo 001101 b:5 t:5 -- .............. i=%lowsign_14 +ldo 001101 b:5 t:5 ................ i=%assemble_16 addi 101101 ..... ..... .... 0 ........... @rri_cf addi_tsv 101101 ..... ..... .... 1 ........... @rri_cf @@ -306,10 +307,12 @@ fstd 001011 ..... ..... .. . 1 -- 100 0 . ..... @fldstdi @ldstim11 ...... b:5 t:5 sp:2 .............. \ &ldst disp=%assemble_11a m=%ma2_to_m x=0 scale=0 size=3 -@ldstim14 ...... b:5 t:5 sp:2 .............. \ - &ldst disp=%lowsign_14 x=0 scale=0 m=0 -@ldstim14m ...... b:5 t:5 sp:2 .............. \ - &ldst disp=%lowsign_14 x=0 scale=0 m=%neg_to_m +@ldstim14 ...... b:5 t:5 ................ \ + &ldst sp=%assemble_sp disp=%assemble_16 \ + x=0 scale=0 m=0 +@ldstim14m ...... b:5 t:5 ................ \ + &ldst sp=%assemble_sp disp=%assemble_16 \ + x=0 scale=0 m=%neg_to_m @ldstim12m ...... b:5 t:5 sp:2 .............. \ &ldst disp=%assemble_12a x=0 scale=0 m=%pos_to_m diff --git a/target/hppa/translate.c b/target/hppa/translate.c index eb2046c5ad..cbe44ef75a 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -144,6 +144,28 @@ static int assemble_6(DisasContext *ctx, int val) return (val ^ 31) + 1; } +/* Expander for assemble_16(s,im14). */ +static int expand_16(DisasContext *ctx, int val) +{ + /* + * @val is bits [0:15], containing both im14 and s. + * Swizzle thing around depending on PSW.W. + */ + int s = extract32(val, 14, 2); + int i = (-(val & 1) << 13) | extract32(val, 1, 13); + + if (ctx->tb_flags & PSW_W) { + i ^= s << 13; + } + return i; +} + +/* The sp field is only present with !PSW_W. */ +static int sp0_if_wide(DisasContext *ctx, int sp) +{ + return ctx->tb_flags & PSW_W ? 0 : sp; +} + /* Translate CMPI doubleword conditions to standard. */ static int cmpbid_c(DisasContext *ctx, int val) { From 4768c28edd4097ebef42822e15b4a43026b15376 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Sat, 2 Mar 2024 15:38:17 -1000 Subject: [PATCH 2/9] target/hppa: Fix assemble_11a insns for wide mode Tested-by: Helge Deller Reviewed-by: Helge Deller Reported-by: Sven Schnelle Signed-off-by: Richard Henderson --- target/hppa/insns.decode | 7 ++++--- target/hppa/translate.c | 23 +++++++++++++++++------ 2 files changed, 21 insertions(+), 9 deletions(-) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index 0d9f8159ec..9c6f92444c 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -24,7 +24,7 @@ %assemble_sr3 13:1 14:2 %assemble_sr3x 13:1 14:2 !function=expand_sr3x -%assemble_11a 0:s1 4:10 !function=expand_shl3 +%assemble_11a 4:12 0:1 !function=expand_11a %assemble_12 0:s1 2:1 3:10 !function=expand_shl2 %assemble_12a 0:s1 3:11 !function=expand_shl2 %assemble_16 0:16 !function=expand_16 @@ -305,8 +305,9 @@ fstd 001011 ..... ..... .. . 1 -- 100 0 . ..... @fldstdi # Offset Mem #### -@ldstim11 ...... b:5 t:5 sp:2 .............. \ - &ldst disp=%assemble_11a m=%ma2_to_m x=0 scale=0 size=3 +@ldstim11 ...... b:5 t:5 ................ \ + &ldst sp=%assemble_sp disp=%assemble_11a \ + m=%ma2_to_m x=0 scale=0 size=3 @ldstim14 ...... b:5 t:5 ................ \ &ldst sp=%assemble_sp disp=%assemble_16 \ x=0 scale=0 m=0 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index cbe44ef75a..40b9ff6d59 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -121,12 +121,6 @@ static int expand_shl2(DisasContext *ctx, int val) return val << 2; } -/* Used for fp memory ops. */ -static int expand_shl3(DisasContext *ctx, int val) -{ - return val << 3; -} - /* Used for assemble_21. */ static int expand_shl11(DisasContext *ctx, int val) { @@ -144,6 +138,23 @@ static int assemble_6(DisasContext *ctx, int val) return (val ^ 31) + 1; } +/* Expander for assemble_16a(s,cat(im10a,0),i). */ +static int expand_11a(DisasContext *ctx, int val) +{ + /* + * @val is bit 0 and bits [4:15]. + * Swizzle thing around depending on PSW.W. + */ + int im10a = extract32(val, 1, 10); + int s = extract32(val, 11, 2); + int i = (-(val & 1) << 13) | (im10a << 3); + + if (ctx->tb_flags & PSW_W) { + i ^= s << 13; + } + return i; +} + /* Expander for assemble_16(s,im14). */ static int expand_16(DisasContext *ctx, int val) { From 46174e140d274385b1255bc7f16a5a711853053f Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Sat, 2 Mar 2024 15:48:48 -1000 Subject: [PATCH 3/9] target/hppa: Fix assemble_12a insns for wide mode Tested-by: Helge Deller Reported-by: Sven Schnelle Signed-off-by: Richard Henderson --- target/hppa/insns.decode | 27 ++++++++++++++++----------- target/hppa/translate.c | 17 +++++++++++++++++ 2 files changed, 33 insertions(+), 11 deletions(-) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index 9c6f92444c..5412ff9836 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -26,7 +26,7 @@ %assemble_11a 4:12 0:1 !function=expand_11a %assemble_12 0:s1 2:1 3:10 !function=expand_shl2 -%assemble_12a 0:s1 3:11 !function=expand_shl2 +%assemble_12a 3:13 0:1 !function=expand_12a %assemble_16 0:16 !function=expand_16 %assemble_17 0:s1 16:5 2:1 3:10 !function=expand_shl2 %assemble_22 0:s1 16:10 2:1 3:10 !function=expand_shl2 @@ -314,8 +314,9 @@ fstd 001011 ..... ..... .. . 1 -- 100 0 . ..... @fldstdi @ldstim14m ...... b:5 t:5 ................ \ &ldst sp=%assemble_sp disp=%assemble_16 \ x=0 scale=0 m=%neg_to_m -@ldstim12m ...... b:5 t:5 sp:2 .............. \ - &ldst disp=%assemble_12a x=0 scale=0 m=%pos_to_m +@ldstim12m ...... b:5 t:5 ................ \ + &ldst sp=%assemble_sp disp=%assemble_12a \ + x=0 scale=0 m=%pos_to_m # LDB, LDH, LDW, LDWM ld 010000 ..... ..... .. .............. @ldstim14 size=0 @@ -331,15 +332,19 @@ st 011010 ..... ..... .. .............. @ldstim14 size=2 st 011011 ..... ..... .. .............. @ldstim14m size=2 st 011111 ..... ..... .. ...........10. @ldstim12m size=2 -fldw 010110 b:5 ..... sp:2 .............. \ - &ldst disp=%assemble_12a t=%rm64 m=%a_to_m x=0 scale=0 size=2 -fldw 010111 b:5 ..... sp:2 ...........0.. \ - &ldst disp=%assemble_12a t=%rm64 m=0 x=0 scale=0 size=2 +fldw 010110 b:5 ..... ................ \ + &ldst disp=%assemble_12a sp=%assemble_sp \ + t=%rm64 m=%a_to_m x=0 scale=0 size=2 +fldw 010111 b:5 ..... .............0.. \ + &ldst disp=%assemble_12a sp=%assemble_sp \ + t=%rm64 m=0 x=0 scale=0 size=2 -fstw 011110 b:5 ..... sp:2 .............. \ - &ldst disp=%assemble_12a t=%rm64 m=%a_to_m x=0 scale=0 size=2 -fstw 011111 b:5 ..... sp:2 ...........0.. \ - &ldst disp=%assemble_12a t=%rm64 m=0 x=0 scale=0 size=2 +fstw 011110 b:5 ..... ................ \ + &ldst disp=%assemble_12a sp=%assemble_sp \ + t=%rm64 m=%a_to_m x=0 scale=0 size=2 +fstw 011111 b:5 ..... .............0.. \ + &ldst disp=%assemble_12a sp=%assemble_sp \ + t=%rm64 m=0 x=0 scale=0 size=2 ld 010100 ..... ..... .. ............0. @ldstim11 fldd 010100 ..... ..... .. ............1. @ldstim11 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 40b9ff6d59..be0b0494d0 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -155,6 +155,23 @@ static int expand_11a(DisasContext *ctx, int val) return i; } +/* Expander for assemble_16a(s,im11a,i). */ +static int expand_12a(DisasContext *ctx, int val) +{ + /* + * @val is bit 0 and bits [3:15]. + * Swizzle thing around depending on PSW.W. + */ + int im11a = extract32(val, 1, 11); + int s = extract32(val, 12, 2); + int i = (-(val & 1) << 13) | (im11a << 2); + + if (ctx->tb_flags & PSW_W) { + i ^= s << 13; + } + return i; +} + /* Expander for assemble_16(s,im14). */ static int expand_16(DisasContext *ctx, int val) { From c3ea1996a14d5dbbedb3f9036f7ebec4395dc889 Mon Sep 17 00:00:00 2001 From: Sven Schnelle Date: Tue, 19 Mar 2024 17:19:16 +0100 Subject: [PATCH 4/9] target/hppa: ldcw,s uses static shift of 3 Fixes: 96d6407f363 ("target-hppa: Implement loads and stores") Signed-off-by: Sven Schnelle Reviewed-by: Richard Henderson Message-Id: <20240319161921.487080-2-svens@stackframe.org> Signed-off-by: Richard Henderson --- target/hppa/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index be0b0494d0..47c6db78c7 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3135,7 +3135,7 @@ static bool trans_ldc(DisasContext *ctx, arg_ldst *a) dest = dest_gpr(ctx, a->t); } - form_gva(ctx, &addr, &ofs, a->b, a->x, a->scale ? a->size : 0, + form_gva(ctx, &addr, &ofs, a->b, a->x, a->scale ? 3 : 0, a->disp, a->sp, a->m, MMU_DISABLED(ctx)); /* From d37fad0ae5bd2c544fdb0f2eff6acdb28a155be0 Mon Sep 17 00:00:00 2001 From: Sven Schnelle Date: Tue, 19 Mar 2024 17:19:17 +0100 Subject: [PATCH 5/9] target/hppa: fix shrp for wide mode Fixes: f7b775a9c075 ("target/hppa: Implement SHRPD") Signed-off-by: Sven Schnelle Reviewed-by: Richard Henderson Reviewed-by: Helge Deller Message-Id: <20240319161921.487080-3-svens@stackframe.org> Signed-off-by: Richard Henderson --- target/hppa/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 47c6db78c7..29ef061baf 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3512,7 +3512,7 @@ static bool trans_shrp_sar(DisasContext *ctx, arg_shrp_sar *a) /* Install the new nullification. */ cond_free(&ctx->null_cond); if (a->c) { - ctx->null_cond = do_sed_cond(ctx, a->c, false, dest); + ctx->null_cond = do_sed_cond(ctx, a->c, a->d, dest); } return nullify_end(ctx); } @@ -3555,7 +3555,7 @@ static bool trans_shrp_imm(DisasContext *ctx, arg_shrp_imm *a) /* Install the new nullification. */ cond_free(&ctx->null_cond); if (a->c) { - ctx->null_cond = do_sed_cond(ctx, a->c, false, dest); + ctx->null_cond = do_sed_cond(ctx, a->c, a->d, dest); } return nullify_end(ctx); } From ae157fc25053917830c3b581bc282f906e6d95d3 Mon Sep 17 00:00:00 2001 From: Sven Schnelle Date: Tue, 19 Mar 2024 17:19:18 +0100 Subject: [PATCH 6/9] target/hppa: fix access_id check PA2.0 provides 8 instead of 4 PID registers. Signed-off-by: Sven Schnelle Reviewed-by: Richard Henderson Message-Id: <20240319161921.487080-4-svens@stackframe.org> Signed-off-by: Richard Henderson --- target/hppa/mem_helper.c | 80 +++++++++++++++++++++++++++++++--------- 1 file changed, 62 insertions(+), 18 deletions(-) diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 80f51e753f..84785b5a5c 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -152,6 +152,49 @@ static HPPATLBEntry *hppa_alloc_tlb_ent(CPUHPPAState *env) return ent; } +#define ACCESS_ID_MASK 0xffff + +/* Return the set of protections allowed by a PID match. */ +static int match_prot_id_1(uint32_t access_id, uint32_t prot_id) +{ + if (((access_id ^ (prot_id >> 1)) & ACCESS_ID_MASK) == 0) { + return (prot_id & 1 + ? PAGE_EXEC | PAGE_READ + : PAGE_EXEC | PAGE_READ | PAGE_WRITE); + } + return 0; +} + +static int match_prot_id32(CPUHPPAState *env, uint32_t access_id) +{ + int r, i; + + for (i = CR_PID1; i <= CR_PID4; ++i) { + r = match_prot_id_1(access_id, env->cr[i]); + if (r) { + return r; + } + } + return 0; +} + +static int match_prot_id64(CPUHPPAState *env, uint32_t access_id) +{ + int r, i; + + for (i = CR_PID1; i <= CR_PID4; ++i) { + r = match_prot_id_1(access_id, env->cr[i]); + if (r) { + return r; + } + r = match_prot_id_1(access_id, env->cr[i] >> 32); + if (r) { + return r; + } + } + return 0; +} + int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, int type, hwaddr *pphys, int *pprot, HPPATLBEntry **tlb_entry) @@ -224,29 +267,30 @@ int hppa_get_physical_address(CPUHPPAState *env, vaddr addr, int mmu_idx, break; } - /* access_id == 0 means public page and no check is performed */ - if (ent->access_id && MMU_IDX_TO_P(mmu_idx)) { - /* If bits [31:1] match, and bit 0 is set, suppress write. */ - int match = ent->access_id * 2 + 1; - - if (match == env->cr[CR_PID1] || match == env->cr[CR_PID2] || - match == env->cr[CR_PID3] || match == env->cr[CR_PID4]) { - prot &= PAGE_READ | PAGE_EXEC; - if (type == PAGE_WRITE) { - ret = EXCP_DMPI; - goto egress; - } - } - } - - /* No guest access type indicates a non-architectural access from - within QEMU. Bypass checks for access, D, B and T bits. */ + /* + * No guest access type indicates a non-architectural access from + * within QEMU. Bypass checks for access, D, B, P and T bits. + */ if (type == 0) { goto egress; } + /* access_id == 0 means public page and no check is performed */ + if (ent->access_id && MMU_IDX_TO_P(mmu_idx)) { + int access_prot = (hppa_is_pa20(env) + ? match_prot_id64(env, ent->access_id) + : match_prot_id32(env, ent->access_id)); + if (unlikely(!(type & access_prot))) { + /* Not allowed -- Inst/Data Memory Protection Id Fault. */ + ret = type & PAGE_EXEC ? EXCP_IMP : EXCP_DMPI; + goto egress; + } + /* Otherwise exclude permissions not allowed (i.e WD). */ + prot &= access_prot; + } + if (unlikely(!(prot & type))) { - /* The access isn't allowed -- Inst/Data Memory Protection Fault. */ + /* Not allowed -- Inst/Data Memory Access Rights Fault. */ ret = (type & PAGE_EXEC) ? EXCP_IMP : EXCP_DMAR; goto egress; } From ad1fdacd1b936557514dd72c2079a80be0c2dfb4 Mon Sep 17 00:00:00 2001 From: Sven Schnelle Date: Tue, 19 Mar 2024 17:19:19 +0100 Subject: [PATCH 7/9] target/hppa: exit tb on flush cache instructions When the guest modifies the tb it is currently executing from, it executes a fic instruction. Exit the tb on such instruction, otherwise we might execute stale code. Signed-off-by: Sven Schnelle Message-Id: <20240319161921.487080-5-svens@stackframe.org> Signed-off-by: Richard Henderson --- target/hppa/insns.decode | 6 +++--- target/hppa/translate.c | 7 +++++++ 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index 5412ff9836..f58455dfdb 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -144,9 +144,9 @@ getshadowregs 1111 1111 1111 1101 1110 1010 1101 0010 nop 000001 ----- ----- -- 11001010 0 ----- # fdc, disp nop_addrx 000001 ..... ..... -- 01001010 . ----- @addrx # fdc, index nop_addrx 000001 ..... ..... -- 01001011 . ----- @addrx # fdce -nop_addrx 000001 ..... ..... --- 0001010 . ----- @addrx # fic 0x0a -nop_addrx 000001 ..... ..... -- 01001111 . 00000 @addrx # fic 0x4f -nop_addrx 000001 ..... ..... --- 0001011 . ----- @addrx # fice +fic 000001 ..... ..... --- 0001010 . ----- @addrx # fic 0x0a +fic 000001 ..... ..... -- 01001111 . 00000 @addrx # fic 0x4f +fic 000001 ..... ..... --- 0001011 . ----- @addrx # fice nop_addrx 000001 ..... ..... -- 01001110 . 00000 @addrx # pdc probe 000001 b:5 ri:5 sp:2 imm:1 100011 write:1 0 t:5 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 29ef061baf..107d7f1a85 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2343,6 +2343,13 @@ static bool trans_nop_addrx(DisasContext *ctx, arg_ldst *a) return true; } +static bool trans_fic(DisasContext *ctx, arg_ldst *a) +{ + /* End TB for flush instruction cache, so we pick up new insns. */ + ctx->base.is_jmp = DISAS_IAQ_N_STALE; + return trans_nop_addrx(ctx, a); +} + static bool trans_probe(DisasContext *ctx, arg_probe *a) { TCGv_i64 dest, ofs; From b5e0b3a53c983c4a9620a44a6a557b389e589218 Mon Sep 17 00:00:00 2001 From: Sven Schnelle Date: Tue, 19 Mar 2024 17:19:20 +0100 Subject: [PATCH 8/9] target/hppa: mask privilege bits in mfia mfia should return only the iaoq bits without privilege bits. Fixes: 98a9cb792c8 ("target-hppa: Implement system and memory-management insns") Signed-off-by: Sven Schnelle Reviewed-by: Richard Henderson Reviewed-by: Helge Deller Message-Id: <20240319161921.487080-6-svens@stackframe.org> Signed-off-by: Richard Henderson --- target/hppa/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 107d7f1a85..19594f917e 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2011,7 +2011,7 @@ static bool trans_mfia(DisasContext *ctx, arg_mfia *a) { unsigned rt = a->t; TCGv_i64 tmp = dest_gpr(ctx, rt); - tcg_gen_movi_i64(tmp, ctx->iaoq_f); + tcg_gen_movi_i64(tmp, ctx->iaoq_f & ~3ULL); save_gpr(ctx, rt, tmp); cond_free(&ctx->null_cond); From 518d2f4300e5c50a3e6416fd46e58373781a5267 Mon Sep 17 00:00:00 2001 From: Sven Schnelle Date: Tue, 19 Mar 2024 17:19:21 +0100 Subject: [PATCH 9/9] target/hppa: fix do_stdby_e() stdby,e,m was writing data from the wrong half of the register into memory for cases 0-3. Fixes: 25460fc5a71 ("target/hppa: Implement STDBY") Signed-off-by: Sven Schnelle Reviewed-by: Richard Henderson Message-Id: <20240319161921.487080-7-svens@stackframe.org> Signed-off-by: Richard Henderson --- target/hppa/op_helper.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index 480fe80844..6cf49f33b7 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -281,17 +281,17 @@ static void do_stdby_e(CPUHPPAState *env, target_ulong addr, uint64_t val, case 3: /* The 3 byte store must appear atomic. */ if (parallel) { - atomic_store_mask32(env, addr - 3, val, 0xffffff00u, ra); + atomic_store_mask32(env, addr - 3, val >> 32, 0xffffff00u, ra); } else { - cpu_stw_data_ra(env, addr - 3, val >> 16, ra); - cpu_stb_data_ra(env, addr - 1, val >> 8, ra); + cpu_stw_data_ra(env, addr - 3, val >> 48, ra); + cpu_stb_data_ra(env, addr - 1, val >> 40, ra); } break; case 2: - cpu_stw_data_ra(env, addr - 2, val >> 16, ra); + cpu_stw_data_ra(env, addr - 2, val >> 48, ra); break; case 1: - cpu_stb_data_ra(env, addr - 1, val >> 24, ra); + cpu_stb_data_ra(env, addr - 1, val >> 56, ra); break; default: /* Nothing is stored, but protection is checked and the