kvm: sync linux headers
Import KVM_CLOCK_TSC_STABLE. Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com> Message-Id: <20161210172324.402794293@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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@ -245,6 +245,7 @@ struct input_mask {
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#define BUS_SPI 0x1C
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#define BUS_SPI 0x1C
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#define BUS_RMI 0x1D
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#define BUS_RMI 0x1D
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#define BUS_CEC 0x1E
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#define BUS_CEC 0x1E
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#define BUS_INTEL_ISHTP 0x1F
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/*
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/*
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* MT_TOOL types
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* MT_TOOL types
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@ -612,6 +612,8 @@
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*/
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*/
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#define PCI_EXP_DEVCAP2 36 /* Device Capabilities 2 */
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#define PCI_EXP_DEVCAP2 36 /* Device Capabilities 2 */
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#define PCI_EXP_DEVCAP2_ARI 0x00000020 /* Alternative Routing-ID */
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#define PCI_EXP_DEVCAP2_ARI 0x00000020 /* Alternative Routing-ID */
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#define PCI_EXP_DEVCAP2_ATOMIC_ROUTE 0x00000040 /* Atomic Op routing */
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#define PCI_EXP_DEVCAP2_ATOMIC_COMP64 0x00000100 /* Atomic 64-bit compare */
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#define PCI_EXP_DEVCAP2_LTR 0x00000800 /* Latency tolerance reporting */
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#define PCI_EXP_DEVCAP2_LTR 0x00000800 /* Latency tolerance reporting */
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#define PCI_EXP_DEVCAP2_OBFF_MASK 0x000c0000 /* OBFF support mechanism */
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#define PCI_EXP_DEVCAP2_OBFF_MASK 0x000c0000 /* OBFF support mechanism */
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#define PCI_EXP_DEVCAP2_OBFF_MSG 0x00040000 /* New message signaling */
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#define PCI_EXP_DEVCAP2_OBFF_MSG 0x00040000 /* New message signaling */
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@ -619,6 +621,7 @@
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#define PCI_EXP_DEVCTL2 40 /* Device Control 2 */
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#define PCI_EXP_DEVCTL2 40 /* Device Control 2 */
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#define PCI_EXP_DEVCTL2_COMP_TIMEOUT 0x000f /* Completion Timeout Value */
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#define PCI_EXP_DEVCTL2_COMP_TIMEOUT 0x000f /* Completion Timeout Value */
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#define PCI_EXP_DEVCTL2_ARI 0x0020 /* Alternative Routing-ID */
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#define PCI_EXP_DEVCTL2_ARI 0x0020 /* Alternative Routing-ID */
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#define PCI_EXP_DEVCTL2_ATOMIC_REQ 0x0040 /* Set Atomic requests */
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#define PCI_EXP_DEVCTL2_IDO_REQ_EN 0x0100 /* Allow IDO for requests */
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#define PCI_EXP_DEVCTL2_IDO_REQ_EN 0x0100 /* Allow IDO for requests */
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#define PCI_EXP_DEVCTL2_IDO_CMP_EN 0x0200 /* Allow IDO for completions */
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#define PCI_EXP_DEVCTL2_IDO_CMP_EN 0x0200 /* Allow IDO for completions */
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#define PCI_EXP_DEVCTL2_LTR_EN 0x0400 /* Enable LTR mechanism */
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#define PCI_EXP_DEVCTL2_LTR_EN 0x0400 /* Enable LTR mechanism */
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@ -671,7 +674,8 @@
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#define PCI_EXT_CAP_ID_PMUX 0x1A /* Protocol Multiplexing */
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#define PCI_EXT_CAP_ID_PMUX 0x1A /* Protocol Multiplexing */
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#define PCI_EXT_CAP_ID_PASID 0x1B /* Process Address Space ID */
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#define PCI_EXT_CAP_ID_PASID 0x1B /* Process Address Space ID */
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#define PCI_EXT_CAP_ID_DPC 0x1D /* Downstream Port Containment */
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#define PCI_EXT_CAP_ID_DPC 0x1D /* Downstream Port Containment */
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#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_DPC
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#define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */
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#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PTM
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#define PCI_EXT_CAP_DSN_SIZEOF 12
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#define PCI_EXT_CAP_DSN_SIZEOF 12
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#define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40
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#define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40
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@ -964,4 +968,13 @@
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#define PCI_EXP_DPC_SOURCE_ID 10 /* DPC Source Identifier */
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#define PCI_EXP_DPC_SOURCE_ID 10 /* DPC Source Identifier */
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/* Precision Time Measurement */
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#define PCI_PTM_CAP 0x04 /* PTM Capability */
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#define PCI_PTM_CAP_REQ 0x00000001 /* Requester capable */
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#define PCI_PTM_CAP_ROOT 0x00000004 /* Root capable */
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#define PCI_PTM_GRANULARITY_MASK 0x0000FF00 /* Clock granularity */
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#define PCI_PTM_CTRL 0x08 /* PTM Control */
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#define PCI_PTM_CTRL_ENABLE 0x00000001 /* PTM enable */
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#define PCI_PTM_CTRL_ROOT 0x00000002 /* Root select */
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#endif /* LINUX_PCI_REGS_H */
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#endif /* LINUX_PCI_REGS_H */
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@ -84,6 +84,13 @@ struct kvm_regs {
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#define KVM_VGIC_V2_DIST_SIZE 0x1000
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#define KVM_VGIC_V2_DIST_SIZE 0x1000
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#define KVM_VGIC_V2_CPU_SIZE 0x2000
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#define KVM_VGIC_V2_CPU_SIZE 0x2000
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/* Supported VGICv3 address types */
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#define KVM_VGIC_V3_ADDR_TYPE_DIST 2
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#define KVM_VGIC_V3_ADDR_TYPE_REDIST 3
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#define KVM_VGIC_V3_DIST_SIZE SZ_64K
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#define KVM_VGIC_V3_REDIST_SIZE (2 * SZ_64K)
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#define KVM_ARM_VCPU_POWER_OFF 0 /* CPU is started in OFF state */
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#define KVM_ARM_VCPU_POWER_OFF 0 /* CPU is started in OFF state */
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#define KVM_ARM_VCPU_PSCI_0_2 1 /* CPU uses PSCI v0.2 */
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#define KVM_ARM_VCPU_PSCI_0_2 1 /* CPU uses PSCI v0.2 */
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@ -377,5 +377,8 @@
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#define __NR_copy_file_range 377
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#define __NR_copy_file_range 377
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#define __NR_preadv2 378
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#define __NR_preadv2 378
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#define __NR_pwritev2 379
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#define __NR_pwritev2 379
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#define __NR_pkey_mprotect 380
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#define __NR_pkey_alloc 381
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#define __NR_pkey_free 382
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#endif /* _ASM_X86_UNISTD_32_H */
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#endif /* _ASM_X86_UNISTD_32_H */
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@ -330,5 +330,8 @@
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#define __NR_copy_file_range 326
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#define __NR_copy_file_range 326
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#define __NR_preadv2 327
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#define __NR_preadv2 327
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#define __NR_pwritev2 328
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#define __NR_pwritev2 328
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#define __NR_pkey_mprotect 329
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#define __NR_pkey_alloc 330
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#define __NR_pkey_free 331
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#endif /* _ASM_X86_UNISTD_64_H */
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#endif /* _ASM_X86_UNISTD_64_H */
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@ -283,6 +283,9 @@
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#define __NR_membarrier (__X32_SYSCALL_BIT + 324)
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#define __NR_membarrier (__X32_SYSCALL_BIT + 324)
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#define __NR_mlock2 (__X32_SYSCALL_BIT + 325)
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#define __NR_mlock2 (__X32_SYSCALL_BIT + 325)
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#define __NR_copy_file_range (__X32_SYSCALL_BIT + 326)
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#define __NR_copy_file_range (__X32_SYSCALL_BIT + 326)
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#define __NR_pkey_mprotect (__X32_SYSCALL_BIT + 329)
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#define __NR_pkey_alloc (__X32_SYSCALL_BIT + 330)
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#define __NR_pkey_free (__X32_SYSCALL_BIT + 331)
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#define __NR_rt_sigaction (__X32_SYSCALL_BIT + 512)
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#define __NR_rt_sigaction (__X32_SYSCALL_BIT + 512)
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#define __NR_rt_sigreturn (__X32_SYSCALL_BIT + 513)
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#define __NR_rt_sigreturn (__X32_SYSCALL_BIT + 513)
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#define __NR_ioctl (__X32_SYSCALL_BIT + 514)
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#define __NR_ioctl (__X32_SYSCALL_BIT + 514)
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@ -972,12 +972,19 @@ struct kvm_irqfd {
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__u8 pad[16];
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__u8 pad[16];
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};
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};
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/* For KVM_CAP_ADJUST_CLOCK */
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/* Do not use 1, KVM_CHECK_EXTENSION returned it before we had flags. */
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#define KVM_CLOCK_TSC_STABLE 2
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struct kvm_clock_data {
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struct kvm_clock_data {
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__u64 clock;
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__u64 clock;
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__u32 flags;
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__u32 flags;
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__u32 pad[9];
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__u32 pad[9];
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};
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};
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/* For KVM_CAP_SW_TLB */
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#define KVM_MMU_FSL_BOOKE_NOHV 0
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#define KVM_MMU_FSL_BOOKE_NOHV 0
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#define KVM_MMU_FSL_BOOKE_HV 1
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#define KVM_MMU_FSL_BOOKE_HV 1
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