tcg-i386: Always implement 32-bit multiword ops
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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@ -1922,13 +1922,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
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tcg_out_qemu_st(s, args, 3);
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break;
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#if TCG_TARGET_REG_BITS == 32
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case INDEX_op_brcond2_i32:
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tcg_out_brcond2(s, args, const_args, 0);
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break;
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case INDEX_op_setcond2_i32:
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tcg_out_setcond2(s, args, const_args);
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break;
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case INDEX_op_mulu2_i32:
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tcg_out_modrm(s, OPC_GRP3_Ev, EXT3_MUL, args[3]);
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break;
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@ -1956,6 +1949,14 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
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tgen_arithr(s, ARITH_SBB, args[1], args[5]);
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}
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break;
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#if TCG_TARGET_REG_BITS == 32
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case INDEX_op_brcond2_i32:
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tcg_out_brcond2(s, args, const_args, 0);
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break;
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case INDEX_op_setcond2_i32:
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tcg_out_setcond2(s, args, const_args);
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break;
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#else /* TCG_TARGET_REG_BITS == 64 */
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case INDEX_op_movi_i64:
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tcg_out_movi(s, TCG_TYPE_I64, args[0], args[1]);
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@ -2078,10 +2079,11 @@ static const TCGTargetOpDef x86_op_defs[] = {
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{ INDEX_op_movcond_i32, { "r", "r", "ri", "r", "0" } },
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#endif
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#if TCG_TARGET_REG_BITS == 32
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{ INDEX_op_mulu2_i32, { "a", "d", "a", "r" } },
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{ INDEX_op_add2_i32, { "r", "r", "0", "1", "ri", "ri" } },
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{ INDEX_op_sub2_i32, { "r", "r", "0", "1", "ri", "ri" } },
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#if TCG_TARGET_REG_BITS == 32
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{ INDEX_op_brcond2_i32, { "r", "r", "ri", "ri" } },
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{ INDEX_op_setcond2_i32, { "r", "r", "r", "ri", "ri" } },
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#else
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@ -92,6 +92,9 @@ typedef enum {
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#define TCG_TARGET_HAS_nor_i32 0
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#define TCG_TARGET_HAS_deposit_i32 1
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#define TCG_TARGET_HAS_movcond_i32 1
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#define TCG_TARGET_HAS_add2_i32 1
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#define TCG_TARGET_HAS_sub2_i32 1
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#define TCG_TARGET_HAS_mulu2_i32 1
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#if TCG_TARGET_REG_BITS == 64
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#define TCG_TARGET_HAS_div2_i64 1
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@ -114,10 +117,6 @@ typedef enum {
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#define TCG_TARGET_HAS_nor_i64 0
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#define TCG_TARGET_HAS_deposit_i64 1
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#define TCG_TARGET_HAS_movcond_i64 1
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#define TCG_TARGET_HAS_add2_i32 0
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#define TCG_TARGET_HAS_sub2_i32 0
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#define TCG_TARGET_HAS_mulu2_i32 0
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#endif
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#define TCG_TARGET_deposit_i32_valid(ofs, len) \
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