target/ppc: Use probe_access for LSW, STSW
Use a minimum number of mmu lookups for the contiguous bytes that are accessed. If the lookup succeeds, we can finish the operation with host addresses only. Reported-by: Howard Spoelstra <hsp.cat7@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20200129235040.24022-2-richard.henderson@linaro.org> Tested-by: Howard Spoelstra <hsp.cat7@gmail.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -56,6 +56,32 @@ static inline target_ulong addr_add(CPUPPCState *env, target_ulong addr,
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}
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}
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static void *probe_contiguous(CPUPPCState *env, target_ulong addr, uint32_t nb,
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MMUAccessType access_type, int mmu_idx,
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uintptr_t raddr)
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{
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void *host1, *host2;
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uint32_t nb_pg1, nb_pg2;
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nb_pg1 = -(addr | TARGET_PAGE_MASK);
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if (likely(nb <= nb_pg1)) {
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/* The entire operation is on a single page. */
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return probe_access(env, addr, nb, access_type, mmu_idx, raddr);
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}
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/* The operation spans two pages. */
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nb_pg2 = nb - nb_pg1;
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host1 = probe_access(env, addr, nb_pg1, access_type, mmu_idx, raddr);
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addr = addr_add(env, addr, nb_pg1);
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host2 = probe_access(env, addr, nb_pg2, access_type, mmu_idx, raddr);
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/* If the two host pages are contiguous, optimize. */
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if (host2 == host1 + nb_pg1) {
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return host1;
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}
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return NULL;
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}
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void helper_lmw(CPUPPCState *env, target_ulong addr, uint32_t reg)
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{
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for (; reg < 32; reg++) {
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@ -84,23 +110,65 @@ void helper_stmw(CPUPPCState *env, target_ulong addr, uint32_t reg)
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static void do_lsw(CPUPPCState *env, target_ulong addr, uint32_t nb,
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uint32_t reg, uintptr_t raddr)
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{
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int sh;
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int mmu_idx;
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void *host;
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uint32_t val;
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if (unlikely(nb == 0)) {
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return;
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}
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mmu_idx = cpu_mmu_index(env, false);
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host = probe_contiguous(env, addr, nb, MMU_DATA_LOAD, mmu_idx, raddr);
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if (likely(host)) {
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/* Fast path -- the entire operation is in RAM at host. */
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for (; nb > 3; nb -= 4) {
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env->gpr[reg] = cpu_ldl_data_ra(env, addr, raddr);
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env->gpr[reg] = (uint32_t)ldl_be_p(host);
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reg = (reg + 1) % 32;
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host += 4;
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}
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switch (nb) {
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default:
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return;
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case 1:
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val = ldub_p(host) << 24;
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break;
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case 2:
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val = lduw_be_p(host) << 16;
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break;
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case 3:
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val = (lduw_be_p(host) << 16) | (ldub_p(host + 2) << 8);
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break;
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}
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} else {
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/* Slow path -- at least some of the operation requires i/o. */
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for (; nb > 3; nb -= 4) {
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env->gpr[reg] = cpu_ldl_mmuidx_ra(env, addr, mmu_idx, raddr);
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reg = (reg + 1) % 32;
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addr = addr_add(env, addr, 4);
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}
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if (unlikely(nb > 0)) {
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env->gpr[reg] = 0;
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for (sh = 24; nb > 0; nb--, sh -= 8) {
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env->gpr[reg] |= cpu_ldub_data_ra(env, addr, raddr) << sh;
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addr = addr_add(env, addr, 1);
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switch (nb) {
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default:
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return;
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case 1:
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val = cpu_ldub_mmuidx_ra(env, addr, mmu_idx, raddr) << 24;
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break;
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case 2:
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val = cpu_lduw_mmuidx_ra(env, addr, mmu_idx, raddr) << 16;
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break;
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case 3:
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val = cpu_lduw_mmuidx_ra(env, addr, mmu_idx, raddr) << 16;
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addr = addr_add(env, addr, 2);
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val |= cpu_ldub_mmuidx_ra(env, addr, mmu_idx, raddr) << 8;
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break;
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}
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}
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env->gpr[reg] = val;
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}
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void helper_lsw(CPUPPCState *env, target_ulong addr, uint32_t nb, uint32_t reg)
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void helper_lsw(CPUPPCState *env, target_ulong addr,
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uint32_t nb, uint32_t reg)
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{
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do_lsw(env, addr, nb, reg, GETPC());
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}
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@ -130,17 +198,57 @@ void helper_lswx(CPUPPCState *env, target_ulong addr, uint32_t reg,
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void helper_stsw(CPUPPCState *env, target_ulong addr, uint32_t nb,
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uint32_t reg)
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{
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int sh;
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uintptr_t raddr = GETPC();
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int mmu_idx;
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void *host;
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uint32_t val;
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if (unlikely(nb == 0)) {
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return;
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}
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mmu_idx = cpu_mmu_index(env, false);
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host = probe_contiguous(env, addr, nb, MMU_DATA_STORE, mmu_idx, raddr);
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if (likely(host)) {
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/* Fast path -- the entire operation is in RAM at host. */
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for (; nb > 3; nb -= 4) {
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cpu_stl_data_ra(env, addr, env->gpr[reg], GETPC());
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stl_be_p(host, env->gpr[reg]);
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reg = (reg + 1) % 32;
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host += 4;
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}
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val = env->gpr[reg];
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switch (nb) {
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case 1:
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stb_p(host, val >> 24);
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break;
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case 2:
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stw_be_p(host, val >> 16);
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break;
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case 3:
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stw_be_p(host, val >> 16);
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stb_p(host + 2, val >> 8);
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break;
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}
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} else {
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for (; nb > 3; nb -= 4) {
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cpu_stl_mmuidx_ra(env, addr, env->gpr[reg], mmu_idx, raddr);
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reg = (reg + 1) % 32;
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addr = addr_add(env, addr, 4);
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}
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if (unlikely(nb > 0)) {
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for (sh = 24; nb > 0; nb--, sh -= 8) {
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cpu_stb_data_ra(env, addr, (env->gpr[reg] >> sh) & 0xFF, GETPC());
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addr = addr_add(env, addr, 1);
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val = env->gpr[reg];
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switch (nb) {
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case 1:
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cpu_stb_mmuidx_ra(env, addr, val >> 24, mmu_idx, raddr);
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break;
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case 2:
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cpu_stw_mmuidx_ra(env, addr, val >> 16, mmu_idx, raddr);
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break;
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case 3:
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cpu_stw_mmuidx_ra(env, addr, val >> 16, mmu_idx, raddr);
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addr = addr_add(env, addr, 2);
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cpu_stb_mmuidx_ra(env, addr, val >> 8, mmu_idx, raddr);
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break;
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}
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}
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}
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