From 1a03362b14affa4d8ddede55df6e21d7a07b87c2 Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Wed, 26 Feb 2020 12:43:52 -0800 Subject: [PATCH 1/2] target/xtensa: fix pasto in pfwait.r opcode name Core xtensa opcode table has pfwait.o instead of pfwait.r. Fix that. Fixes: c884400f2988 ("target/xtensa: implement block prefetch option opcodes") Signed-off-by: Max Filippov --- target/xtensa/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 37f65b1f03..1010c1ca87 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -3746,7 +3746,7 @@ static const XtensaOpcodeOps core_ops[] = { .name = "pfwait.a", .translate = translate_nop, }, { - .name = "pfwait.o", + .name = "pfwait.r", .translate = translate_nop, }, { .name = "pitlb", From fde557ad25ff3370ef1dd0587d299a86e060bb23 Mon Sep 17 00:00:00 2001 From: Max Filippov Date: Mon, 6 Apr 2020 20:59:54 -0700 Subject: [PATCH 2/2] target/xtensa: statically allocate xtensa_insnbufs in DisasContext Rather than dynamically allocate, and risk failing to free when we longjmp out of the translator, allocate the maximum buffer size based on the maximum supported instruction length. Suggested-by: Richard Henderson Signed-off-by: Max Filippov Reviewed-by: Richard Henderson Tested-by: Richard Henderson --- target/xtensa/cpu.h | 3 +++ target/xtensa/helper.c | 1 + target/xtensa/translate.c | 18 ++---------------- 3 files changed, 6 insertions(+), 16 deletions(-) diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index c0d69fad96..7a46dccbe1 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -213,6 +213,9 @@ enum { #define MEMCTL_IL0EN 0x1 #define MAX_INSN_LENGTH 64 +#define MAX_INSNBUF_LENGTH \ + ((MAX_INSN_LENGTH + sizeof(xtensa_insnbuf_word) - 1) / \ + sizeof(xtensa_insnbuf_word)) #define MAX_INSN_SLOTS 32 #define MAX_OPCODE_ARGS 16 #define MAX_NAREG 64 diff --git a/target/xtensa/helper.c b/target/xtensa/helper.c index 376a61f339..7073381f03 100644 --- a/target/xtensa/helper.c +++ b/target/xtensa/helper.c @@ -96,6 +96,7 @@ static void init_libisa(XtensaConfig *config) config->isa = xtensa_isa_init(config->isa_internal, NULL, NULL); assert(xtensa_isa_maxlength(config->isa) <= MAX_INSN_LENGTH); + assert(xtensa_insnbuf_size(config->isa) <= MAX_INSNBUF_LENGTH); opcodes = xtensa_isa_num_opcodes(config->isa); formats = xtensa_isa_num_formats(config->isa); regfiles = xtensa_isa_num_regfiles(config->isa); diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 1010c1ca87..e0beaf7abb 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -72,8 +72,8 @@ struct DisasContext { unsigned cpenable; uint32_t op_flags; - xtensa_insnbuf insnbuf; - xtensa_insnbuf slotbuf; + xtensa_insnbuf_word insnbuf[MAX_INSNBUF_LENGTH]; + xtensa_insnbuf_word slotbuf[MAX_INSNBUF_LENGTH]; }; static TCGv_i32 cpu_pc; @@ -1173,16 +1173,6 @@ static void xtensa_tr_init_disas_context(DisasContextBase *dcbase, dc->cwoe = tb_flags & XTENSA_TBFLAG_CWOE; dc->callinc = ((tb_flags & XTENSA_TBFLAG_CALLINC_MASK) >> XTENSA_TBFLAG_CALLINC_SHIFT); - - /* - * FIXME: This will leak when a failed instruction load or similar - * event causes us to longjump out of the translation loop and - * hence not clean-up in xtensa_tr_tb_stop - */ - if (dc->config->isa) { - dc->insnbuf = xtensa_insnbuf_alloc(dc->config->isa); - dc->slotbuf = xtensa_insnbuf_alloc(dc->config->isa); - } init_sar_tracker(dc); } @@ -1272,10 +1262,6 @@ static void xtensa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) DisasContext *dc = container_of(dcbase, DisasContext, base); reset_sar_tracker(dc); - if (dc->config->isa) { - xtensa_insnbuf_free(dc->config->isa, dc->insnbuf); - xtensa_insnbuf_free(dc->config->isa, dc->slotbuf); - } if (dc->icount) { tcg_temp_free(dc->next_icount); }