From bae4b15aa4fa56815e08cee395486a1c990caa99 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Wed, 16 Dec 2020 12:29:34 +0100 Subject: [PATCH] target/mips/mips-defs: Rename ISA_MIPS32R3 as ISA_MIPS_R3 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The MIPS ISA release 3 is common to 32/64-bit CPUs. To avoid holes in the insn_flags type, update the definition with the next available bit. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20210104221154.3127610-14-f4bug@amsat.org> --- target/mips/mips-defs.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/mips/mips-defs.h b/target/mips/mips-defs.h index d1eeb69dfd..12ff2b3280 100644 --- a/target/mips/mips-defs.h +++ b/target/mips/mips-defs.h @@ -18,7 +18,7 @@ #define ISA_MIPS5 0x0000000000000010ULL #define ISA_MIPS_R1 0x0000000000000020ULL #define ISA_MIPS_R2 0x0000000000000040ULL -#define ISA_MIPS32R3 0x0000000000000200ULL +#define ISA_MIPS_R3 0x0000000000000080ULL #define ISA_MIPS32R5 0x0000000000000800ULL #define ISA_MIPS32R6 0x0000000000002000ULL #define ISA_NANOMIPS32 0x0000000000008000ULL @@ -77,7 +77,7 @@ #define CPU_MIPS64R2 (CPU_MIPS64R1 | CPU_MIPS32R2) /* MIPS Technologies "Release 3" */ -#define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS32R3) +#define CPU_MIPS32R3 (CPU_MIPS32R2 | ISA_MIPS_R3) #define CPU_MIPS64R3 (CPU_MIPS64R2 | CPU_MIPS32R3) /* MIPS Technologies "Release 5" */