target/arm: Create ARMVAParameters and helpers
Split out functions to extract the virtual address parameters. Let the functions choose T0 or T1 address space half, if present. Extract (most of) the control bits that vary between EL or Tx. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20190108223129.5570-19-richard.henderson@linaro.org [PMM: fixed minor checkpatch comment nits] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson
Peter Maydell
parent
64be86ab1b
commit
ba97be9f4a
@ -9744,6 +9744,124 @@ static uint8_t convert_stage2_attrs(CPUARMState *env, uint8_t s2attrs)
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return (hiattr << 6) | (hihint << 4) | (loattr << 2) | lohint;
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}
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static ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
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ARMMMUIdx mmu_idx, bool data)
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{
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uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr;
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uint32_t el = regime_el(env, mmu_idx);
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bool tbi, epd, hpd, using16k, using64k;
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int select, tsz;
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/*
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* Bit 55 is always between the two regions, and is canonical for
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* determining if address tagging is enabled.
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*/
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select = extract64(va, 55, 1);
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if (el > 1) {
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tsz = extract32(tcr, 0, 6);
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using64k = extract32(tcr, 14, 1);
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using16k = extract32(tcr, 15, 1);
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if (mmu_idx == ARMMMUIdx_S2NS) {
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/* VTCR_EL2 */
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tbi = hpd = false;
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} else {
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tbi = extract32(tcr, 20, 1);
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hpd = extract32(tcr, 24, 1);
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}
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epd = false;
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} else if (!select) {
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tsz = extract32(tcr, 0, 6);
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epd = extract32(tcr, 7, 1);
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using64k = extract32(tcr, 14, 1);
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using16k = extract32(tcr, 15, 1);
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tbi = extract64(tcr, 37, 1);
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hpd = extract64(tcr, 41, 1);
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} else {
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int tg = extract32(tcr, 30, 2);
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using16k = tg == 1;
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using64k = tg == 3;
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tsz = extract32(tcr, 16, 6);
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epd = extract32(tcr, 23, 1);
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tbi = extract64(tcr, 38, 1);
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hpd = extract64(tcr, 42, 1);
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}
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tsz = MIN(tsz, 39); /* TODO: ARMv8.4-TTST */
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tsz = MAX(tsz, 16); /* TODO: ARMv8.2-LVA */
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return (ARMVAParameters) {
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.tsz = tsz,
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.select = select,
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.tbi = tbi,
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.epd = epd,
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.hpd = hpd,
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.using16k = using16k,
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.using64k = using64k,
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};
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}
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static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va,
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ARMMMUIdx mmu_idx)
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{
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uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr;
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uint32_t el = regime_el(env, mmu_idx);
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int select, tsz;
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bool epd, hpd;
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if (mmu_idx == ARMMMUIdx_S2NS) {
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/* VTCR */
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bool sext = extract32(tcr, 4, 1);
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bool sign = extract32(tcr, 3, 1);
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/*
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* If the sign-extend bit is not the same as t0sz[3], the result
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* is unpredictable. Flag this as a guest error.
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*/
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if (sign != sext) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"AArch32: VTCR.S / VTCR.T0SZ[3] mismatch\n");
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}
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tsz = sextract32(tcr, 0, 4) + 8;
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select = 0;
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hpd = false;
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epd = false;
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} else if (el == 2) {
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/* HTCR */
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tsz = extract32(tcr, 0, 3);
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select = 0;
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hpd = extract64(tcr, 24, 1);
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epd = false;
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} else {
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int t0sz = extract32(tcr, 0, 3);
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int t1sz = extract32(tcr, 16, 3);
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if (t1sz == 0) {
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select = va > (0xffffffffu >> t0sz);
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} else {
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/* Note that we will detect errors later. */
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select = va >= ~(0xffffffffu >> t1sz);
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}
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if (!select) {
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tsz = t0sz;
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epd = extract32(tcr, 7, 1);
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hpd = extract64(tcr, 41, 1);
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} else {
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tsz = t1sz;
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epd = extract32(tcr, 23, 1);
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hpd = extract64(tcr, 42, 1);
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}
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/* For aarch32, hpd0 is not enabled without t2e as well. */
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hpd &= extract32(tcr, 6, 1);
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}
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return (ARMVAParameters) {
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.tsz = tsz,
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.select = select,
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.epd = epd,
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.hpd = hpd,
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};
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}
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static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
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MMUAccessType access_type, ARMMMUIdx mmu_idx,
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hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,
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@ -9755,26 +9873,20 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
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/* Read an LPAE long-descriptor translation table. */
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ARMFaultType fault_type = ARMFault_Translation;
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uint32_t level;
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uint32_t epd = 0;
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int32_t t0sz, t1sz;
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uint32_t tg;
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ARMVAParameters param;
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uint64_t ttbr;
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int ttbr_select;
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hwaddr descaddr, indexmask, indexmask_grainsize;
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uint32_t tableattrs;
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target_ulong page_size;
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target_ulong page_size, top_bits;
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uint32_t attrs;
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int32_t stride = 9;
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int32_t addrsize;
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int inputsize;
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int32_t tbi = 0;
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int32_t stride;
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int addrsize, inputsize;
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TCR *tcr = regime_tcr(env, mmu_idx);
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int ap, ns, xn, pxn;
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uint32_t el = regime_el(env, mmu_idx);
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bool ttbr1_valid = true;
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bool ttbr1_valid;
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uint64_t descaddrmask;
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bool aarch64 = arm_el_is_aa64(env, el);
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bool hpd = false;
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/* TODO:
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* This code does not handle the different format TCR for VTCR_EL2.
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@ -9783,91 +9895,44 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
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* support for those page table walks.
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*/
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if (aarch64) {
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param = aa64_va_parameters(env, address, mmu_idx,
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access_type != MMU_INST_FETCH);
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level = 0;
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addrsize = 64;
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if (el > 1) {
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if (mmu_idx != ARMMMUIdx_S2NS) {
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tbi = extract64(tcr->raw_tcr, 20, 1);
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}
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} else {
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if (extract64(address, 55, 1)) {
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tbi = extract64(tcr->raw_tcr, 38, 1);
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} else {
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tbi = extract64(tcr->raw_tcr, 37, 1);
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}
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}
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tbi *= 8;
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/* If we are in 64-bit EL2 or EL3 then there is no TTBR1, so mark it
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* invalid.
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*/
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if (el > 1) {
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ttbr1_valid = false;
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}
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ttbr1_valid = (el < 2);
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addrsize = 64 - 8 * param.tbi;
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inputsize = 64 - param.tsz;
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} else {
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param = aa32_va_parameters(env, address, mmu_idx);
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level = 1;
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addrsize = 32;
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/* There is no TTBR1 for EL2 */
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if (el == 2) {
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ttbr1_valid = false;
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}
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ttbr1_valid = (el != 2);
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addrsize = (mmu_idx == ARMMMUIdx_S2NS ? 40 : 32);
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inputsize = addrsize - param.tsz;
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}
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/* Determine whether this address is in the region controlled by
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* TTBR0 or TTBR1 (or if it is in neither region and should fault).
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* This is a Non-secure PL0/1 stage 1 translation, so controlled by
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* TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
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/*
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* We determined the region when collecting the parameters, but we
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* have not yet validated that the address is valid for the region.
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* Extract the top bits and verify that they all match select.
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*/
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if (aarch64) {
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/* AArch64 translation. */
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t0sz = extract32(tcr->raw_tcr, 0, 6);
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t0sz = MIN(t0sz, 39);
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t0sz = MAX(t0sz, 16);
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} else if (mmu_idx != ARMMMUIdx_S2NS) {
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/* AArch32 stage 1 translation. */
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t0sz = extract32(tcr->raw_tcr, 0, 3);
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} else {
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/* AArch32 stage 2 translation. */
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bool sext = extract32(tcr->raw_tcr, 4, 1);
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bool sign = extract32(tcr->raw_tcr, 3, 1);
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/* Address size is 40-bit for a stage 2 translation,
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* and t0sz can be negative (from -8 to 7),
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* so we need to adjust it to use the TTBR selecting logic below.
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*/
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addrsize = 40;
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t0sz = sextract32(tcr->raw_tcr, 0, 4) + 8;
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/* If the sign-extend bit is not the same as t0sz[3], the result
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* is unpredictable. Flag this as a guest error. */
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if (sign != sext) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"AArch32: VTCR.S / VTCR.T0SZ[3] mismatch\n");
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}
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}
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t1sz = extract32(tcr->raw_tcr, 16, 6);
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if (aarch64) {
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t1sz = MIN(t1sz, 39);
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t1sz = MAX(t1sz, 16);
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}
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if (t0sz && !extract64(address, addrsize - t0sz, t0sz - tbi)) {
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/* there is a ttbr0 region and we are in it (high bits all zero) */
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ttbr_select = 0;
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} else if (ttbr1_valid && t1sz &&
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!extract64(~address, addrsize - t1sz, t1sz - tbi)) {
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/* there is a ttbr1 region and we are in it (high bits all one) */
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ttbr_select = 1;
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} else if (!t0sz) {
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/* ttbr0 region is "everything not in the ttbr1 region" */
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ttbr_select = 0;
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} else if (!t1sz && ttbr1_valid) {
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/* ttbr1 region is "everything not in the ttbr0 region" */
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ttbr_select = 1;
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} else {
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/* in the gap between the two regions, this is a Translation fault */
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top_bits = sextract64(address, inputsize, addrsize - inputsize);
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if (-top_bits != param.select || (param.select && !ttbr1_valid)) {
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/* In the gap between the two regions, this is a Translation fault */
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fault_type = ARMFault_Translation;
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goto do_fault;
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}
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if (param.using64k) {
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stride = 13;
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} else if (param.using16k) {
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stride = 11;
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} else {
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stride = 9;
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}
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/* Note that QEMU ignores shareability and cacheability attributes,
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* so we don't need to do anything with the SH, ORGN, IRGN fields
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* in the TTBCR. Similarly, TTBCR:A1 selects whether we get the
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@ -9875,56 +9940,13 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
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* implement any ASID-like capability so we can ignore it (instead
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* we will always flush the TLB any time the ASID is changed).
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*/
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if (ttbr_select == 0) {
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ttbr = regime_ttbr(env, mmu_idx, 0);
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if (el < 2) {
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epd = extract32(tcr->raw_tcr, 7, 1);
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}
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inputsize = addrsize - t0sz;
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tg = extract32(tcr->raw_tcr, 14, 2);
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if (tg == 1) { /* 64KB pages */
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stride = 13;
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}
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if (tg == 2) { /* 16KB pages */
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stride = 11;
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}
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if (aarch64 && el > 1) {
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hpd = extract64(tcr->raw_tcr, 24, 1);
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} else {
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hpd = extract64(tcr->raw_tcr, 41, 1);
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}
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if (!aarch64) {
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/* For aarch32, hpd0 is not enabled without t2e as well. */
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hpd &= extract64(tcr->raw_tcr, 6, 1);
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}
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} else {
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/* We should only be here if TTBR1 is valid */
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assert(ttbr1_valid);
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ttbr = regime_ttbr(env, mmu_idx, 1);
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epd = extract32(tcr->raw_tcr, 23, 1);
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inputsize = addrsize - t1sz;
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tg = extract32(tcr->raw_tcr, 30, 2);
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if (tg == 3) { /* 64KB pages */
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stride = 13;
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}
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if (tg == 1) { /* 16KB pages */
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stride = 11;
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}
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hpd = extract64(tcr->raw_tcr, 42, 1);
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if (!aarch64) {
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/* For aarch32, hpd1 is not enabled without t2e as well. */
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hpd &= extract64(tcr->raw_tcr, 6, 1);
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}
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}
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ttbr = regime_ttbr(env, mmu_idx, param.select);
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/* Here we should have set up all the parameters for the translation:
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* inputsize, ttbr, epd, stride, tbi
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*/
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if (epd) {
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if (param.epd) {
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/* Translation table walk disabled => Translation fault on TLB miss
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* Note: This is always 0 on 64-bit EL2 and EL3.
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*/
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@ -10037,7 +10059,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
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}
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/* Merge in attributes from table descriptors */
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attrs |= nstable << 3; /* NS */
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if (hpd) {
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if (param.hpd) {
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/* HPD disables all the table attributes except NSTable. */
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break;
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}
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@ -942,4 +942,18 @@ static inline ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env)
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ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env);
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#endif
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/*
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* Parameters of a given virtual address, as extracted from the
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* translation control register (TCR) for a given regime.
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*/
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typedef struct ARMVAParameters {
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unsigned tsz : 8;
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unsigned select : 1;
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bool tbi : 1;
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bool epd : 1;
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bool hpd : 1;
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bool using16k : 1;
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bool using64k : 1;
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} ARMVAParameters;
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#endif
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