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target/sparc: Use i128 for Fdmulq

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Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20231103173841.33651-14-richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-11-03 10:38:32 -07:00
parent fdc50716a0
commit ba21dc991b
3 changed files with 9 additions and 16 deletions
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8
target/sparc/fop_helper.c
View File

@ -129,11 +129,11 @@ float64 helper_fsmuld(CPUSPARCState *env, float32 src1, float32 src2)
&env->fp_status);
}
void helper_fdmulq(CPUSPARCState *env, float64 src1, float64 src2)
Int128 helper_fdmulq(CPUSPARCState *env, float64 src1, float64 src2)
{
QT0 = float128_mul(float64_to_float128(src1, &env->fp_status),
float64_to_float128(src2, &env->fp_status),
&env->fp_status);
return f128_ret(float128_mul(float64_to_float128(src1, &env->fp_status),
float64_to_float128(src2, &env->fp_status),
&env->fp_status));
}
/* Integer to float conversion. */

2
target/sparc/helper.h
View File

@ -84,7 +84,7 @@ DEF_HELPER_FLAGS_3(fmuls, TCG_CALL_NO_RWG, f32, env, f32, f32)
DEF_HELPER_FLAGS_3(fdivs, TCG_CALL_NO_RWG, f32, env, f32, f32)
DEF_HELPER_FLAGS_3(fsmuld, TCG_CALL_NO_RWG, f64, env, f32, f32)
DEF_HELPER_FLAGS_3(fdmulq, TCG_CALL_NO_RWG, void, env, f64, f64)
DEF_HELPER_FLAGS_3(fdmulq, TCG_CALL_NO_RWG, i128, env, f64, f64)
DEF_HELPER_FLAGS_2(fitod, TCG_CALL_NO_RWG_SE, f64, env, s32)
DEF_HELPER_FLAGS_2(fitoq, TCG_CALL_NO_RWG, i128, env, s32)

15
target/sparc/translate.c
View File

@ -276,14 +276,6 @@ static void gen_store_fpr_Q(DisasContext *dc, unsigned int dst, TCGv_i128 v)
gen_update_fprs_dirty(dc, dst);
}
static void gen_op_store_QT0_fpr(unsigned int dst)
{
tcg_gen_ld_i64(cpu_fpr[dst / 2], tcg_env, offsetof(CPUSPARCState, qt0) +
offsetof(CPU_QuadU, ll.upper));
tcg_gen_ld_i64(cpu_fpr[dst/2 + 1], tcg_env, offsetof(CPUSPARCState, qt0) +
offsetof(CPU_QuadU, ll.lower));
}
/* moves */
#ifdef CONFIG_USER_ONLY
#define supervisor(dc) 0
@ -4992,6 +4984,7 @@ TRANS(FDIVq, ALL, do_env_qqq, a, gen_helper_fdivq)
static bool trans_FdMULq(DisasContext *dc, arg_r_r_r *a)
{
TCGv_i64 src1, src2;
TCGv_i128 dst;
if (gen_trap_ifnofpu(dc)) {
return true;
@ -5003,10 +4996,10 @@ static bool trans_FdMULq(DisasContext *dc, arg_r_r_r *a)
gen_op_clear_ieee_excp_and_FTT();
src1 = gen_load_fpr_D(dc, a->rs1);
src2 = gen_load_fpr_D(dc, a->rs2);
gen_helper_fdmulq(tcg_env, src1, src2);
dst = tcg_temp_new_i128();
gen_helper_fdmulq(dst, tcg_env, src1, src2);
gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env);
gen_op_store_QT0_fpr(QFPREG(a->rd));
gen_update_fprs_dirty(dc, QFPREG(a->rd));
gen_store_fpr_Q(dc, a->rd, dst);
return advance_pc(dc);
}